* [PATCH v6 03/05] clk: shmobile: Make MSTP clock-output-names optional
2015-09-02 7:16 [PATCH v6 00/05] Renesas R-Car Gen3 CPG support V6 Magnus Damm
2015-09-02 7:17 ` [PATCH v6 01/05] clk: shmobile: Rework CONFIG_ARCH_SHMOBILE_MULTI Magnus Damm
2015-09-02 7:17 ` [PATCH v6 02/05] clk: shmobile: Add r8a7795 SoC to MSTP bindings Magnus Damm
@ 2015-09-02 7:17 ` Magnus Damm
2015-09-02 11:23 ` Sergei Shtylyov
2015-09-02 11:26 ` Sergei Shtylyov
2015-09-02 7:17 ` [PATCH v6 04/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support Magnus Damm
` (2 subsequent siblings)
5 siblings, 2 replies; 11+ messages in thread
From: Magnus Damm @ 2015-09-02 7:17 UTC (permalink / raw)
To: linux-clk
Cc: kuninori.morimoto.gx, linux-sh, mturquette, gaku.inami.xw, sboyd,
horms, geert, laurent.pinchart, Magnus Damm
From: Magnus Damm <damm+renesas@opensource.se>
This patch updates the MSTP driver to make the "clock-output-names"
DT property optional instead of mandatory. In case the DT property
is omitted then the function clk_register_clkdev() is skipped.
The default for new SoCs is to not use "clock-output-names".
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---
Changes since V5:
- Simplified code using const char *allocated_name - thanks Geert!
Changes since V4:
- None
Changes since V3:
- Added support for multiple MSTP bits. =)
drivers/clk/shmobile/clk-mstp.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
--- 0001/drivers/clk/shmobile/clk-mstp.c
+++ work/drivers/clk/shmobile/clk-mstp.c 2015-09-02 11:52:02.182366518 +0900
@@ -193,26 +193,26 @@ static void __init cpg_mstp_clocks_init(
for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
const char *parent_name;
const char *name;
+ const char *allocated_name = NULL;
u32 clkidx;
int ret;
- /* Skip clocks with no name. */
- ret = of_property_read_string_index(np, "clock-output-names",
- i, &name);
- if (ret < 0 || strlen(name) = 0)
- continue;
-
parent_name = of_clk_get_parent_name(np, i);
ret = of_property_read_u32_index(np, idxname, i, &clkidx);
if (parent_name = NULL || ret < 0)
break;
if (clkidx >= MSTP_MAX_CLOCKS) {
- pr_err("%s: invalid clock %s %s index %u)\n",
- __func__, np->name, name, clkidx);
+ pr_err("%s: invalid clock %s index %u)\n",
+ __func__, np->name, clkidx);
continue;
}
+ if (of_property_read_string_index(np, "clock-output-names",
+ i, &name) < 0)
+ allocated_name = name = kasprintf(GFP_KERNEL, "%s.%u",
+ np->name, clkidx);
+
clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
clkidx, group);
if (!IS_ERR(clks[clkidx])) {
@@ -225,12 +225,18 @@ static void __init cpg_mstp_clocks_init(
*
* FIXME: Remove this when all devices that require a
* clock will be instantiated from DT.
+ *
+ * We currently register clkdev only when the DT
+ * property clock-output-names is present.
*/
- clk_register_clkdev(clks[clkidx], name, NULL);
+ if (!allocated_name)
+ clk_register_clkdev(clks[clkidx], name, NULL);
} else {
pr_err("%s: failed to register %s %s clock (%ld)\n",
__func__, np->name, name, PTR_ERR(clks[clkidx]));
}
+
+ kfree(allocated_name);
}
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v6 04/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support
2015-09-02 7:16 [PATCH v6 00/05] Renesas R-Car Gen3 CPG support V6 Magnus Damm
` (2 preceding siblings ...)
2015-09-02 7:17 ` [PATCH v6 03/05] clk: shmobile: Make MSTP clock-output-names optional Magnus Damm
@ 2015-09-02 7:17 ` Magnus Damm
2015-09-02 7:17 ` [PATCH v6 05/05] clk: shmobile: rcar-gen3: Add CPG/MSTP Clock Domain support Magnus Damm
2015-09-02 9:28 ` [PATCH v6 00/05] Renesas R-Car Gen3 CPG support V6 Geert Uytterhoeven
5 siblings, 0 replies; 11+ messages in thread
From: Magnus Damm @ 2015-09-02 7:17 UTC (permalink / raw)
To: linux-clk
Cc: kuninori.morimoto.gx, gaku.inami.xw, mturquette, linux-sh, sboyd,
horms, geert, laurent.pinchart, Magnus Damm
From: Gaku Inami <gaku.inami.xw@bp.renesas.com>
This V6 patch adds initial CPG support for R-Car Generation 3 and in
particular the R8A7795 SoC.
The R-Car Gen3 clock hardware has a register write protection feature that
needs to be shared between the CPG function and the MSTP hardware somehow.
So far this feature is simply ignored.
At this point this driver is considered to be in quite early experimental
state and the inner workings of the code such as boot mode detection as
well as PLL1 and probably other things need to be updated once the friendly
hardware documentation becomes more stable.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---
Changes since V5: (Magnus Damm <damm+renesas@opensource.se>)
- Removed unused spinlock, use 0x3f as mask - thanks Laurent!
- Fixed space -> tab for DT binding documentation - thanks Geert!
- Postponed PLL1 divide-by-2 rewrite - requires a tad more effort.
- Updated commit log
Changes since V4: (Magnus Damm <damm+renesas@opensource.se>)
- Simplified clks array handling - thanks Geert!
- Updated th DT binding documentation to reflect latest state
- of_property_count_strings() -> of_property_count_u32_elems() fix
Changes since V3: (Magnus Damm <damm+renesas@opensource.se>)
- Reworked driver to incorporate most feedback from Stephen Boyd - thanks!!
- Major things like syscon and driver model require more discussion.
- Added hunk to build drivers/clk/shmobile if ARCH_RENESAS is set.
Changes since V2: (Magnus Damm <damm+renesas@opensource.se>)
- Reworked driver to rely on clock index instead of strings.
- Dropped use of "clock-output-names".
Earlier versions: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Initial version: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt | 32 +
drivers/clk/Makefile | 1
drivers/clk/shmobile/Makefile | 1
drivers/clk/shmobile/clk-rcar-gen3.c | 241 ++++++++++
4 files changed, 275 insertions(+)
--- /dev/null
+++ work/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt 2015-09-02 11:58:06.782366518 +0900
@@ -0,0 +1,32 @@
+* Renesas R-Car Gen3 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
+and several fixed ratio dividers.
+
+Required Properties:
+
+ - compatible: Must be one of
+ - "renesas,r8a7795-cpg-clocks" for the r8a7795 CPG
+ - "renesas,rcar-gen3-cpg-clocks" for the generic R-Car Gen3 CPG
+
+ - reg: Base address and length of the memory resource used by the CPG
+
+ - clocks: References to the parent clocks: first to the EXTAL clock
+ - #clock-cells: Must be 1
+ - clock-indices: Indices of the exported clocks
+
+Example
+-------
+
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7795-cpg-clocks",
+ "renesas,rcar-gen3-cpg-clocks";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>;
+ #clock-cells = <1>;
+ clock-indices = <
+ R8A7795_CLK_MAIN R8A7795_CLK_PLL0
+ R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
+ R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
+ >;
+ };
--- 0001/drivers/clk/Makefile
+++ work/drivers/clk/Makefile 2015-09-02 11:56:49.942366518 +0900
@@ -67,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
+obj-$(CONFIG_ARCH_RENESAS) += shmobile/
obj-$(CONFIG_ARCH_SIRF) += sirf/
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/
--- 0006/drivers/clk/shmobile/Makefile
+++ work/drivers/clk/shmobile/Makefile 2015-09-02 11:56:49.942366518 +0900
@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7795) += clk-rcar-gen3.o clk-mstp.o clk-div6.o
obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
--- /dev/null
+++ work/drivers/clk/shmobile/clk-rcar-gen3.c 2015-09-02 14:35:06.302366518 +0900
@@ -0,0 +1,241 @@
+/*
+ * rcar_gen3 Core CPG Clocks
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * Based on rcar_gen2 Core CPG Clocks driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define RCAR_GEN3_CLK_MAIN 0
+#define RCAR_GEN3_CLK_PLL0 1
+#define RCAR_GEN3_CLK_PLL1 2
+#define RCAR_GEN3_CLK_PLL2 3
+#define RCAR_GEN3_CLK_PLL3 4
+#define RCAR_GEN3_CLK_PLL4 5
+#define RCAR_GEN3_CLK_NR 6
+
+static const char * const rcar_gen3_clk_names[RCAR_GEN3_CLK_NR] = {
+ [RCAR_GEN3_CLK_MAIN] = "main",
+ [RCAR_GEN3_CLK_PLL0] = "pll0",
+ [RCAR_GEN3_CLK_PLL1] = "pll1",
+ [RCAR_GEN3_CLK_PLL2] = "pll2",
+ [RCAR_GEN3_CLK_PLL3] = "pll3",
+ [RCAR_GEN3_CLK_PLL4] = "pll4",
+};
+
+struct rcar_gen3_cpg {
+ struct clk_onecell_data data;
+ void __iomem *reg;
+ struct clk *clks[RCAR_GEN3_CLK_NR];
+};
+
+#define CPG_PLL0CR 0x00d8
+#define CPG_PLL2CR 0x002c
+
+/*
+ * common function
+ */
+#define rcar_clk_readl(cpg, _reg) readl(cpg->reg + _reg)
+
+/*
+ * Reset register definitions.
+ */
+#define MODEMR 0xe6160060
+
+static u32 rcar_gen3_read_mode_pins(void)
+{
+ static u32 mode;
+ static bool mode_valid;
+
+ if (!mode_valid) {
+ void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+
+ BUG_ON(!modemr);
+ mode = ioread32(modemr);
+ iounmap(modemr);
+ mode_valid = true;
+ }
+
+ return mode;
+}
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
+ * 14 13 19 17 (MHz) *1 *1 *1
+ *-------------------------------------------------------------------
+ * 0 0 0 0 16.66 x 1 x180/2 x192/2 x144/2 x192 x144
+ * 0 0 0 1 16.66 x 1 x180/2 x192/2 x144/2 x128 x144
+ * 0 0 1 0 Prohibited setting
+ * 0 0 1 1 16.66 x 1 x180/2 x192/2 x144/2 x192 x144
+ * 0 1 0 0 20 x 1 x150/2 x156/2 x120/2 x156 x120
+ * 0 1 0 1 20 x 1 x150/2 x156/2 x120/2 x106 x120
+ * 0 1 1 0 Prohibited setting
+ * 0 1 1 1 20 x 1 x150/2 x156/2 x120/2 x156 x120
+ * 1 0 0 0 25 x 1 x120/2 x128/2 x96/2 x128 x96
+ * 1 0 0 1 25 x 1 x120/2 x128/2 x96/2 x84 x96
+ * 1 0 1 0 Prohibited setting
+ * 1 0 1 1 25 x 1 x120/2 x128/2 x96/2 x128 x96
+ * 1 1 0 0 33.33 / 2 x180/2 x192/2 x144/2 x192 x144
+ * 1 1 0 1 33.33 / 2 x180/2 x192/2 x144/2 x128 x144
+ * 1 1 1 0 Prohibited setting
+ * 1 1 1 1 33.33 / 2 x180/2 x192/2 x144/2 x192 x144
+ *
+ * *1 : datasheet indicates VCO output (PLLx = VCO/2)
+ *
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
+ (((md) & BIT(13)) >> 11) | \
+ (((md) & BIT(19)) >> 18) | \
+ (((md) & BIT(17)) >> 17))
+struct cpg_pll_config {
+ unsigned int extal_div;
+ unsigned int pll1_mult;
+ unsigned int pll3_mult;
+ unsigned int pll4_mult;
+};
+
+static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
+/* EXTAL div PLL1 PLL3 PLL4 */
+ { 1, 192, 192, 144, },
+ { 1, 192, 128, 144, },
+ { 0, 0, 0, 0, }, /* Prohibited setting */
+ { 1, 192, 192, 144, },
+ { 1, 156, 156, 120, },
+ { 1, 156, 106, 120, },
+ { 0, 0, 0, 0, }, /* Prohibited setting */
+ { 1, 156, 156, 120, },
+ { 1, 128, 128, 96, },
+ { 1, 128, 84, 96, },
+ { 0, 0, 0, 0, }, /* Prohibited setting */
+ { 1, 128, 128, 96, },
+ { 2, 192, 192, 144, },
+ { 2, 192, 128, 144, },
+ { 0, 0, 0, 0, }, /* Prohibited setting */
+ { 2, 192, 192, 144, },
+};
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static struct clk * __init
+rcar_gen3_cpg_register_clock(struct device_node *np, struct rcar_gen3_cpg *cpg,
+ const struct cpg_pll_config *config,
+ unsigned int gen3_clk)
+{
+ const char *parent_name = rcar_gen3_clk_names[RCAR_GEN3_CLK_MAIN];
+ unsigned int mult = 1;
+ unsigned int div = 1;
+ u32 value;
+
+ switch (gen3_clk) {
+ case RCAR_GEN3_CLK_MAIN:
+ parent_name = of_clk_get_parent_name(np, 0);
+ div = config->extal_div;
+ break;
+ case RCAR_GEN3_CLK_PLL0:
+ /* PLL0 is a configurable multiplier clock. Register it as a
+ * fixed factor clock for now as there's no generic multiplier
+ * clock implementation and we currently have no need to change
+ * the multiplier value.
+ */
+ value = rcar_clk_readl(cpg, CPG_PLL0CR);
+ mult = ((value >> 24) & 0x3f) + 1;
+ break;
+ case RCAR_GEN3_CLK_PLL1:
+ mult = config->pll1_mult / 2;
+ break;
+ case RCAR_GEN3_CLK_PLL2:
+ /* PLL2 is a configurable multiplier clock. Register it as a
+ * fixed factor clock for now as there's no generic multiplier
+ * clock implementation and we currently have no need to change
+ * the multiplier value.
+ */
+ value = rcar_clk_readl(cpg, CPG_PLL2CR);
+ mult = ((value >> 24) & 0x3f) + 1;
+ break;
+ case RCAR_GEN3_CLK_PLL3:
+ mult = config->pll3_mult;
+ break;
+ case RCAR_GEN3_CLK_PLL4:
+ mult = config->pll4_mult;
+ break;
+ default:
+ return ERR_PTR(-EINVAL);
+ }
+
+ return clk_register_fixed_factor(NULL, rcar_gen3_clk_names[gen3_clk],
+ parent_name, 0, mult, div);
+}
+
+static void __init rcar_gen3_cpg_clocks_init(struct device_node *np)
+{
+ const struct cpg_pll_config *config;
+ struct rcar_gen3_cpg *cpg;
+ u32 cpg_mode;
+ unsigned int i;
+ int num_clks;
+
+ cpg_mode = rcar_gen3_read_mode_pins();
+
+ num_clks = of_property_count_u32_elems(np, "clock-indices");
+ if (num_clks < 0) {
+ pr_err("%s: failed to count clocks\n", __func__);
+ return;
+ }
+
+ cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+ if (!cpg)
+ return;
+
+ cpg->data.clks = cpg->clks;
+ cpg->data.clk_num = num_clks;
+
+ cpg->reg = of_iomap(np, 0);
+ if (WARN_ON(cpg->reg = NULL))
+ return;
+
+ config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+ if (!config->extal_div) {
+ pr_err("%s: Prohibited setting (cpg_mode=0x%x)\n",
+ __func__, cpg_mode);
+ return;
+ }
+
+ for (i = 0; i < num_clks; ++i) {
+ struct clk *clk;
+ u32 idx;
+ int ret;
+
+ ret = of_property_read_u32_index(np, "clock-indices", i, &idx);
+ if (ret < 0)
+ break;
+
+ clk = rcar_gen3_cpg_register_clock(np, cpg, config, idx);
+ if (IS_ERR(clk))
+ pr_err("%s: failed to register %s %u clock (%ld)\n",
+ __func__, np->name, idx, PTR_ERR(clk));
+ else
+ cpg->data.clks[idx] = clk;
+ }
+
+ of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks",
+ rcar_gen3_cpg_clocks_init);
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v6 05/05] clk: shmobile: rcar-gen3: Add CPG/MSTP Clock Domain support
2015-09-02 7:16 [PATCH v6 00/05] Renesas R-Car Gen3 CPG support V6 Magnus Damm
` (3 preceding siblings ...)
2015-09-02 7:17 ` [PATCH v6 04/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support Magnus Damm
@ 2015-09-02 7:17 ` Magnus Damm
2015-09-02 9:28 ` [PATCH v6 00/05] Renesas R-Car Gen3 CPG support V6 Geert Uytterhoeven
5 siblings, 0 replies; 11+ messages in thread
From: Magnus Damm @ 2015-09-02 7:17 UTC (permalink / raw)
To: linux-clk
Cc: kuninori.morimoto.gx, linux-sh, mturquette, gaku.inami.xw, sboyd,
horms, geert, laurent.pinchart, Magnus Damm
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add Clock Domain support to the R-Car Gen3 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---
Changes since V5:
- Rebased to fit on top of updated CPG DT binding document
Changes since V4:
- Rebased to fit on top of updated CPG DT binding document
Changes since V3:
- Fixed so correct file is actually used. =)
- Took V2 from Geert but filtered out Kconfig.platforms bits
Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt | 26 +++++++++-
drivers/clk/shmobile/clk-rcar-gen3.c | 2
2 files changed, 26 insertions(+), 2 deletions(-)
--- 0009/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt
+++ work/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt 2015-09-02 14:41:32.942366518 +0900
@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,9 +16,17 @@ Required Properties:
- clocks: References to the parent clocks: first to the EXTAL clock
- #clock-cells: Must be 1
- clock-indices: Indices of the exported clocks
+ - #power-domain-cells: Must be 0
-Example
--------
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7795-cpg-clocks",
@@ -29,4 +39,16 @@ Example
R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
>;
+ #power-domain-cells = <0>;
+ };
+
+ - CPG/MSTP Clock Domain member device node:
+
+ scif2: serial@e6e88000 {
+ compatible = "renesas,scif-r8a7795", "renesas,scif";
+ reg = <0 0xe6e88000 0 64>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks RCAR_R8A7795_CLK_SCIF2>;
+ clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
};
--- 0009/drivers/clk/shmobile/clk-rcar-gen3.c
+++ work/drivers/clk/shmobile/clk-rcar-gen3.c 2015-09-02 14:39:35.912366518 +0900
@@ -236,6 +236,8 @@ static void __init rcar_gen3_cpg_clocks_
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks",
rcar_gen3_cpg_clocks_init);
^ permalink raw reply [flat|nested] 11+ messages in thread