From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mark Rutland <mark.rutland@arm.com>
Date: Mon, 07 Dec 2015 19:03:55 +0000
Subject: Re: [PATCH v2 6/6] arm64: renesas: r8a7795: Add L2 cache-controller nodes
Message-Id: <20151207190355.GE28024@leverpostej>
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To: linux-arm-kernel@lists.infradead.org

On Mon, Dec 07, 2015 at 06:49:43PM +0000, Sudeep Holla wrote:
> 
> On 07/12/15 18:24, Geert Uytterhoeven wrote:
> >+	L2_CA57: cache-controller@0 {
> >+		compatible = "cache";
> >+		arm,data-latency = <4 4 1>;
> >+		arm,tag-latency = <3 3 3>;
> 
> Interesting, only PL2xx/3xx cache controller driver reads this from the
> DT and configures the controller. The integrated L2 found in
> A15/A7/A57/A53 needs doesn't make use of these values from the DT.

These properties seem to be from l2cc.txt, which really only corresponds
to PL210/PL220/PL310 (and variants) and isn't as generic as it sounds.

I don't see that these are necessary at all.

Thanks,
Mark.