* [PATCH RESEND 01/12] sh: Fix typo
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 02/12] sh: Config update for OF mode Yoshinori Sato
` (10 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
BL is 1 in this time.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/kernel/head_32.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S
index 974bc15..14da954 100644
--- a/arch/sh/kernel/head_32.S
+++ b/arch/sh/kernel/head_32.S
@@ -59,7 +59,7 @@ ENTRY(empty_zero_page)
*/
ENTRY(_stext)
! Initialize Status Register
- mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
+ mov.l 1f, r0 ! MD=1, RB=0, BL=1, IMASK=0xF
ldc r0, sr
! Initialize global interrupt mask
#ifdef CONFIG_CPU_HAS_SR_RB
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 02/12] sh: Config update for OF mode
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 01/12] sh: Fix typo Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 03/12] sh: Disable board specific code in " Yoshinori Sato
` (9 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
DeviceTreee support is use liner IRQ.
And use generic function (clock / io / IRQ).
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/Kconfig | 26 +++++++++++++++++++++++---
arch/sh/boards/Kconfig | 4 ++++
arch/sh/drivers/Makefile | 2 ++
arch/sh/include/asm/io.h | 6 ++++++
arch/sh/kernel/cpu/Makefile | 8 ++++++--
arch/sh/kernel/cpu/clock.c | 9 ++++++---
drivers/sh/Makefile | 2 ++
7 files changed, 49 insertions(+), 8 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 7ed20fc..d4177ba 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -28,7 +28,7 @@ config SUPERH
select ARCH_WANT_IPC_PARSE_VERSION
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_REGS_AND_STACK_ACCESS_API
- select MAY_HAVE_SPARSE_IRQ
+ select MAY_HAVE_SPARSE_IRQ if !SH_DEVICE_TREE
select IRQ_FORCED_THREADING
select RTC_LIB
select GENERIC_ATOMIC64
@@ -66,7 +66,7 @@ config SUPERH32
select HAVE_MIXED_BREAKPOINTS_REGS
select PERF_EVENTS
select ARCH_HIBERNATION_POSSIBLE if MMU
- select SPARSE_IRQ
+ select SPARSE_IRQ if !SH_DEVICE_TREE
select HAVE_CC_STACKPROTECTOR
config SUPERH64
@@ -745,6 +745,26 @@ endmenu
menu "Boot options"
+config USE_BUILTIN_DTB
+ bool "Use builtin DTB"
+ default n
+ depends on SH_DEVICE_TREE
+ help
+ Link a device tree blob for particular hardware into the kernel,
+ suppressing use of the DTB pointer provided by the bootloader.
+ This option should only be used with legacy bootloaders that are
+ not capable of providing a DTB to the kernel, or for experimental
+ hardware without stable device tree bindings.
+
+config BUILTIN_DTB_SOURCE
+ string "Source file for builtin DTB"
+ default ""
+ depends on USE_BUILTIN_DTB
+ help
+ Base name (without suffix, relative to arch/sh/boot/dts) for the
+ a DTS file that will be used to produce the DTB linked into the
+ kernel.
+
config ZERO_PAGE_OFFSET
hex
default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
@@ -839,7 +859,7 @@ config PCI
depends on SYS_SUPPORTS_PCI
select PCI_DOMAINS
select GENERIC_PCI_IOMAP
- select NO_GENERIC_PCI_IOPORT_MAP
+ select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 5e52d53..98f884e 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -12,6 +12,10 @@ config SH_DEVICE_TREE
select OF_EARLY_FLATTREE
select CLKSRC_OF
select GENERIC_CALIBRATE_DELAY
+ select COMMON_CLK
+ select GENERIC_IOMAP
+ select GENERIC_IRQ_CHIP
+ select SYS_SUPPORTS_PCI
help
Select Board Described by Device Tree to build a kernel that
does not hard-code any board-specific knowledge but instead uses
diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile
index e13f06b..382e86f 100644
--- a/arch/sh/drivers/Makefile
+++ b/arch/sh/drivers/Makefile
@@ -4,7 +4,9 @@
obj-y += dma/
+ifndef CONFIG_SH_DEVICE_TREE
obj-$(CONFIG_PCI) += pci/
+endif
obj-$(CONFIG_SUPERHYWAY) += superhyway/
obj-$(CONFIG_PUSH_SWITCH) += push-switch.o
obj-$(CONFIG_HEARTBEAT) += heartbeat.o
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 3280a6b..df62a9f 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -387,6 +387,12 @@ static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+#define PCI_IOBASE 0xfe240000UL
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET PCI_IOBASE
+#define PIO_MASK 0x3ffffUL
+#define PIO_RESERVED 0x40000UL
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index accc7ca..22ad0ee 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -16,6 +16,10 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
# Common interfaces.
obj-$(CONFIG_SH_ADC) += adc.o
+ifndef CONFIG_COMMON_CLK
obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
-
-obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o
+endif
+ifndef CONFIG_GENERIC_IRQ_CHIP
+obj-y += irq/
+endif
+obj-y += init.o clock.o fpu.o pfc.o proc.o
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 4187cf4..856a05c 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -17,19 +17,21 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
+#include <linux/of.h>
#include <asm/clock.h>
#include <asm/machvec.h>
int __init clk_init(void)
{
- int ret;
+ int ret = 0;
+#ifndef CONFIG_COMMON_CLK
ret = arch_clk_init();
if (unlikely(ret)) {
pr_err("%s: CPU clock registration failed.\n", __func__);
return ret;
}
-
+#endif
if (sh_mv.mv_clk_init) {
ret = sh_mv.mv_clk_init();
if (unlikely(ret)) {
@@ -39,12 +41,13 @@ int __init clk_init(void)
}
}
+#ifndef CONFIG_COMMON_CLK
/* Kick the child clocks.. */
recalculate_root_clocks();
/* Enable the necessary init clocks */
clk_enable_init_clocks();
-
+#endif
return ret;
}
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index 114203f..e7888ea 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -1,7 +1,9 @@
#
# Makefile for the SuperH specific drivers.
#
+ifneq ($(CONFIG_RENESAS_SH_INTC),y)
obj-$(CONFIG_SH_INTC) += intc/
+endif
ifneq ($(CONFIG_COMMON_CLK),y)
obj-$(CONFIG_HAVE_CLK) += clk/
endif
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 03/12] sh: Disable board specific code in OF mode
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 01/12] sh: Fix typo Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 02/12] sh: Config update for OF mode Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-04 2:49 ` Rich Felker
2016-05-01 5:08 ` [PATCH RESEND 04/12] sh: Drop CPU specific setup on " Yoshinori Sato
` (8 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
Board specific code conflict on of-generic.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/Makefile | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index bf5b3f5..8ff943b 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -130,6 +130,9 @@ head-y := arch/sh/kernel/head_$(BITS).o
core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
+core-$(CONFIG_USE_BUILTIN_DTB) += arch/sh/boot/dts/
+
+ifneq ($(CONFIG_SH_DEVICE_TREE),y)
# Mach groups
machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se
machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx
@@ -150,6 +153,7 @@ machdir-$(CONFIG_SH_LANDISK) += mach-landisk
machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2
machdir-$(CONFIG_SH_CAYMAN) += mach-cayman
machdir-$(CONFIG_SH_RSK) += mach-rsk
+endif
ifneq ($(machdir-y),)
core-y += $(addprefix arch/sh/boards/, \
@@ -222,6 +226,13 @@ archclean:
$(Q)$(MAKE) $(clean)=$(boot)
$(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall
+%.dtb %.dtb.S %.dtb.o: | scripts
+ $(Q)$(MAKE) $(build)=arch/sh/boot/dts arch/sh/boot/dts/$@
+
+PHONY += dtbs
+dtbs: scripts
+ $(Q)$(MAKE) $(build)=arch/sh/boot/dts
+
define archhelp
@echo ' zImage - Compressed kernel image'
@echo ' romImage - Compressed ROM image, if supported'
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 03/12] sh: Disable board specific code in OF mode
2016-05-01 5:08 ` [PATCH RESEND 03/12] sh: Disable board specific code in " Yoshinori Sato
@ 2016-05-04 2:49 ` Rich Felker
2016-05-10 7:28 ` Yoshinori Sato
0 siblings, 1 reply; 29+ messages in thread
From: Rich Felker @ 2016-05-04 2:49 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, linux-kernel
On Sun, May 01, 2016 at 02:08:27PM +0900, Yoshinori Sato wrote:
> Board specific code conflict on of-generic.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> arch/sh/Makefile | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/sh/Makefile b/arch/sh/Makefile
> index bf5b3f5..8ff943b 100644
> --- a/arch/sh/Makefile
> +++ b/arch/sh/Makefile
> @@ -130,6 +130,9 @@ head-y := arch/sh/kernel/head_$(BITS).o
> core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
> core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
>
> +core-$(CONFIG_USE_BUILTIN_DTB) += arch/sh/boot/dts/
> +
It looks like you inadvertently mixed the builtin-dtb patch with this
commit. Is yours based on the builtin-dtb patch I posted to the list
or a different approach?
> +ifneq ($(CONFIG_SH_DEVICE_TREE),y)
> # Mach groups
> machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se
> machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx
> @@ -150,6 +153,7 @@ machdir-$(CONFIG_SH_LANDISK) += mach-landisk
> machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2
> machdir-$(CONFIG_SH_CAYMAN) += mach-cayman
> machdir-$(CONFIG_SH_RSK) += mach-rsk
> +endif
Is this actually necessary? I thought SH_DEVICE_TREE was mutually
exclusive with board-specific configs at the Kconfig level. If not, it
should probably be handled that way rather than with logic like this
in the Makefile.
> ifneq ($(machdir-y),)
> core-y += $(addprefix arch/sh/boards/, \
> @@ -222,6 +226,13 @@ archclean:
> $(Q)$(MAKE) $(clean)=$(boot)
> $(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall
>
> +%.dtb %.dtb.S %.dtb.o: | scripts
> + $(Q)$(MAKE) $(build)=arch/sh/boot/dts arch/sh/boot/dts/$@
> +
> +PHONY += dtbs
> +dtbs: scripts
> + $(Q)$(MAKE) $(build)=arch/sh/boot/dts
> +
> define archhelp
> @echo ' zImage - Compressed kernel image'
> @echo ' romImage - Compressed ROM image, if supported'
> --
More builtin-dtb stuff.
Rich
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH RESEND 03/12] sh: Disable board specific code in OF mode
2016-05-04 2:49 ` Rich Felker
@ 2016-05-10 7:28 ` Yoshinori Sato
0 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-10 7:28 UTC (permalink / raw)
To: Rich Felker; +Cc: linux-sh, linux-kernel
Sorry too late reply.
On Wed, 04 May 2016 11:49:41 +0900,
Rich Felker wrote:
>
> On Sun, May 01, 2016 at 02:08:27PM +0900, Yoshinori Sato wrote:
> > Board specific code conflict on of-generic.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> > arch/sh/Makefile | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/sh/Makefile b/arch/sh/Makefile
> > index bf5b3f5..8ff943b 100644
> > --- a/arch/sh/Makefile
> > +++ b/arch/sh/Makefile
> > @@ -130,6 +130,9 @@ head-y := arch/sh/kernel/head_$(BITS).o
> > core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
> > core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
> >
> > +core-$(CONFIG_USE_BUILTIN_DTB) += arch/sh/boot/dts/
> > +
>
> It looks like you inadvertently mixed the builtin-dtb patch with this
> commit. Is yours based on the builtin-dtb patch I posted to the list
> or a different approach?
Oh sorry.
It changes same. I mistake origin version.
> > +ifneq ($(CONFIG_SH_DEVICE_TREE),y)
> > # Mach groups
> > machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se
> > machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx
> > @@ -150,6 +153,7 @@ machdir-$(CONFIG_SH_LANDISK) += mach-landisk
> > machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2
> > machdir-$(CONFIG_SH_CAYMAN) += mach-cayman
> > machdir-$(CONFIG_SH_RSK) += mach-rsk
> > +endif
>
> Is this actually necessary? I thought SH_DEVICE_TREE was mutually
> exclusive with board-specific configs at the Kconfig level. If not, it
> should probably be handled that way rather than with logic like this
> in the Makefile.
Hmm.
I think Kconfig level exclsive more better.
>
> > ifneq ($(machdir-y),)
> > core-y += $(addprefix arch/sh/boards/, \
> > @@ -222,6 +226,13 @@ archclean:
> > $(Q)$(MAKE) $(clean)=$(boot)
> > $(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall
> >
> > +%.dtb %.dtb.S %.dtb.o: | scripts
> > + $(Q)$(MAKE) $(build)=arch/sh/boot/dts arch/sh/boot/dts/$@
> > +
> > +PHONY += dtbs
> > +dtbs: scripts
> > + $(Q)$(MAKE) $(build)=arch/sh/boot/dts
> > +
> > define archhelp
> > @echo ' zImage - Compressed kernel image'
> > @echo ' romImage - Compressed ROM image, if supported'
> > --
>
> More builtin-dtb stuff.
>
> Rich
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH RESEND 04/12] sh: Drop CPU specific setup on OF mode
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (2 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 03/12] sh: Disable board specific code in " Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 05/12] sh: DeviceTree support update Yoshinori Sato
` (7 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
CPU specific set conflict of-generic.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/kernel/cpu/sh4/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 3a1dbc7..b822c0c 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -14,6 +14,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o
+ifndef CONFIG_OF
# CPU subtype setup
obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -31,6 +32,7 @@ endif
# Additional clocks by subtype
clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
+endif
obj-y += $(clock-y)
obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (3 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 04/12] sh: Drop CPU specific setup on " Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-04 3:10 ` Rich Felker
2016-05-01 5:08 ` [PATCH RESEND 06/12] clk: sh: SH7750/51 PLL and divider clock driver Yoshinori Sato
` (6 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
Changes bellow
- FDT setup timing fix.
- chosen/bootargs support.
- zImage support.
- DT binding helper macro.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boards/of-generic.c | 23 +++++++++++-----------
arch/sh/boot/compressed/head_32.S | 5 +++--
arch/sh/boot/dts/include/dt-bindings | 1 +
arch/sh/kernel/setup.c | 19 ++++++++++++++++++
include/dt-bindings/interrupt-controller/sh_intc.h | 2 ++
5 files changed, 36 insertions(+), 14 deletions(-)
create mode 120000 arch/sh/boot/dts/include/dt-bindings
create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index bf3a166..9570873 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -112,29 +112,25 @@ static int noopi(void)
return 0;
}
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
}
-static void __init sh_of_time_init(void)
-{
- pr_info("SH generic board support: scanning for clocksource devices\n");
- clocksource_probe();
-}
-
static void __init sh_of_setup(char **cmdline_p)
{
- unflatten_device_tree();
-
- board_time_init = sh_of_time_init;
+ struct device_node *cpu;
+ int freq;
sh_mv.mv_name = of_flat_dt_get_machine_name();
if (!sh_mv.mv_name)
sh_mv.mv_name = "Unknown SH model";
sh_of_smp_probe();
+ cpu = of_find_node_by_name(NULL, "cpu");
+ if (!of_property_read_u32(cpu, "clock-frequency", &freq))
+ preset_lpj = freq / 500;
}
static int sh_of_irq_demux(int irq)
@@ -167,8 +163,7 @@ static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_init_irq = sh_of_init_irq,
.mv_clk_init = sh_of_clk_init,
.mv_mode_pins = noopi,
- .mv_mem_init = noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mem_init = sh_of_mem_init,
};
struct sh_clk_ops;
@@ -194,3 +189,7 @@ static int __init sh_of_device_init(void)
return 0;
}
arch_initcall_sync(sh_of_device_init);
+
+void intc_finalize(void)
+{
+}
diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 3e15032..cd34377 100644
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -14,7 +14,8 @@ startup:
/* Load initial status register */
mov.l init_sr, r1
ldc r1, sr
-
+ /* Save FDT address */
+ mov r4, r13
/* Move myself to proper location if necessary */
mova 1f, r0
mov.l 1f, r2
@@ -83,7 +84,7 @@ l1:
/* Jump to the start of the decompressed kernel */
mov.l kernel_start_addr, r0
jmp @r0
- nop
+ mov r13,r4
.align 2
bss_start_addr:
diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
new file mode 120000
index 0000000..08c00e4
--- /dev/null
+++ b/arch/sh/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 5d34605..f6bb105 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -177,7 +177,12 @@ disable:
#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
void calibrate_delay(void)
{
+#ifndef CONFIG_OF
struct clk *clk = clk_get(NULL, "cpu_clk");
+#else
+ struct device_node *cpu = of_find_node_by_name(NULL, "cpu");
+ struct clk *clk = of_clk_get_by_name(cpu, NULL);
+#endif
if (IS_ERR(clk))
panic("Need a sane CPU clock definition!");
@@ -251,7 +256,11 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
/* Avoid calling an __init function on secondary cpus. */
if (done) return;
+#ifdef CONFIG_USE_BUILTIN_DTB
+ dt_virt = __dtb_start;
+#else
dt_virt = phys_to_virt(dt_phys);
+#endif
if (!dt_virt || !early_init_dt_scan(dt_virt)) {
pr_crit("Error: invalid device tree blob"
@@ -267,8 +276,13 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#ifdef CONFIG_OF
+ unflatten_device_tree();
+#endif
enable_mmu();
+
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -290,6 +304,7 @@ void __init setup_arch(char **cmdline_p)
if (!MOUNT_ROOT_RDONLY)
root_mountflags &= ~MS_RDONLY;
+#endif
init_mm.start_code = (unsigned long) _text;
init_mm.end_code = (unsigned long) _etext;
init_mm.end_data = (unsigned long) _edata;
@@ -312,9 +327,13 @@ void __init setup_arch(char **cmdline_p)
#endif
#endif
+#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
/* Save unparsed command line copy for /proc/cmdline */
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
+#else
+ *cmdline_p = boot_command_line;
+#endif
parse_early_param();
diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
new file mode 100644
index 0000000..8c9dcdc
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/sh_intc.h
@@ -0,0 +1,2 @@
+#define evt2irq(evt) (((evt) >> 5) - 16)
+#define irq2evt(irq) (((irq) + 16) << 5)
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-01 5:08 ` [PATCH RESEND 05/12] sh: DeviceTree support update Yoshinori Sato
@ 2016-05-04 3:10 ` Rich Felker
2016-05-04 6:41 ` Geert Uytterhoeven
2016-05-10 8:25 ` Yoshinori Sato
0 siblings, 2 replies; 29+ messages in thread
From: Rich Felker @ 2016-05-04 3:10 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, linux-kernel
On Sun, May 01, 2016 at 02:08:29PM +0900, Yoshinori Sato wrote:
> Changes bellow
> - FDT setup timing fix.
> - chosen/bootargs support.
> - zImage support.
> - DT binding helper macro.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> arch/sh/boards/of-generic.c | 23 +++++++++++-----------
> arch/sh/boot/compressed/head_32.S | 5 +++--
> arch/sh/boot/dts/include/dt-bindings | 1 +
> arch/sh/kernel/setup.c | 19 ++++++++++++++++++
> include/dt-bindings/interrupt-controller/sh_intc.h | 2 ++
> 5 files changed, 36 insertions(+), 14 deletions(-)
> create mode 120000 arch/sh/boot/dts/include/dt-bindings
> create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
>
> diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
> index bf3a166..9570873 100644
> --- a/arch/sh/boards/of-generic.c
> +++ b/arch/sh/boards/of-generic.c
> @@ -112,29 +112,25 @@ static int noopi(void)
> return 0;
> }
>
> -static void __init sh_of_mem_reserve(void)
> +static void __init sh_of_mem_init(void)
> {
> early_init_fdt_reserve_self();
> early_init_fdt_scan_reserved_mem();
> }
>
> -static void __init sh_of_time_init(void)
> -{
> - pr_info("SH generic board support: scanning for clocksource devices\n");
> - clocksource_probe();
> -}
Why did you remove this? Without it you won't get clock
event/clocksource devices from the device tree so the only way to have
a working timer interrupt is if the driver is hard-coded somewhere.
> static void __init sh_of_setup(char **cmdline_p)
> {
> - unflatten_device_tree();
> -
> - board_time_init = sh_of_time_init;
> + struct device_node *cpu;
> + int freq;
>
> sh_mv.mv_name = of_flat_dt_get_machine_name();
> if (!sh_mv.mv_name)
> sh_mv.mv_name = "Unknown SH model";
>
> sh_of_smp_probe();
> + cpu = of_find_node_by_name(NULL, "cpu");
> + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
> + preset_lpj = freq / 500;
> }
I setup the DT-based pseudo-board to use the generic calibrate-delay
rather than hard-coding lpj. Ideally we could just get rid of bogomips
completely but there are probably still some things using it. Is there
a reason you prefer making up a value for lpj based on the cpu clock
rate?
> static int sh_of_irq_demux(int irq)
> @@ -167,8 +163,7 @@ static struct sh_machine_vector __initmv sh_of_generic_mv = {
> .mv_init_irq = sh_of_init_irq,
> .mv_clk_init = sh_of_clk_init,
> .mv_mode_pins = noopi,
> - .mv_mem_init = noop,
> - .mv_mem_reserve = sh_of_mem_reserve,
> + .mv_mem_init = sh_of_mem_init,
Is there a reason for this renaming? The function seems to be dealing
purely with reserving memory ranges.
> struct sh_clk_ops;
> @@ -194,3 +189,7 @@ static int __init sh_of_device_init(void)
> return 0;
> }
> arch_initcall_sync(sh_of_device_init);
> +
> +void intc_finalize(void)
> +{
> +}
> diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
> index 3e15032..cd34377 100644
> --- a/arch/sh/boot/compressed/head_32.S
> +++ b/arch/sh/boot/compressed/head_32.S
> @@ -14,7 +14,8 @@ startup:
> /* Load initial status register */
> mov.l init_sr, r1
> ldc r1, sr
> -
> + /* Save FDT address */
> + mov r4, r13
> /* Move myself to proper location if necessary */
> mova 1f, r0
> mov.l 1f, r2
> @@ -83,7 +84,7 @@ l1:
> /* Jump to the start of the decompressed kernel */
> mov.l kernel_start_addr, r0
> jmp @r0
> - nop
> + mov r13,r4
>
> .align 2
> bss_start_addr:
This should probably be its own patch, adding DT support for
compressed kernel images. It's independent from everything else in
this patch.
> diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
> new file mode 120000
> index 0000000..08c00e4
> --- /dev/null
> +++ b/arch/sh/boot/dts/include/dt-bindings
> @@ -0,0 +1 @@
> +../../../../../include/dt-bindings
> \ No newline at end of file
> diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
> index 5d34605..f6bb105 100644
> --- a/arch/sh/kernel/setup.c
> +++ b/arch/sh/kernel/setup.c
> @@ -177,7 +177,12 @@ disable:
> #ifndef CONFIG_GENERIC_CALIBRATE_DELAY
> void calibrate_delay(void)
> {
> +#ifndef CONFIG_OF
> struct clk *clk = clk_get(NULL, "cpu_clk");
> +#else
> + struct device_node *cpu = of_find_node_by_name(NULL, "cpu");
> + struct clk *clk = of_clk_get_by_name(cpu, NULL);
> +#endif
>
> if (IS_ERR(clk))
> panic("Need a sane CPU clock definition!");
> @@ -251,7 +256,11 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
> /* Avoid calling an __init function on secondary cpus. */
> if (done) return;
>
> +#ifdef CONFIG_USE_BUILTIN_DTB
> + dt_virt = __dtb_start;
> +#else
> dt_virt = phys_to_virt(dt_phys);
> +#endif
This is also part of the bultin-dtb patch, which seems to have been
spread out across several of your patches.
> if (!dt_virt || !early_init_dt_scan(dt_virt)) {
> pr_crit("Error: invalid device tree blob"
> @@ -267,8 +276,13 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
>
> void __init setup_arch(char **cmdline_p)
> {
> +#ifdef CONFIG_OF
> + unflatten_device_tree();
> +#endif
> enable_mmu();
Was this moved to setup_arch to have it before enable_mmu? I think
that makes sense.
> +#ifndef CONFIG_OF
> ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
>
> printk(KERN_NOTICE "Boot params:\n"
> @@ -290,6 +304,7 @@ void __init setup_arch(char **cmdline_p)
>
> if (!MOUNT_ROOT_RDONLY)
> root_mountflags &= ~MS_RDONLY;
> +#endif
Do these boot params only make sense for non-DT setups?
> +#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
> /* Save unparsed command line copy for /proc/cmdline */
> memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
> *cmdline_p = command_line;
> +#else
> + *cmdline_p = boot_command_line;
> +#endif
I think this is wrong -- it causes the builtin command line and
bootloader-provided command line to be ignored on DT kernels. Do you
just want to deprecate builtin and bootloader-provided command lines?
Or is it just a side effect of adding support for chosen/bootarg?
> parse_early_param();
>
> diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
> new file mode 100644
> index 0000000..8c9dcdc
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> @@ -0,0 +1,2 @@
> +#define evt2irq(evt) (((evt) >> 5) - 16)
> +#define irq2evt(irq) (((irq) + 16) << 5)
This seems unrelated to other things in this patch.
Rich
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-04 3:10 ` Rich Felker
@ 2016-05-04 6:41 ` Geert Uytterhoeven
2016-05-10 8:27 ` Yoshinori Sato
2016-05-10 8:25 ` Yoshinori Sato
1 sibling, 1 reply; 29+ messages in thread
From: Geert Uytterhoeven @ 2016-05-04 6:41 UTC (permalink / raw)
To: Rich Felker; +Cc: Yoshinori Sato, Linux-sh list, linux-kernel@vger.kernel.org
On Wed, May 4, 2016 at 5:10 AM, Rich Felker <dalias@libc.org> wrote:
>On Sun, May 01, 2016 at 02:08:29PM +0900, Yoshinori Sato wrote:
>> static void __init sh_of_setup(char **cmdline_p)
>> {
>> - unflatten_device_tree();
>> -
>> - board_time_init = sh_of_time_init;
>> + struct device_node *cpu;
>> + int freq;
You better make freq unsigned.
>> sh_mv.mv_name = of_flat_dt_get_machine_name();
>> if (!sh_mv.mv_name)
>> sh_mv.mv_name = "Unknown SH model";
>>
>> sh_of_smp_probe();
>> + cpu = of_find_node_by_name(NULL, "cpu");
>> + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
>> + preset_lpj = freq / 500;
>> }
>
> I setup the DT-based pseudo-board to use the generic calibrate-delay
> rather than hard-coding lpj. Ideally we could just get rid of bogomips
> completely but there are probably still some things using it. Is there
> a reason you prefer making up a value for lpj based on the cpu clock
> rate?
Calibrating the delay loop takes some time.
However, you shouldn't hardcode 500, but take HZ into account.
I assume you used the default HZ%0, so
preset_lpj = freq / HZ / 2;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-04 6:41 ` Geert Uytterhoeven
@ 2016-05-10 8:27 ` Yoshinori Sato
0 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-10 8:27 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rich Felker, Linux-sh list, linux-kernel@vger.kernel.org
On Wed, 04 May 2016 15:41:18 +0900,
Geert Uytterhoeven wrote:
>
> On Wed, May 4, 2016 at 5:10 AM, Rich Felker <dalias@libc.org> wrote:
> >On Sun, May 01, 2016 at 02:08:29PM +0900, Yoshinori Sato wrote:
> >> static void __init sh_of_setup(char **cmdline_p)
> >> {
> >> - unflatten_device_tree();
> >> -
> >> - board_time_init = sh_of_time_init;
> >> + struct device_node *cpu;
> >> + int freq;
>
> You better make freq unsigned.
OK.
> >> sh_mv.mv_name = of_flat_dt_get_machine_name();
> >> if (!sh_mv.mv_name)
> >> sh_mv.mv_name = "Unknown SH model";
> >>
> >> sh_of_smp_probe();
> >> + cpu = of_find_node_by_name(NULL, "cpu");
> >> + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
> >> + preset_lpj = freq / 500;
> >> }
> >
> > I setup the DT-based pseudo-board to use the generic calibrate-delay
> > rather than hard-coding lpj. Ideally we could just get rid of bogomips
> > completely but there are probably still some things using it. Is there
> > a reason you prefer making up a value for lpj based on the cpu clock
> > rate?
>
> Calibrating the delay loop takes some time.
> However, you shouldn't hardcode 500, but take HZ into account.
> I assume you used the default HZ%0, so
That's right.
I'll fix it.
> preset_lpj = freq / HZ / 2;
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-04 3:10 ` Rich Felker
2016-05-04 6:41 ` Geert Uytterhoeven
@ 2016-05-10 8:25 ` Yoshinori Sato
2016-05-10 16:28 ` Rich Felker
1 sibling, 1 reply; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-10 8:25 UTC (permalink / raw)
To: Rich Felker; +Cc: linux-sh, linux-kernel
On Wed, 04 May 2016 12:10:05 +0900,
Rich Felker wrote:
>
> On Sun, May 01, 2016 at 02:08:29PM +0900, Yoshinori Sato wrote:
> > Changes bellow
> > - FDT setup timing fix.
> > - chosen/bootargs support.
> > - zImage support.
> > - DT binding helper macro.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> > arch/sh/boards/of-generic.c | 23 +++++++++++-----------
> > arch/sh/boot/compressed/head_32.S | 5 +++--
> > arch/sh/boot/dts/include/dt-bindings | 1 +
> > arch/sh/kernel/setup.c | 19 ++++++++++++++++++
> > include/dt-bindings/interrupt-controller/sh_intc.h | 2 ++
> > 5 files changed, 36 insertions(+), 14 deletions(-)
> > create mode 120000 arch/sh/boot/dts/include/dt-bindings
> > create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
> >
> > diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
> > index bf3a166..9570873 100644
> > --- a/arch/sh/boards/of-generic.c
> > +++ b/arch/sh/boards/of-generic.c
> > @@ -112,29 +112,25 @@ static int noopi(void)
> > return 0;
> > }
> >
> > -static void __init sh_of_mem_reserve(void)
> > +static void __init sh_of_mem_init(void)
> > {
> > early_init_fdt_reserve_self();
> > early_init_fdt_scan_reserved_mem();
> > }
> >
> > -static void __init sh_of_time_init(void)
> > -{
> > - pr_info("SH generic board support: scanning for clocksource devices\n");
> > - clocksource_probe();
> > -}
>
> Why did you remove this? Without it you won't get clock
> event/clocksource devices from the device tree so the only way to have
> a working timer interrupt is if the driver is hard-coded somewhere.
It not needed on Common Clock Framework.
tmu define in dts.
> > static void __init sh_of_setup(char **cmdline_p)
> > {
> > - unflatten_device_tree();
> > -
> > - board_time_init = sh_of_time_init;
> > + struct device_node *cpu;
> > + int freq;
> >
> > sh_mv.mv_name = of_flat_dt_get_machine_name();
> > if (!sh_mv.mv_name)
> > sh_mv.mv_name = "Unknown SH model";
> >
> > sh_of_smp_probe();
> > + cpu = of_find_node_by_name(NULL, "cpu");
> > + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
> > + preset_lpj = freq / 500;
> > }
>
> I setup the DT-based pseudo-board to use the generic calibrate-delay
> rather than hard-coding lpj. Ideally we could just get rid of bogomips
> completely but there are probably still some things using it. Is there
> a reason you prefer making up a value for lpj based on the cpu clock
> rate?
clockevent initalize after calibrate delay.
So don't work interrupt based calibrate.
> > static int sh_of_irq_demux(int irq)
> > @@ -167,8 +163,7 @@ static struct sh_machine_vector __initmv sh_of_generic_mv = {
> > .mv_init_irq = sh_of_init_irq,
> > .mv_clk_init = sh_of_clk_init,
> > .mv_mode_pins = noopi,
> > - .mv_mem_init = noop,
> > - .mv_mem_reserve = sh_of_mem_reserve,
> > + .mv_mem_init = sh_of_mem_init,
>
> Is there a reason for this renaming? The function seems to be dealing
> purely with reserving memory ranges.
mv_mem_reserve too late call in MMU system.
>
> > struct sh_clk_ops;
> > @@ -194,3 +189,7 @@ static int __init sh_of_device_init(void)
> > return 0;
> > }
> > arch_initcall_sync(sh_of_device_init);
> > +
> > +void intc_finalize(void)
> > +{
> > +}
> > diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
> > index 3e15032..cd34377 100644
> > --- a/arch/sh/boot/compressed/head_32.S
> > +++ b/arch/sh/boot/compressed/head_32.S
> > @@ -14,7 +14,8 @@ startup:
> > /* Load initial status register */
> > mov.l init_sr, r1
> > ldc r1, sr
> > -
> > + /* Save FDT address */
> > + mov r4, r13
> > /* Move myself to proper location if necessary */
> > mova 1f, r0
> > mov.l 1f, r2
> > @@ -83,7 +84,7 @@ l1:
> > /* Jump to the start of the decompressed kernel */
> > mov.l kernel_start_addr, r0
> > jmp @r0
> > - nop
> > + mov r13,r4
> >
> > .align 2
> > bss_start_addr:
>
> This should probably be its own patch, adding DT support for
> compressed kernel images. It's independent from everything else in
> this patch.
OK. separated.
> > diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
> > new file mode 120000
> > index 0000000..08c00e4
> > --- /dev/null
> > +++ b/arch/sh/boot/dts/include/dt-bindings
> > @@ -0,0 +1 @@
> > +../../../../../include/dt-bindings
> > \ No newline at end of file
> > diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
> > index 5d34605..f6bb105 100644
> > --- a/arch/sh/kernel/setup.c
> > +++ b/arch/sh/kernel/setup.c
> > @@ -177,7 +177,12 @@ disable:
> > #ifndef CONFIG_GENERIC_CALIBRATE_DELAY
> > void calibrate_delay(void)
> > {
> > +#ifndef CONFIG_OF
> > struct clk *clk = clk_get(NULL, "cpu_clk");
> > +#else
> > + struct device_node *cpu = of_find_node_by_name(NULL, "cpu");
> > + struct clk *clk = of_clk_get_by_name(cpu, NULL);
> > +#endif
> >
> > if (IS_ERR(clk))
> > panic("Need a sane CPU clock definition!");
> > @@ -251,7 +256,11 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
> > /* Avoid calling an __init function on secondary cpus. */
> > if (done) return;
> >
> > +#ifdef CONFIG_USE_BUILTIN_DTB
> > + dt_virt = __dtb_start;
> > +#else
> > dt_virt = phys_to_virt(dt_phys);
> > +#endif
>
> This is also part of the bultin-dtb patch, which seems to have been
> spread out across several of your patches.
Sorry. It my mistake.
> > if (!dt_virt || !early_init_dt_scan(dt_virt)) {
> > pr_crit("Error: invalid device tree blob"
> > @@ -267,8 +276,13 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
> >
> > void __init setup_arch(char **cmdline_p)
> > {
> > +#ifdef CONFIG_OF
> > + unflatten_device_tree();
> > +#endif
> > enable_mmu();
>
> Was this moved to setup_arch to have it before enable_mmu? I think
> that makes sense.
early_init_dt_alloc_memory_arch used physical address.
It override on sh-specific, can after enable_mmu.
But I don't feel an advantage.
> > +#ifndef CONFIG_OF
> > ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
> >
> > printk(KERN_NOTICE "Boot params:\n"
> > @@ -290,6 +304,7 @@ void __init setup_arch(char **cmdline_p)
> >
> > if (!MOUNT_ROOT_RDONLY)
> > root_mountflags &= ~MS_RDONLY;
> > +#endif
>
> Do these boot params only make sense for non-DT setups?
>
> > +#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
> > /* Save unparsed command line copy for /proc/cmdline */
> > memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
> > *cmdline_p = command_line;
> > +#else
> > + *cmdline_p = boot_command_line;
> > +#endif
>
> I think this is wrong -- it causes the builtin command line and
> bootloader-provided command line to be ignored on DT kernels. Do you
> just want to deprecate builtin and bootloader-provided command lines?
> Or is it just a side effect of adding support for chosen/bootarg?
Yes. I think zero-page passing only non-DT.
DT using chosen/bootargs.
> > parse_early_param();
> >
> > diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
> > new file mode 100644
> > index 0000000..8c9dcdc
> > --- /dev/null
> > +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> > @@ -0,0 +1,2 @@
> > +#define evt2irq(evt) (((evt) >> 5) - 16)
> > +#define irq2evt(irq) (((irq) + 16) << 5)
>
> This seems unrelated to other things in this patch.
It using DT define.
> Rich
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-10 8:25 ` Yoshinori Sato
@ 2016-05-10 16:28 ` Rich Felker
2016-05-16 7:36 ` Yoshinori Sato
0 siblings, 1 reply; 29+ messages in thread
From: Rich Felker @ 2016-05-10 16:28 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, linux-kernel
On Tue, May 10, 2016 at 05:25:36PM +0900, Yoshinori Sato wrote:
> On Wed, 04 May 2016 12:10:05 +0900,
> Rich Felker wrote:
> >
> > On Sun, May 01, 2016 at 02:08:29PM +0900, Yoshinori Sato wrote:
> > > Changes bellow
> > > - FDT setup timing fix.
> > > - chosen/bootargs support.
> > > - zImage support.
> > > - DT binding helper macro.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > > ---
> > > arch/sh/boards/of-generic.c | 23 +++++++++++-----------
> > > arch/sh/boot/compressed/head_32.S | 5 +++--
> > > arch/sh/boot/dts/include/dt-bindings | 1 +
> > > arch/sh/kernel/setup.c | 19 ++++++++++++++++++
> > > include/dt-bindings/interrupt-controller/sh_intc.h | 2 ++
> > > 5 files changed, 36 insertions(+), 14 deletions(-)
> > > create mode 120000 arch/sh/boot/dts/include/dt-bindings
> > > create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
> > >
> > > diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
> > > index bf3a166..9570873 100644
> > > --- a/arch/sh/boards/of-generic.c
> > > +++ b/arch/sh/boards/of-generic.c
> > > @@ -112,29 +112,25 @@ static int noopi(void)
> > > return 0;
> > > }
> > >
> > > -static void __init sh_of_mem_reserve(void)
> > > +static void __init sh_of_mem_init(void)
> > > {
> > > early_init_fdt_reserve_self();
> > > early_init_fdt_scan_reserved_mem();
> > > }
> > >
> > > -static void __init sh_of_time_init(void)
> > > -{
> > > - pr_info("SH generic board support: scanning for clocksource devices\n");
> > > - clocksource_probe();
> > > -}
> >
> > Why did you remove this? Without it you won't get clock
> > event/clocksource devices from the device tree so the only way to have
> > a working timer interrupt is if the driver is hard-coded somewhere.
>
> It not needed on Common Clock Framework.
> tmu define in dts.
It is needed. clocksources are something completely different from
"clk"s. A clocksource is the modern source of time data for the kernel
timekeeping system (without one, you're stuck using jiffies and very
low-res time), and the probe also gets clock_event_devices which are
the source of timer interrupts. Without this, unless you have a
hard-coded source of timer interrupt for the board, you won't get a
timer interrupt and the kernel will hang early in the boot process.
> > > static void __init sh_of_setup(char **cmdline_p)
> > > {
> > > - unflatten_device_tree();
> > > -
> > > - board_time_init = sh_of_time_init;
> > > + struct device_node *cpu;
> > > + int freq;
> > >
> > > sh_mv.mv_name = of_flat_dt_get_machine_name();
> > > if (!sh_mv.mv_name)
> > > sh_mv.mv_name = "Unknown SH model";
> > >
> > > sh_of_smp_probe();
> > > + cpu = of_find_node_by_name(NULL, "cpu");
> > > + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
> > > + preset_lpj = freq / 500;
> > > }
> >
> > I setup the DT-based pseudo-board to use the generic calibrate-delay
> > rather than hard-coding lpj. Ideally we could just get rid of bogomips
> > completely but there are probably still some things using it. Is there
> > a reason you prefer making up a value for lpj based on the cpu clock
> > rate?
>
> clockevent initalize after calibrate delay.
> So don't work interrupt based calibrate.
Currently, it initializes before, but you removed the probe that
initializes it (above), clocksource_probe().
> > > static int sh_of_irq_demux(int irq)
> > > @@ -167,8 +163,7 @@ static struct sh_machine_vector __initmv sh_of_generic_mv = {
> > > .mv_init_irq = sh_of_init_irq,
> > > .mv_clk_init = sh_of_clk_init,
> > > .mv_mode_pins = noopi,
> > > - .mv_mem_init = noop,
> > > - .mv_mem_reserve = sh_of_mem_reserve,
> > > + .mv_mem_init = sh_of_mem_init,
> >
> > Is there a reason for this renaming? The function seems to be dealing
> > purely with reserving memory ranges.
>
> mv_mem_reserve too late call in MMU system.
OK.
> > > if (!dt_virt || !early_init_dt_scan(dt_virt)) {
> > > pr_crit("Error: invalid device tree blob"
> > > @@ -267,8 +276,13 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
> > >
> > > void __init setup_arch(char **cmdline_p)
> > > {
> > > +#ifdef CONFIG_OF
> > > + unflatten_device_tree();
> > > +#endif
> > > enable_mmu();
> >
> > Was this moved to setup_arch to have it before enable_mmu? I think
> > that makes sense.
>
> early_init_dt_alloc_memory_arch used physical address.
> It override on sh-specific, can after enable_mmu.
> But I don't feel an advantage.
I dont think we should be putting sh-specific code in
early_init_dt_alloc_memory. If calling unflatten_device_tree before
enable_mmu avoids the need to do that, it seems like the right choice.
Is this how other archs do it? I think we should try to be as
consistent as possible with general practice across the kernel.
> > > +#ifndef CONFIG_OF
> > > ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
> > >
> > > printk(KERN_NOTICE "Boot params:\n"
> > > @@ -290,6 +304,7 @@ void __init setup_arch(char **cmdline_p)
> > >
> > > if (!MOUNT_ROOT_RDONLY)
> > > root_mountflags &= ~MS_RDONLY;
> > > +#endif
> >
> > Do these boot params only make sense for non-DT setups?
> >
> > > +#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
> > > /* Save unparsed command line copy for /proc/cmdline */
> > > memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
> > > *cmdline_p = command_line;
> > > +#else
> > > + *cmdline_p = boot_command_line;
> > > +#endif
> >
> > I think this is wrong -- it causes the builtin command line and
> > bootloader-provided command line to be ignored on DT kernels. Do you
> > just want to deprecate builtin and bootloader-provided command lines?
> > Or is it just a side effect of adding support for chosen/bootarg?
>
> Yes. I think zero-page passing only non-DT.
> DT using chosen/bootargs.
This precludes having the bootloader provide a DTB from ROM, since it
needs to be able to patch the DTB with user preferences, and also
requires DTB-patching code to be added to the bootloader. At the very
least we should retain the ability to have a builtin command line in
the kernel that's appended to the one from the DTB (and possibly allow
the order to be changed), but I think we should also allow the
bootloader to pass in a command line like in the non-DTB setup.
DTB and command line are very different things (hardware description
vs user preference, and OS-generic vs OS-specific) and the whole
chosen/bootargs system is something of a hack.
> > > parse_early_param();
> > >
> > > diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
> > > new file mode 100644
> > > index 0000000..8c9dcdc
> > > --- /dev/null
> > > +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> > > @@ -0,0 +1,2 @@
> > > +#define evt2irq(evt) (((evt) >> 5) - 16)
> > > +#define irq2evt(irq) (((irq) + 16) << 5)
> >
> > This seems unrelated to other things in this patch.
>
> It using DT define.
Ah, I see, it's used later in the dts itself. But why not just put the
actual IRQ numbers in the dts directly? The evt numbers seem like an
implementation detail, whereas device tree bindings should be stable
and independent of kernel sources.
If evt numbers are really what makes sense to have in the dts, then
sh_intc should probably define its irq_domain so that it maps evt
numbers to irq numbers. But that doesn't seem necessary.
Rich
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 05/12] sh: DeviceTree support update
2016-05-10 16:28 ` Rich Felker
@ 2016-05-16 7:36 ` Yoshinori Sato
0 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-16 7:36 UTC (permalink / raw)
To: Rich Felker; +Cc: linux-sh, linux-kernel
On Wed, 11 May 2016 01:28:07 +0900,
Rich Felker wrote:
>
> On Tue, May 10, 2016 at 05:25:36PM +0900, Yoshinori Sato wrote:
> > On Wed, 04 May 2016 12:10:05 +0900,
> > Rich Felker wrote:
> > >
> > > On Sun, May 01, 2016 at 02:08:29PM +0900, Yoshinori Sato wrote:
> > > > Changes bellow
> > > > - FDT setup timing fix.
> > > > - chosen/bootargs support.
> > > > - zImage support.
> > > > - DT binding helper macro.
> > > >
> > > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > > > ---
> > > > arch/sh/boards/of-generic.c | 23 +++++++++++-----------
> > > > arch/sh/boot/compressed/head_32.S | 5 +++--
> > > > arch/sh/boot/dts/include/dt-bindings | 1 +
> > > > arch/sh/kernel/setup.c | 19 ++++++++++++++++++
> > > > include/dt-bindings/interrupt-controller/sh_intc.h | 2 ++
> > > > 5 files changed, 36 insertions(+), 14 deletions(-)
> > > > create mode 120000 arch/sh/boot/dts/include/dt-bindings
> > > > create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
> > > >
> > > > diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
> > > > index bf3a166..9570873 100644
> > > > --- a/arch/sh/boards/of-generic.c
> > > > +++ b/arch/sh/boards/of-generic.c
> > > > @@ -112,29 +112,25 @@ static int noopi(void)
> > > > return 0;
> > > > }
> > > >
> > > > -static void __init sh_of_mem_reserve(void)
> > > > +static void __init sh_of_mem_init(void)
> > > > {
> > > > early_init_fdt_reserve_self();
> > > > early_init_fdt_scan_reserved_mem();
> > > > }
> > > >
> > > > -static void __init sh_of_time_init(void)
> > > > -{
> > > > - pr_info("SH generic board support: scanning for clocksource devices\n");
> > > > - clocksource_probe();
> > > > -}
> > >
> > > Why did you remove this? Without it you won't get clock
> > > event/clocksource devices from the device tree so the only way to have
> > > a working timer interrupt is if the driver is hard-coded somewhere.
> >
> > It not needed on Common Clock Framework.
> > tmu define in dts.
>
> It is needed. clocksources are something completely different from
> "clk"s. A clocksource is the modern source of time data for the kernel
> timekeeping system (without one, you're stuck using jiffies and very
> low-res time), and the probe also gets clock_event_devices which are
> the source of timer interrupts. Without this, unless you have a
> hard-coded source of timer interrupt for the board, you won't get a
> timer interrupt and the kernel will hang early in the boot process.
OK.
> > > > {
> > > > - unflatten_device_tree();
> > > > -
> > > > - board_time_init = sh_of_time_init;
> > > > + struct device_node *cpu;
> > > > + int freq;
> > > >
> > > > sh_mv.mv_name = of_flat_dt_get_machine_name();
> > > > if (!sh_mv.mv_name)
> > > > sh_mv.mv_name = "Unknown SH model";
> > > >
> > > > sh_of_smp_probe();
> > > > + cpu = of_find_node_by_name(NULL, "cpu");
> > > > + if (!of_property_read_u32(cpu, "clock-frequency", &freq))
> > > > + preset_lpj = freq / 500;
> > > > }
> > >
> > > I setup the DT-based pseudo-board to use the generic calibrate-delay
> > > rather than hard-coding lpj. Ideally we could just get rid of bogomips
> > > completely but there are probably still some things using it. Is there
> > > a reason you prefer making up a value for lpj based on the cpu clock
> > > rate?
> >
> > clockevent initalize after calibrate delay.
> > So don't work interrupt based calibrate.
>
> Currently, it initializes before, but you removed the probe that
> initializes it (above), clocksource_probe().
OK.
> > > > static int sh_of_irq_demux(int irq)
> > > > @@ -167,8 +163,7 @@ static struct sh_machine_vector __initmv sh_of_generic_mv = {
> > > > .mv_init_irq = sh_of_init_irq,
> > > > .mv_clk_init = sh_of_clk_init,
> > > > .mv_mode_pins = noopi,
> > > > - .mv_mem_init = noop,
> > > > - .mv_mem_reserve = sh_of_mem_reserve,
> > > > + .mv_mem_init = sh_of_mem_init,
> > >
> > > Is there a reason for this renaming? The function seems to be dealing
> > > purely with reserving memory ranges.
> >
> > mv_mem_reserve too late call in MMU system.
>
> OK.
>
> > > > if (!dt_virt || !early_init_dt_scan(dt_virt)) {
> > > > pr_crit("Error: invalid device tree blob"
> > > > @@ -267,8 +276,13 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
> > > >
> > > > void __init setup_arch(char **cmdline_p)
> > > > {
> > > > +#ifdef CONFIG_OF
> > > > + unflatten_device_tree();
> > > > +#endif
> > > > enable_mmu();
> > >
> > > Was this moved to setup_arch to have it before enable_mmu? I think
> > > that makes sense.
> >
> > early_init_dt_alloc_memory_arch used physical address.
> > It override on sh-specific, can after enable_mmu.
> > But I don't feel an advantage.
>
> I dont think we should be putting sh-specific code in
> early_init_dt_alloc_memory. If calling unflatten_device_tree before
> enable_mmu avoids the need to do that, it seems like the right choice.
> Is this how other archs do it? I think we should try to be as
> consistent as possible with general practice across the kernel.
OK.
It's considered.
> > > > +#ifndef CONFIG_OF
> > > > ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
> > > >
> > > > printk(KERN_NOTICE "Boot params:\n"
> > > > @@ -290,6 +304,7 @@ void __init setup_arch(char **cmdline_p)
> > > >
> > > > if (!MOUNT_ROOT_RDONLY)
> > > > root_mountflags &= ~MS_RDONLY;
> > > > +#endif
> > >
> > > Do these boot params only make sense for non-DT setups?
> > >
> > > > +#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
> > > > /* Save unparsed command line copy for /proc/cmdline */
> > > > memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
> > > > *cmdline_p = command_line;
> > > > +#else
> > > > + *cmdline_p = boot_command_line;
> > > > +#endif
> > >
> > > I think this is wrong -- it causes the builtin command line and
> > > bootloader-provided command line to be ignored on DT kernels. Do you
> > > just want to deprecate builtin and bootloader-provided command lines?
> > > Or is it just a side effect of adding support for chosen/bootarg?
> >
> > Yes. I think zero-page passing only non-DT.
> > DT using chosen/bootargs.
>
> This precludes having the bootloader provide a DTB from ROM, since it
> needs to be able to patch the DTB with user preferences, and also
> requires DTB-patching code to be added to the bootloader. At the very
> least we should retain the ability to have a builtin command line in
> the kernel that's appended to the one from the DTB (and possibly allow
> the order to be changed), but I think we should also allow the
> bootloader to pass in a command line like in the non-DTB setup.
>
> DTB and command line are very different things (hardware description
> vs user preference, and OS-generic vs OS-specific) and the whole
> chosen/bootargs system is something of a hack.
It's better to decide a requirement to a boot loader.
u-boot is passing to bootargs in easy way.
> > > > parse_early_param();
> > > >
> > > > diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
> > > > new file mode 100644
> > > > index 0000000..8c9dcdc
> > > > --- /dev/null
> > > > +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> > > > @@ -0,0 +1,2 @@
> > > > +#define evt2irq(evt) (((evt) >> 5) - 16)
> > > > +#define irq2evt(irq) (((irq) + 16) << 5)
> > >
> > > This seems unrelated to other things in this patch.
> >
> > It using DT define.
>
> Ah, I see, it's used later in the dts itself. But why not just put the
> actual IRQ numbers in the dts directly? The evt numbers seem like an
> implementation detail, whereas device tree bindings should be stable
> and independent of kernel sources.
An IRQ is the virtual value, so it's necessary to convert from EVT.
SH3/4 interrupt controller using EVT.
> If evt numbers are really what makes sense to have in the dts, then
> sh_intc should probably define its irq_domain so that it maps evt
> numbers to irq numbers. But that doesn't seem necessary.
It good way.
>
> Rich
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH RESEND 06/12] clk: sh: SH7750/51 PLL and divider clock driver
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (4 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 05/12] sh: DeviceTree support update Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 20:48 ` Geert Uytterhoeven
2016-05-01 5:08 ` [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver Yoshinori Sato
` (5 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-clk, linux-sh, linux-kernel; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../bindings/clock/renesas,sh-div-clock.txt | 24 ++
.../bindings/clock/renesas,sh7750-div-clock.txt | 27 ++
.../bindings/clock/renesas,sh7750-pll-clock.txt | 26 ++
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 3 +-
drivers/clk/sh/Kconfig | 5 +
drivers/clk/sh/Makefile | 2 +
drivers/clk/sh/clk-sh7750.c | 223 ++++++++++++++
drivers/clk/sh/clk-shdiv.c | 338 +++++++++++++++++++++
9 files changed, 648 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
create mode 100644 drivers/clk/sh/Kconfig
create mode 100644 drivers/clk/sh/Makefile
create mode 100644 drivers/clk/sh/clk-sh7750.c
create mode 100644 drivers/clk/sh/clk-shdiv.c
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
new file mode 100644
index 0000000..399e0da
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
@@ -0,0 +1,24 @@
+* Renesas H8/300 divider clock
+
+Required Properties:
+
+ - compatible: Must be "renesas,h8300-div-clock"
+
+ - clocks: Reference to the parent clocks ("extal1" and "extal2")
+
+ - #clock-cells: Must be 1
+
+ - reg: Base address and length of the divide rate selector
+
+ - renesas,width: bit width of selector
+
+Example
+-------
+
+ cclk: cclk {
+ compatible = "renesas,h8300-div-clock";
+ clocks = <&xclk>;
+ #clock-cells = <0>;
+ reg = <0xfee01b 2>;
+ renesas,width = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
new file mode 100644
index 0000000..8c57ab5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
@@ -0,0 +1,27 @@
+* Renesas SH7750/51 divider clock
+
+Required Properties:
+
+ - compatible: Must be "renesas,sh7750-div-clock"
+
+ - clocks: Reference to the parent clocks (mostly PLL)
+
+ - #clock-cells: Must be 0
+
+ - reg: Base address and length of the divide rate selector
+
+ - renesas,offset: bit offset of selector
+
+ - clock-output-names: The names of the clocks.
+
+Example
+-------
+
+ iclk: iclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <6>;
+ clock-output-names = "ick";
+ };
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
new file mode 100644
index 0000000..06a3d31
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
@@ -0,0 +1,26 @@
+Renesas SH7750/51 PLL clock
+
+This device is Clock multiplyer
+
+Required Properties:
+
+ - compatible: Must be "renesas,sh7750-pll-clock"
+
+ - clocks: Reference to the parent clocks
+
+ - #clock-cells: Must be 0
+
+ - renesas,mult: PLL1 multiply rate
+
+ - reg: Two rate selector (FRQCR / WDT) register address
+
+Example
+-------
+
+ pllclk: pllclk {
+ compatible = "renesas,sh7750-pll-clock";
+ clocks = <&oclk>;
+ #clock-cells = <0>;
+ renesas,mult = <12>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 16f7d33..19b0cd3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -202,6 +202,7 @@ source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/samsung/Kconfig"
+source "drivers/clk/sh/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/ti/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d6..c75d9c8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -83,4 +83,5 @@ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
-obj-$(CONFIG_H8300) += h8300/
+obj-$(CONFIG_H8300) += h8300/
+obj-$(CONFIG_SUPERH) += sh/
diff --git a/drivers/clk/sh/Kconfig b/drivers/clk/sh/Kconfig
new file mode 100644
index 0000000..729850c
--- /dev/null
+++ b/drivers/clk/sh/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_CLK_SH7750
+ bool "Clcok driver for SH7750/SH7751"
+ depends on CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+ CPU_SUBTYPE_SH7750R || \
+ CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
diff --git a/drivers/clk/sh/Makefile b/drivers/clk/sh/Makefile
new file mode 100644
index 0000000..7122c37
--- /dev/null
+++ b/drivers/clk/sh/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_COMMON_CLK_SH7750) += clk-sh7750.o
+obj-$(CONFIG_COMMON_CLK_SH7750) += clk-shdiv.o
diff --git a/drivers/clk/sh/clk-sh7750.c b/drivers/clk/sh/clk-sh7750.c
new file mode 100644
index 0000000..a00c421
--- /dev/null
+++ b/drivers/clk/sh/clk-sh7750.c
@@ -0,0 +1,223 @@
+/*
+ * Renesas SH7750/51 clock driver
+ *
+ * Copyright 2016 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+struct clk *sh_div_clk_register(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock);
+
+static DEFINE_SPINLOCK(clklock);
+
+static struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { .val = 0, .div = 0, },
+};
+
+static struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { .val = 0, .div = 0, },
+};
+
+struct pll_clock {
+ struct clk_hw hw;
+ void __iomem *freqcr;
+ void __iomem *wdt;
+ int mult;
+};
+
+#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct pll_clock *pll_clock = to_pll_clock(hw);
+
+ if ((ioread16(pll_clock->freqcr) >> 9) & 1)
+ return parent_rate * pll_clock->mult;
+ else
+ return parent_rate;
+}
+
+static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct pll_clock *pll_clock = to_pll_clock(hw);
+ int mul;
+
+ mul = rate / *prate;
+ mul = (pll_clock->mult / 2 < mul)?pll_clock->mult:1;
+ return *prate * mul;
+}
+
+static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int mult;
+ unsigned char val;
+ unsigned long flags;
+ struct pll_clock *pll_clock = to_pll_clock(hw);
+
+ mult = rate / parent_rate;
+ if (mult > 1) {
+ /* PLL enable */
+ /* required stable time */
+ spin_lock_irqsave(&clklock, flags);
+ iowrite16(0x5a00, pll_clock->wdt);
+ iowrite16(0xa503, pll_clock->wdt + 2);
+ val = ioread16(pll_clock->freqcr);
+ val |= 0x0200;
+ iowrite16(val, pll_clock->freqcr);
+ spin_unlock_irqrestore(&clklock, flags);
+ } else {
+ /* PLL disable */
+ /* not required stable time */
+ val = ioread16(pll_clock->freqcr);
+ val &= ~0x0200;
+ iowrite16(val, pll_clock->freqcr);
+ }
+ return 0;
+}
+
+static const struct clk_ops pll_ops = {
+ .recalc_rate = pll_recalc_rate,
+ .round_rate = pll_round_rate,
+ .set_rate = pll_set_rate,
+};
+
+static void __init sh7750_pll_clk_setup(struct device_node *node)
+{
+ unsigned int num_parents;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ struct pll_clock *pll_clock;
+ struct clk_init_data init;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: no parent found", clk_name);
+ return;
+ }
+
+ pll_clock = kzalloc(sizeof(struct pll_clock), GFP_KERNEL);
+ if (!pll_clock) {
+ pr_err("%s: failed to alloc memory", clk_name);
+ return;
+ }
+
+ pll_clock->freqcr = of_iomap(node, 0);
+ if (pll_clock->freqcr = NULL) {
+ pr_err("%s: failed to map frequenct control register",
+ clk_name);
+ goto free_clock;
+ }
+
+ pll_clock->wdt = of_iomap(node, 1);
+ if (pll_clock->wdt = NULL) {
+ pr_err("%s: failed to map watchdog register", clk_name);
+ goto unmap_freqcr;
+ }
+
+ of_property_read_u32_index(node, "renesas,mult", 0, &pll_clock->mult);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.name = clk_name;
+ init.ops = &pll_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ pll_clock->hw.init = &init;
+
+ clk = clk_register(NULL, &pll_clock->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register %s pll clock (%ld)\n",
+ __func__, clk_name, PTR_ERR(clk));
+ goto unmap_wdt;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+unmap_wdt:
+ iounmap(pll_clock->wdt);
+unmap_freqcr:
+ iounmap(pll_clock->freqcr);
+free_clock:
+ kfree(pll_clock);
+}
+
+static void __init sh7750_div_clk_setup(struct device_node *node)
+{
+ unsigned int num_parents;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ void __iomem *freqcr = NULL;
+ int i;
+ int num_clks;
+ int offset;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: no parent found", clk_name);
+ return;
+ }
+
+ num_clks = of_property_count_strings(node, "clock-output-names");
+ if (num_clks < 0) {
+ pr_err("%s: failed to count clocks", clk_name);
+ return;
+ }
+
+ freqcr = of_iomap(node, 0);
+ if (freqcr = NULL) {
+ pr_err("%s: failed to map divide register", clk_name);
+ goto error;
+ }
+ of_property_read_u32_index(node, "renesas,offset", 0, &offset);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ for (i = 0; i < num_clks; i++) {
+ of_property_read_string_index(node, "clock-output-names", i,
+ &clk_name);
+ clk = sh_div_clk_register(NULL, clk_name, parent_name,
+ freqcr,
+ offset, 3,
+ (offset = 0)?pdiv_table:div_table,
+ &clklock);
+ if (IS_ERR(clk))
+ pr_err("%s: failed to register %s div clock (%ld)\n",
+ __func__, clk_name, PTR_ERR(clk));
+ else
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ }
+error:
+ if (freqcr)
+ iounmap(freqcr);
+}
+
+CLK_OF_DECLARE(sh7750_div_clk, "renesas,sh7750-div-clock",
+ sh7750_div_clk_setup);
+CLK_OF_DECLARE(sh7750_pll_clk, "renesas,sh7750-pll-clock",
+ sh7750_pll_clk_setup);
diff --git a/drivers/clk/sh/clk-shdiv.c b/drivers/clk/sh/clk-shdiv.c
new file mode 100644
index 0000000..ad244a8
--- /dev/null
+++ b/drivers/clk/sh/clk-shdiv.c
@@ -0,0 +1,338 @@
+/*
+ * SuperH divider clock driver
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+#define div_mask(width) ((1 << (width)) - 1)
+
+static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
+ u8 width)
+{
+ unsigned int maxdiv = 0, mask = div_mask(width);
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div > maxdiv && clkt->val <= mask)
+ maxdiv = clkt->div;
+ return maxdiv;
+}
+
+static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width)
+{
+ if (table)
+ return _get_table_maxdiv(table, width);
+ return div_mask(width) + 1;
+}
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val = val)
+ return clkt->div;
+ return 0;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, u8 width)
+{
+ if (table)
+ return _get_table_div(table, val);
+ return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div = div)
+ return clkt->val;
+ return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+ unsigned int div, u8 width)
+{
+ if (table)
+ return _get_table_val(table, div);
+ return div - 1;
+}
+
+static unsigned long sh_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int div;
+
+ div = _get_div(table, val, divider->width);
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static unsigned long sh_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int val;
+
+ val = __raw_readw(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return sh_divider_recalc_rate(hw, parent_rate, val, divider->table);
+}
+
+static bool _is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div = div)
+ return true;
+ return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div)
+{
+ if (table)
+ return _is_valid_table_div(table, div);
+ return true;
+}
+
+static int _round_up_table(const struct clk_div_table *table, int div)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div = div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round_up(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (table)
+ div = _round_up_table(table, div);
+
+ return div;
+}
+
+static int _div_round(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ return _div_round_up(table, parent_rate, rate);
+}
+
+static bool _is_best_div(unsigned long rate, unsigned long now,
+ unsigned long best)
+{
+ return now <= rate && now > best;
+}
+
+static int _next_div(const struct clk_div_table *table, int div)
+{
+ div++;
+
+ if (table)
+ return _round_up_table(table, div);
+
+ return div;
+}
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ int i, bestdiv = 0;
+ unsigned long parent_rate, best = 0, now, maxdiv;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ maxdiv = _get_maxdiv(table, width);
+
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestdiv = _div_round(table, parent_rate, rate);
+ bestdiv = bestdiv = 0 ? 1 : bestdiv;
+ bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+ return bestdiv;
+ }
+
+ /*
+ * The maximum divider we can use without overflowing
+ * unsigned long in rate * i below
+ */
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (i = _next_div(table, 0); i <= maxdiv;
+ i = _next_div(table, i)) {
+ if (rate * i = parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+ rate * i);
+ now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
+ if (_is_best_div(rate, now, best)) {
+ bestdiv = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestdiv) {
+ bestdiv = _get_maxdiv(table, width);
+ *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
+ }
+
+ return bestdiv;
+}
+
+static long sh_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate, const struct clk_div_table *table,
+ u8 width)
+{
+ int div;
+
+ div = clk_divider_bestdiv(hw, rate, prate, table, width);
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
+static long sh_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+
+ return sh_divider_round_rate(hw, rate, prate, divider->table,
+ divider->width);
+}
+
+static int sh_divider_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ unsigned int div, value;
+
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (!_is_valid_div(table, div))
+ return -EINVAL;
+
+ value = _get_val(table, div, width);
+
+ return min_t(unsigned int, value, div_mask(width));
+}
+
+static int sh_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int value;
+ unsigned long flags = 0;
+ u16 val;
+
+ value = sh_divider_get_val(rate, parent_rate, divider->table,
+ divider->width);
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ val = __raw_readw(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ val |= value << divider->shift;
+ __raw_writew(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static const struct clk_ops sh_clk_divider_ops = {
+ .recalc_rate = sh_clk_divider_recalc_rate,
+ .round_rate = sh_clk_divider_round_rate,
+ .set_rate = sh_clk_divider_set_rate,
+};
+
+static struct clk *_register_divider(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_divider *div;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &sh_clk_divider_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_divider assignments */
+ div->reg = reg;
+ div->shift = shift;
+ div->width = width;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ /* register the clock */
+ clk = clk_register(dev, &div->hw);
+
+ if (IS_ERR(clk))
+ kfree(div);
+
+ return clk;
+}
+
+struct clk *sh_div_clk_register(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ return _register_divider(dev, name, parent_name, reg, shift,
+ width, table, lock);
+}
+EXPORT_SYMBOL_GPL(sh_div_clk_register);
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 06/12] clk: sh: SH7750/51 PLL and divider clock driver
2016-05-01 5:08 ` [PATCH RESEND 06/12] clk: sh: SH7750/51 PLL and divider clock driver Yoshinori Sato
@ 2016-05-01 20:48 ` Geert Uytterhoeven
2016-05-10 8:31 ` Yoshinori Sato
0 siblings, 1 reply; 29+ messages in thread
From: Geert Uytterhoeven @ 2016-05-01 20:48 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-clk, Linux-sh list, linux-kernel@vger.kernel.org
Hi Sato-san,
On Sun, May 1, 2016 at 7:08 AM, Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> .../bindings/clock/renesas,sh-div-clock.txt | 24 ++
> .../bindings/clock/renesas,sh7750-div-clock.txt | 27 ++
> .../bindings/clock/renesas,sh7750-pll-clock.txt | 26 ++
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 3 +-
> drivers/clk/sh/Kconfig | 5 +
> drivers/clk/sh/Makefile | 2 +
> drivers/clk/sh/clk-sh7750.c | 223 ++++++++++++++
> drivers/clk/sh/clk-shdiv.c | 338 +++++++++++++++++++++
> 9 files changed, 648 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
> create mode 100644 drivers/clk/sh/Kconfig
> create mode 100644 drivers/clk/sh/Makefile
> create mode 100644 drivers/clk/sh/clk-sh7750.c
> create mode 100644 drivers/clk/sh/clk-shdiv.c
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
> new file mode 100644
> index 0000000..399e0da
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
> @@ -0,0 +1,24 @@
> +* Renesas H8/300 divider clock
[...]
h8300?
> diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
> new file mode 100644
> index 0000000..8c57ab5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
> @@ -0,0 +1,27 @@
> +* Renesas SH7750/51 divider clock
> +
> +Required Properties:
> +
> + - compatible: Must be "renesas,sh7750-div-clock"
> +
> + - clocks: Reference to the parent clocks (mostly PLL)
> +
> + - #clock-cells: Must be 0
> +
> + - reg: Base address and length of the divide rate selector
> +
> + - renesas,offset: bit offset of selector
> +
> + - clock-output-names: The names of the clocks.
> +
> +Example
> +-------
> +
> + iclk: iclk {
> + compatible = "renesas,sh7750-div-clock";
> + clocks = <&pllclk>;
> + #clock-cells = <0>;
> + reg = <0xffc00000 2>;
> + renesas,offset = <6>;
> + clock-output-names = "ick";
> + };
> diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
> new file mode 100644
> index 0000000..06a3d31
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
> @@ -0,0 +1,26 @@
> +Renesas SH7750/51 PLL clock
> +
> +This device is Clock multiplyer
> +
> +Required Properties:
> +
> + - compatible: Must be "renesas,sh7750-pll-clock"
> +
> + - clocks: Reference to the parent clocks
> +
> + - #clock-cells: Must be 0
> +
> + - renesas,mult: PLL1 multiply rate
> +
> + - reg: Two rate selector (FRQCR / WDT) register address
> +
> +Example
> +-------
> +
> + pllclk: pllclk {
> + compatible = "renesas,sh7750-pll-clock";
> + clocks = <&oclk>;
> + #clock-cells = <0>;
> + renesas,mult = <12>;
> + reg = <0xffc00000 2>, <0xffc00008 4>;
> + };
As the registers of the PLL clock and the various div clocks are the
same, I think it will be simpler to just write a single driver that provides
all clocks, instead of describing all clocks in DT.
Cfr. drivers/clk/renesas/*-cpg-mssr.c vs. drivers/clk/renesas/clk-rcar-gen2.c
+ drivers/clk/renesas/clk-mstp.c + drivers/clk/renesas/clk-div6.c.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 06/12] clk: sh: SH7750/51 PLL and divider clock driver
2016-05-01 20:48 ` Geert Uytterhoeven
@ 2016-05-10 8:31 ` Yoshinori Sato
0 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-10 8:31 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-clk, Linux-sh list, linux-kernel@vger.kernel.org
Sorry too late reply.
On Mon, 02 May 2016 05:48:28 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Sun, May 1, 2016 at 7:08 AM, Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> > .../bindings/clock/renesas,sh-div-clock.txt | 24 ++
> > .../bindings/clock/renesas,sh7750-div-clock.txt | 27 ++
> > .../bindings/clock/renesas,sh7750-pll-clock.txt | 26 ++
> > drivers/clk/Kconfig | 1 +
> > drivers/clk/Makefile | 3 +-
> > drivers/clk/sh/Kconfig | 5 +
> > drivers/clk/sh/Makefile | 2 +
> > drivers/clk/sh/clk-sh7750.c | 223 ++++++++++++++
> > drivers/clk/sh/clk-shdiv.c | 338 +++++++++++++++++++++
> > 9 files changed, 648 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
> > create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
> > create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
> > create mode 100644 drivers/clk/sh/Kconfig
> > create mode 100644 drivers/clk/sh/Makefile
> > create mode 100644 drivers/clk/sh/clk-sh7750.c
> > create mode 100644 drivers/clk/sh/clk-shdiv.c
> >
> > diff --git a/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
> > new file mode 100644
> > index 0000000..399e0da
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,sh-div-clock.txt
> > @@ -0,0 +1,24 @@
> > +* Renesas H8/300 divider clock
>
> [...]
>
> h8300?
Ouch. fixed.
>
> > diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
> > new file mode 100644
> > index 0000000..8c57ab5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-div-clock.txt
> > @@ -0,0 +1,27 @@
> > +* Renesas SH7750/51 divider clock
> > +
> > +Required Properties:
> > +
> > + - compatible: Must be "renesas,sh7750-div-clock"
> > +
> > + - clocks: Reference to the parent clocks (mostly PLL)
> > +
> > + - #clock-cells: Must be 0
> > +
> > + - reg: Base address and length of the divide rate selector
> > +
> > + - renesas,offset: bit offset of selector
> > +
> > + - clock-output-names: The names of the clocks.
> > +
> > +Example
> > +-------
> > +
> > + iclk: iclk {
> > + compatible = "renesas,sh7750-div-clock";
> > + clocks = <&pllclk>;
> > + #clock-cells = <0>;
> > + reg = <0xffc00000 2>;
> > + renesas,offset = <6>;
> > + clock-output-names = "ick";
> > + };
> > diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt b/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
> > new file mode 100644
> > index 0000000..06a3d31
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-pll-clock.txt
> > @@ -0,0 +1,26 @@
> > +Renesas SH7750/51 PLL clock
> > +
> > +This device is Clock multiplyer
> > +
> > +Required Properties:
> > +
> > + - compatible: Must be "renesas,sh7750-pll-clock"
> > +
> > + - clocks: Reference to the parent clocks
> > +
> > + - #clock-cells: Must be 0
> > +
> > + - renesas,mult: PLL1 multiply rate
> > +
> > + - reg: Two rate selector (FRQCR / WDT) register address
> > +
> > +Example
> > +-------
> > +
> > + pllclk: pllclk {
> > + compatible = "renesas,sh7750-pll-clock";
> > + clocks = <&oclk>;
> > + #clock-cells = <0>;
> > + renesas,mult = <12>;
> > + reg = <0xffc00000 2>, <0xffc00008 4>;
> > + };
>
> As the registers of the PLL clock and the various div clocks are the
> same, I think it will be simpler to just write a single driver that provides
> all clocks, instead of describing all clocks in DT.
>
> Cfr. drivers/clk/renesas/*-cpg-mssr.c vs. drivers/clk/renesas/clk-rcar-gen2.c
> + drivers/clk/renesas/clk-mstp.c + drivers/clk/renesas/clk-div6.c.
OK.
This part little complex.
I'll clean up this.
Thanks.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (5 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 06/12] clk: sh: SH7750/51 PLL and divider clock driver Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-02 16:48 ` Bjorn Helgaas
2016-05-02 19:33 ` Bjorn Helgaas
2016-05-01 5:08 ` [PATCH RESEND 08/12] intc: sh: Renesas Super H INTC driver Yoshinori Sato
` (4 subsequent siblings)
11 siblings, 2 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-pci, linux-sh, linux-kernel; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../devicetree/bindings/pci/sh7751-pci.txt | 51 ++++
drivers/pci/host/Kconfig | 7 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-sh7751.c | 321 +++++++++++++++++++++
drivers/pci/host/pci-sh7751.h | 269 +++++++++++++++++
5 files changed, 649 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sh7751-pci.txt
create mode 100644 drivers/pci/host/pci-sh7751.c
create mode 100644 drivers/pci/host/pci-sh7751.h
diff --git a/Documentation/devicetree/bindings/pci/sh7751-pci.txt b/Documentation/devicetree/bindings/pci/sh7751-pci.txt
new file mode 100644
index 0000000..45b5152
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sh7751-pci.txt
@@ -0,0 +1,51 @@
+* Renesas SH7751 PCI host interfaces
+
+Required properties:
+ - compatible: "renesas,sh7751-pci" is required.
+ And board specific compatible if fixup required.
+
+ - reg: base address and length of the pcie controller registers.
+ - #address-cells: set to <2>
+ - #size-cells: set to <1>
+ - bus-range: PCI bus numbers covered
+ - device_type: set to "pci"
+ - ranges: ranges for the PCI memory and I/O regions.
+ - interrupt-map-mask and interrupt-map: standard PCI properties
+ to define the mapping of the PCIe interface to interrupt
+ numbers.
+
+Example:
+ pci: pci-controller@fe200000 {
+ compatible = "renesas,sh7751-pci", "iodata,landisk";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x02000000 0x00000000 0xfd000000 0xfd000000 0x00000000 0x01000000>,
+ <0x01000000 0x00000000 0xfe240000 0x00000000 0x00000000 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x1800 0 7>;
+ interrupt-map = <0x0000 0 1 &cpldintc evt2irq(0x2a0) 0
+ 0x0000 0 2 &cpldintc evt2irq(0x2c0) 0
+ 0x0000 0 3 &cpldintc evt2irq(0x2e0) 0
+ 0x0000 0 4 &cpldintc evt2irq(0x300) 0
+
+ 0x0800 0 1 &cpldintc evt2irq(0x2c0) 0
+ 0x0800 0 2 &cpldintc evt2irq(0x2e0) 0
+ 0x0800 0 3 &cpldintc evt2irq(0x300) 0
+ 0x0800 0 4 &cpldintc evt2irq(0x2a0) 0
+
+ 0x1000 0 1 &cpldintc evt2irq(0x2e0) 0
+ 0x1000 0 2 &cpldintc evt2irq(0x300) 0
+ 0x1000 0 3 &cpldintc evt2irq(0x2a0) 0
+ 0x1000 0 4 &cpldintc evt2irq(0x2c0) 0
+
+ 0x1800 0 1 &cpldintc evt2irq(0x300) 0
+ 0x1800 0 2 &cpldintc evt2irq(0x2a0) 0
+ 0x1800 0 3 &cpldintc evt2irq(0x2c0) 0
+ 0x1800 0 4 &cpldintc evt2irq(0x2e0) 0>;
+ };
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 7a0780d..a8596db 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -231,4 +231,11 @@ config PCI_HOST_THUNDER_ECAM
help
Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
+config PCI_SH7751
+ bool "Renesas SH7751 On-Chip PCI controller"
+ depends on OF && SUPERH
+ select PCI_HOST_COMMON
+ help
+ Say Y here if you want PCI support on SH7751.
+
endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index d85b5fa..91268cb 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
+obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o
diff --git a/drivers/pci/host/pci-sh7751.c b/drivers/pci/host/pci-sh7751.c
new file mode 100644
index 0000000..fd6548b
--- /dev/null
+++ b/drivers/pci/host/pci-sh7751.c
@@ -0,0 +1,321 @@
+/*
+ * SH7751 PCI driver
+ * Copyright (C) 2016 Yoshinori Sato
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include "pci-host-common.h"
+#include "pci-sh7751.h"
+
+#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
+#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
+
+unsigned long PCIBIOS_MIN_IO;
+unsigned long PCIBIOS_MIN_MEM;
+DEFINE_RAW_SPINLOCK(pci_config_lock);
+
+/*
+ * PCIC fixups
+ */
+
+static __initconst const struct fixups {
+ char *compatible;
+ void (*fixup)(void __iomem *, void __iomem *);
+} fixup_list[] = {
+};
+
+static __init void pcic_fixups(struct device_node *np,
+ void __iomem *pcic, void __iomem *bcr)
+{
+ int i;
+ const struct fixups *f = fixup_list;
+
+ for (i = 0; i < ARRAY_SIZE(fixup_list); i++) {
+ if (of_device_is_compatible(np, f->compatible)) {
+ f->fixup(pcic, bcr);
+ break;
+ }
+ }
+}
+
+/*
+ * Direct access to PCI hardware...
+ */
+#define CONFIG_CMD(bus, devfn, where) \
+ (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
+
+/*
+ * Functions for accessing PCI configuration space with type 1 accesses
+ */
+static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct gen_pci *pci = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)pci->cfg.res.start;
+ unsigned long flags;
+ u32 data;
+
+ /*
+ * PCIPDR may only be accessed as 32 bit words,
+ * so we must do byte alignment by hand
+ */
+ raw_spin_lock_irqsave(&pci_config_lock, flags);
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ data = pcic_readl(SH4_PCIPDR);
+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+
+ switch (size) {
+ case 1:
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ *val = (data >> ((where & 2) << 3)) & 0xffff;
+ break;
+ case 4:
+ *val = data;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * Since SH4 only does 32bit access we'll have to do a read,
+ * mask,write operation.
+ * We'll allow an odd byte offset, though it should be illegal.
+ */
+static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct gen_pci *pci = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)pci->cfg.res.start;
+ unsigned long flags;
+ int shift;
+ u32 data;
+
+ raw_spin_lock_irqsave(&pci_config_lock, flags);
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ data = pcic_readl(SH4_PCIPDR);
+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+
+ switch (size) {
+ case 1:
+ shift = (where & 3) << 3;
+ data &= ~(0xff << shift);
+ data |= ((val & 0xff) << shift);
+ break;
+ case 2:
+ shift = (where & 2) << 3;
+ data &= ~(0xffff << shift);
+ data |= ((val & 0xffff) << shift);
+ break;
+ case 4:
+ data = val;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+
+ pcic_writel(data, SH4_PCIPDR);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct gen_pci_cfg_bus_ops pci_sh7751_ops = {
+ .ops = {
+ .read = sh4_pci_read,
+ .write = sh4_pci_write,
+ },
+};
+
+/*
+ * Called after each bus is probed, but before its children
+ * are examined.
+ */
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+}
+
+/*
+ * We need to avoid collisions with `mirrored' VGA ports
+ * and other strange ISA hardware, so we always want the
+ * addresses to be allocated in the 0x000-0x0ff region
+ * modulo 0x400.
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+ resource_size_t size, resource_size_t align)
+{
+ resource_size_t start = res->start;
+
+ return start;
+}
+
+int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+ enum pci_mmap_state mmap_state, int write_combine)
+{
+ /*
+ * I/O space can be accessed via normal processor loads and stores on
+ * this platform but for now we elect not to do this and portable
+ * drivers should not do this anyway.
+ */
+ if (mmap_state = pci_mmap_io)
+ return -EINVAL;
+
+ /*
+ * Ignore write-combine; for now only return uncached mappings.
+ */
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+ vma->vm_end - vma->vm_start,
+ vma->vm_page_prot);
+}
+
+static const struct of_device_id sh7751_pci_of_match[] = {
+ { .compatible = "renesas,sh7751-pci", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sh7751_pci_of_match);
+
+static int __init area_sdram_check(void __iomem *pci_reg_base,
+ void __iomem *bcr,
+ unsigned int area)
+{
+ unsigned long word;
+
+ word = __raw_readl(bcr + SH7751_BCR1);
+ /* check BCR for SDRAM in area */
+ if (((word >> area) & 1) = 0) {
+ printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, SH4_PCIBCR1);
+
+ word = __raw_readw(bcr + SH7751_BCR2);
+ /* check BCR2 for 32bit SDRAM interface*/
+ if (((word >> (area << 1)) & 0x3) != 0x3) {
+ printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, SH4_PCIBCR2);
+
+ return 1;
+}
+
+static __init int sh7751_pci_probe(struct platform_device *pdev)
+{
+ struct resource *res, *wres;
+ u32 id;
+ u32 reg, word;
+ void __iomem *pci_reg_base;
+ void __iomem *bcr;
+ struct gen_pci *pci;
+
+ pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pci_reg_base = (void __iomem *)res->start;
+ if (IS_ERR(pci_reg_base))
+ return PTR_ERR(pci_reg_base);
+
+ wres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (IS_ERR(wres))
+ return PTR_ERR(wres);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ bcr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pci_reg_base))
+ return PTR_ERR(bcr);
+
+ /* check for SH7751/SH7751R hardware */
+ id = pcic_readl(SH7751_PCICONF0);
+ if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
+ id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
+ pr_warn("PCI: This is not an SH7751(R)\n");
+ return -ENODEV;
+ }
+ dev_info(&pdev->dev, "PCI core found at %p\n",
+ pci_reg_base);
+
+ /* Set the BCR's to enable PCI access */
+ reg = __raw_readl(bcr);
+ reg |= 0x80000;
+ __raw_writel(reg, bcr);
+
+ /* Turn the clocks back on (not done in reset)*/
+ pcic_writel(0, SH4_PCICLKR);
+ /* Clear Powerdown IRQ's (not done in reset) */
+ word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
+ pcic_writel(word, SH4_PCIPINT);
+
+ /* set the command/status bits to:
+ * Wait Cycle Control + Parity Enable + Bus Master +
+ * Mem space enable
+ */
+ word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
+ SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
+ pcic_writel(word, SH7751_PCICONF1);
+
+ /* define this host as the host bridge */
+ word = PCI_BASE_CLASS_BRIDGE << 24;
+ pcic_writel(word, SH7751_PCICONF2);
+
+ /* Set IO and Mem windows to local address
+ * Make PCI and local address the same for easy 1 to 1 mapping
+ */
+ word = wres->end - wres->start - 1;
+ pcic_writel(word, SH4_PCILSR0);
+ /* Set the values on window 0 PCI config registers */
+ word = P2SEGADDR(wres->start);
+ pcic_writel(word, SH4_PCILAR0);
+ pcic_writel(word, SH7751_PCICONF5);
+
+ /* check BCR for SDRAM in specified area */
+ area_sdram_check(pci_reg_base, bcr, (wres->start >> 27) & 0x07);
+
+ /* configure the wait control registers */
+ word = __raw_readl(bcr + SH7751_WCR1);
+ pcic_writel(word, SH4_PCIWCR1);
+ word = __raw_readl(bcr + SH7751_WCR2);
+ pcic_writel(word, SH4_PCIWCR2);
+ word = __raw_readl(bcr + SH7751_WCR3);
+ pcic_writel(word, SH4_PCIWCR3);
+ word = __raw_readl(bcr + SH7751_MCR);
+ pcic_writel(word, SH4_PCIMCR);
+
+ pcic_fixups(pdev->dev.of_node, pci_reg_base, bcr);
+
+ /* SH7751 init done, set central function init complete */
+ /* use round robin mode to stop a device starving/overruning */
+ word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
+ pcic_writel(word, SH4_PCICR);
+
+ pci->cfg.ops = &pci_sh7751_ops;
+ return pci_host_common_probe(pdev, pci);
+}
+
+static __refdata struct platform_driver sh7751_pci_driver = {
+ .driver = {
+ .name = "sh7751-pci",
+ .of_match_table = sh7751_pci_of_match,
+ },
+ .probe = sh7751_pci_probe,
+};
+module_platform_driver(sh7751_pci_driver);
+
+MODULE_DESCRIPTION("SH7751 PCI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pci-sh7751.h b/drivers/pci/host/pci-sh7751.h
new file mode 100644
index 0000000..4f8230e
--- /dev/null
+++ b/drivers/pci/host/pci-sh7751.h
@@ -0,0 +1,269 @@
+/*
+ * Low-Level PCI Support for SH7751 targets
+ *
+ * Dustin McIntire (dustin@sensoria.com) (c) 2001
+ * Paul Mundt (lethal@linux-sh.org) (c) 2003
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License. See linux/COPYING for more information.
+ *
+ */
+
+#ifndef _PCI_SH7751_H_
+#define _PCI_SH7751_H_
+
+#define SH4_PCICR 0x100 /* PCI Control Register */
+ #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
+ #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
+ #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */
+ #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */
+ #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
+ #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
+ #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */
+ #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */
+ #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */
+ #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
+ #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
+#define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
+#define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
+#define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
+#define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
+#define SH4_PCIINT 0x114 /* PCI Interrupt Register */
+ #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */
+ #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */
+ #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */
+ #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
+ #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */
+ #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */
+ #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
+ #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */
+ #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
+ #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
+ #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
+ #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
+#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
+ #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
+ #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
+ #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
+ #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
+ #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
+ #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
+ #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
+ #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
+ #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
+ #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
+ #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
+#define SH4_PCIALR 0x11C /* Error Address Register */
+#define SH4_PCICLR 0x120 /* Error Command/Data */
+ #define SH4_PCICLR_MPIO 0x80000000
+ #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
+ #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
+ #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
+ #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
+ #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
+ #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
+#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
+ #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
+ #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
+ #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
+ #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
+ #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
+ #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
+ #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
+#define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
+#define SH4_PCIBMLR 0x138 /* Error Bus Master Register */
+ #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
+ #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
+ #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
+ #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
+ #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
+#define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
+ #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
+#define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
+#define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */
+#define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
+#define SH4_PCIDCR0 0x18C /* DMA0 Control Register */
+ #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
+ #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
+ #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
+ #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
+ #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */
+ #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
+ #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
+ #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
+ #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
+ #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */
+#define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
+#define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */
+#define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
+#define SH4_PCIDCR1 0x19C /* DMA1 Control Register */
+#define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
+#define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */
+#define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
+#define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
+#define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
+#define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */
+#define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
+#define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
+#define SH4_PCIPAR 0x1C0 /* PIO Address Register */
+ #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
+ #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
+ #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
+ #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */
+#define SH4_PCIMBR 0x1C4 /* Memory Base Address */
+ #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
+ #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
+#define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
+ #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
+ #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
+#define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
+ #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
+ #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
+#define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
+#define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */
+ #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
+ #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
+/* For definitions of BCR, MCR see ... */
+#define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
+ #define SH4_PCIMBR0 SH4_PCIBCR1
+#define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
+ #define SH4_PCIMBMR0 SH4_PCIBCR2
+#define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */
+#define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */
+#define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */
+ #define SH4_PCIMBR2 SH4_PCIWCR3
+#define SH4_PCIMCR 0x1F4 /* Memory Control Register */
+#define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
+#define SH4_PCIPCTR 0x200 /* Port Control Register */
+ #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
+ #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
+ #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
+ #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
+ #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
+ #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
+ #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
+ #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
+ #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
+#define SH4_PCIPDTR 0x204 /* Port Data Register */
+ #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
+ #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
+ #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
+ #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
+ #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
+ #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
+#define SH4_PCIPDR 0x220 /* Port IO Data Register */
+
+/* Platform Specific Values */
+#define SH7751_VENDOR_ID 0x1054
+#define SH7751_DEVICE_ID 0x3505
+#define SH7751R_DEVICE_ID 0x350e
+
+/* SH7751 Specific Values */
+#define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
+#define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
+#define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
+#define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
+#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
+
+#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
+
+#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
+ #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
+ #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */
+#define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
+ #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */
+ #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */
+ #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */
+ #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */
+ #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */
+ #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */
+ #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */
+ #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */
+ #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */
+ #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */
+ #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */
+ #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */
+ #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */
+ #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */
+ #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */
+ #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */
+ #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
+ #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */
+ #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */
+ #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
+ #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */
+#define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
+ #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
+ #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
+ #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
+ #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
+#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
+ #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
+ #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
+ #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
+ #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */
+ #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */
+ #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */
+ #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */
+#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
+ #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
+ #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
+ #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
+ #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
+/* PCICONF7 - PCICONF10 are undefined */
+#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
+ #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
+ #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */
+/* PCICONF12 is undefined */
+#define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
+ #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */
+/* PCICONF14 is undefined */
+#define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
+ #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */
+#define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
+ #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */
+ #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */
+ #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */
+ #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */
+ #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */
+ #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */
+ #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */
+ #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */
+#define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
+ #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */
+ #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */
+ #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */
+ #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */
+ #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */
+ #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */
+/* SH7751 Internal PCI Registers */
+
+/* Memory Control Registers */
+#define SH7751_BCR1 0x0000 /* Memory BCR1 Register */
+#define SH7751_BCR2 0x0004 /* Memory BCR2 Register */
+#define SH7751_BCR3 0x0050 /* Memory BCR3 Register */
+#define SH7751_WCR1 0x0008 /* Wait Control 1 Register */
+#define SH7751_WCR2 0x000C /* Wait Control 2 Register */
+#define SH7751_WCR3 0x0010 /* Wait Control 3 Register */
+#define SH7751_MCR 0x0014 /* Memory Control Register */
+
+/* General Memory Config Addresses */
+#define SH7751_CS0_BASE_ADDR 0x0
+#define SH7751_MEM_REGION_SIZE 0x04000000
+#define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+
+#endif /* _PCI_SH7751_H_ */
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver
2016-05-01 5:08 ` [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver Yoshinori Sato
@ 2016-05-02 16:48 ` Bjorn Helgaas
2016-05-02 19:33 ` Bjorn Helgaas
1 sibling, 0 replies; 29+ messages in thread
From: Bjorn Helgaas @ 2016-05-02 16:48 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-pci, linux-sh, linux-kernel
On Sun, May 01, 2016 at 02:08:31PM +0900, Yoshinori Sato wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> .../devicetree/bindings/pci/sh7751-pci.txt | 51 ++++
> drivers/pci/host/Kconfig | 7 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pci-sh7751.c | 321 +++++++++++++++++++++
> drivers/pci/host/pci-sh7751.h | 269 +++++++++++++++++
> 5 files changed, 649 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/sh7751-pci.txt
> create mode 100644 drivers/pci/host/pci-sh7751.c
> create mode 100644 drivers/pci/host/pci-sh7751.h
>
> diff --git a/Documentation/devicetree/bindings/pci/sh7751-pci.txt b/Documentation/devicetree/bindings/pci/sh7751-pci.txt
> new file mode 100644
> index 0000000..45b5152
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/sh7751-pci.txt
> @@ -0,0 +1,51 @@
> +* Renesas SH7751 PCI host interfaces
> +
> +Required properties:
> + - compatible: "renesas,sh7751-pci" is required.
> + And board specific compatible if fixup required.
> +
> + - reg: base address and length of the pcie controller registers.
s/pcie/PCIe/
> + - #address-cells: set to <2>
> + - #size-cells: set to <1>
> + - bus-range: PCI bus numbers covered
> + - device_type: set to "pci"
> + - ranges: ranges for the PCI memory and I/O regions.
> + - interrupt-map-mask and interrupt-map: standard PCI properties
> + to define the mapping of the PCIe interface to interrupt
Whitespace error (space before tab).
> + numbers.
> +
> +Example:
> + pci: pci-controller@fe200000 {
> + compatible = "renesas,sh7751-pci", "iodata,landisk";
> + device_type = "pci";
> + bus-range = <0 0>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0x02000000 0x00000000 0xfd000000 0xfd000000 0x00000000 0x01000000>,
> + <0x01000000 0x00000000 0xfe240000 0x00000000 0x00000000 0x00040000>;
> + reg = <0xfe200000 0x0400>,
> + <0x0c000000 0x04000000>,
> + <0xff800000 0x0030>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0x1800 0 7>;
> + interrupt-map = <0x0000 0 1 &cpldintc evt2irq(0x2a0) 0
> + 0x0000 0 2 &cpldintc evt2irq(0x2c0) 0
> + 0x0000 0 3 &cpldintc evt2irq(0x2e0) 0
> + 0x0000 0 4 &cpldintc evt2irq(0x300) 0
> +
> + 0x0800 0 1 &cpldintc evt2irq(0x2c0) 0
> + 0x0800 0 2 &cpldintc evt2irq(0x2e0) 0
> + 0x0800 0 3 &cpldintc evt2irq(0x300) 0
> + 0x0800 0 4 &cpldintc evt2irq(0x2a0) 0
> +
> + 0x1000 0 1 &cpldintc evt2irq(0x2e0) 0
> + 0x1000 0 2 &cpldintc evt2irq(0x300) 0
> + 0x1000 0 3 &cpldintc evt2irq(0x2a0) 0
> + 0x1000 0 4 &cpldintc evt2irq(0x2c0) 0
> +
> + 0x1800 0 1 &cpldintc evt2irq(0x300) 0
> + 0x1800 0 2 &cpldintc evt2irq(0x2a0) 0
> + 0x1800 0 3 &cpldintc evt2irq(0x2c0) 0
> + 0x1800 0 4 &cpldintc evt2irq(0x2e0) 0>;
> + };
> +};
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 7a0780d..a8596db 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -231,4 +231,11 @@ config PCI_HOST_THUNDER_ECAM
> help
> Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
>
> +config PCI_SH7751
> + bool "Renesas SH7751 On-Chip PCI controller"
> + depends on OF && SUPERH
> + select PCI_HOST_COMMON
> + help
> + Say Y here if you want PCI support on SH7751.
> +
> endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index d85b5fa..91268cb 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
> obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
> +obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o
> diff --git a/drivers/pci/host/pci-sh7751.c b/drivers/pci/host/pci-sh7751.c
> new file mode 100644
> index 0000000..fd6548b
> --- /dev/null
> +++ b/drivers/pci/host/pci-sh7751.c
> @@ -0,0 +1,321 @@
> +/*
> + * SH7751 PCI driver
> + * Copyright (C) 2016 Yoshinori Sato
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include "pci-host-common.h"
> +#include "pci-sh7751.h"
> +
> +#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
> +#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
> +
> +unsigned long PCIBIOS_MIN_IO;
> +unsigned long PCIBIOS_MIN_MEM;
> +DEFINE_RAW_SPINLOCK(pci_config_lock);
I think this (pci_config_lock) can be static.
> +/*
> + * PCIC fixups
> + */
> +
> +static __initconst const struct fixups {
> + char *compatible;
> + void (*fixup)(void __iomem *, void __iomem *);
> +} fixup_list[] = {
> +};
> +
> +static __init void pcic_fixups(struct device_node *np,
> + void __iomem *pcic, void __iomem *bcr)
> +{
> + int i;
> + const struct fixups *f = fixup_list;
> +
> + for (i = 0; i < ARRAY_SIZE(fixup_list); i++) {
> + if (of_device_is_compatible(np, f->compatible)) {
> + f->fixup(pcic, bcr);
> + break;
> + }
> + }
> +}
This fixup feature looks unused (fixup_list[] is empty). Please
remove it unless it's needed.
> +
> +/*
> + * Direct access to PCI hardware...
> + */
> +#define CONFIG_CMD(bus, devfn, where) \
> + (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
> +
> +/*
> + * Functions for accessing PCI configuration space with type 1 accesses
> + */
> +static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 *val)
> +{
> + struct gen_pci *pci = bus->sysdata;
> + void __iomem *pci_reg_base = (void __iomem *)pci->cfg.res.start;
pci->cfg.res is a struct resource, which contains CPU physical
addresses. You would need to ioremap() those addresses before
accessing them.
> + unsigned long flags;
> + u32 data;
> +
> + /*
> + * PCIPDR may only be accessed as 32 bit words,
> + * so we must do byte alignment by hand
> + */
> + raw_spin_lock_irqsave(&pci_config_lock, flags);
> + pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
> + data = pcic_readl(SH4_PCIPDR);
> + raw_spin_unlock_irqrestore(&pci_config_lock, flags);
> +
> + switch (size) {
> + case 1:
> + *val = (data >> ((where & 3) << 3)) & 0xff;
> + break;
> + case 2:
> + *val = (data >> ((where & 2) << 3)) & 0xffff;
> + break;
> + case 4:
> + *val = data;
> + break;
> + default:
> + return PCIBIOS_FUNC_NOT_SUPPORTED;
> + }
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +/*
> + * Since SH4 only does 32bit access we'll have to do a read,
> + * mask,write operation.
> + * We'll allow an odd byte offset, though it should be illegal.
PCI config space allows byte accesses at any alignment. Your hardware
is not fully PCI-compliant if it can only do 32-bit accesses. The
read/mask/write scheme works most of the time, but it will sometimes
corrupt RW1C bits in nearby registers.
> + */
> +static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 val)
> +{
> + struct gen_pci *pci = bus->sysdata;
> + void __iomem *pci_reg_base = (void __iomem *)pci->cfg.res.start;
> + unsigned long flags;
> + int shift;
> + u32 data;
> +
> + raw_spin_lock_irqsave(&pci_config_lock, flags);
> + pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
> + data = pcic_readl(SH4_PCIPDR);
> + raw_spin_unlock_irqrestore(&pci_config_lock, flags);
> +
> + switch (size) {
> + case 1:
> + shift = (where & 3) << 3;
> + data &= ~(0xff << shift);
> + data |= ((val & 0xff) << shift);
> + break;
> + case 2:
> + shift = (where & 2) << 3;
> + data &= ~(0xffff << shift);
> + data |= ((val & 0xffff) << shift);
> + break;
> + case 4:
> + data = val;
> + break;
> + default:
> + return PCIBIOS_FUNC_NOT_SUPPORTED;
> + }
> +
> + pcic_writel(data, SH4_PCIPDR);
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static struct gen_pci_cfg_bus_ops pci_sh7751_ops = {
> + .ops = {
> + .read = sh4_pci_read,
> + .write = sh4_pci_write,
> + },
> +};
> +
> +/*
> + * Called after each bus is probed, but before its children
> + * are examined.
Extra spaces at the beginnings of these lines.
> + */
> +void pcibios_fixup_bus(struct pci_bus *bus)
> +{
> +}
> +
> +/*
> + * We need to avoid collisions with `mirrored' VGA ports
> + * and other strange ISA hardware, so we always want the
> + * addresses to be allocated in the 0x000-0x0ff region
> + * modulo 0x400.
> + */
> +resource_size_t pcibios_align_resource(void *data, const struct resource *res,
> + resource_size_t size, resource_size_t align)
> +{
> + resource_size_t start = res->start;
> +
> + return start;
> +}
> +
> +int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
> + enum pci_mmap_state mmap_state, int write_combine)
> +{
> + /*
> + * I/O space can be accessed via normal processor loads and stores on
> + * this platform but for now we elect not to do this and portable
> + * drivers should not do this anyway.
> + */
> + if (mmap_state = pci_mmap_io)
> + return -EINVAL;
> +
> + /*
> + * Ignore write-combine; for now only return uncached mappings.
> + */
> + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
> +
> + return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
> + vma->vm_end - vma->vm_start,
> + vma->vm_page_prot);
> +}
> +
> +static const struct of_device_id sh7751_pci_of_match[] = {
> + { .compatible = "renesas,sh7751-pci", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, sh7751_pci_of_match);
> +
> +static int __init area_sdram_check(void __iomem *pci_reg_base,
> + void __iomem *bcr,
> + unsigned int area)
Nobody checks the return value, so this could be void. "check" in the
name doesn't really tell us what it does. In fact, it looks like it
programs something.
> +{
> + unsigned long word;
> +
> + word = __raw_readl(bcr + SH7751_BCR1);
> + /* check BCR for SDRAM in area */
> + if (((word >> area) & 1) = 0) {
> + printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
> + area, word);
> + return 0;
> + }
> + pcic_writel(word, SH4_PCIBCR1);
> +
> + word = __raw_readw(bcr + SH7751_BCR2);
> + /* check BCR2 for 32bit SDRAM interface*/
> + if (((word >> (area << 1)) & 0x3) != 0x3) {
> + printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
> + area, word);
> + return 0;
> + }
> + pcic_writel(word, SH4_PCIBCR2);
> +
> + return 1;
> +}
> +
> +static __init int sh7751_pci_probe(struct platform_device *pdev)
> +{
> + struct resource *res, *wres;
> + u32 id;
> + u32 reg, word;
> + void __iomem *pci_reg_base;
> + void __iomem *bcr;
> + struct gen_pci *pci;
> +
> + pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + pci_reg_base = (void __iomem *)res->start;
res->start is a CPU physical address. You need to ioremap() it if you
want a virtual address.
> + if (IS_ERR(pci_reg_base))
platform_get_resource() returns a valid struct resource * or NULL for
error. This should check "!res" for error. Same below for "wres".
> + return PTR_ERR(pci_reg_base);
> +
> + wres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + if (IS_ERR(wres))
> + return PTR_ERR(wres);
Shouldn't we be requesting these two regions (0 and 1)? Even if you
don't need to ioremap them, if the device consumes those two regions
of address space, they should be in iomem_resource so they appear in
/proc/iomem and so we don't allocate that space to anything else.
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> + bcr = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(pci_reg_base))
This looks like a typo for "bcr"? (s/pci_reg_base/bcr/ ?)
> + return PTR_ERR(bcr);
> +
> + /* check for SH7751/SH7751R hardware */
> + id = pcic_readl(SH7751_PCICONF0);
> + if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
> + id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
> + pr_warn("PCI: This is not an SH7751(R)\n");
> + return -ENODEV;
> + }
> + dev_info(&pdev->dev, "PCI core found at %p\n",
> + pci_reg_base);
Save the struct resource pointer and use %pR instead of %p.
Please add a printk like:
dev_warn(&pdev->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n")
> + /* Set the BCR's to enable PCI access */
s/BCR's/BCRs/ (apostrophe is for possessives or omitted letters, not
making things plural)
> + reg = __raw_readl(bcr);
> + reg |= 0x80000;
> + __raw_writel(reg, bcr);
> +
> + /* Turn the clocks back on (not done in reset)*/
> + pcic_writel(0, SH4_PCICLKR);
> + /* Clear Powerdown IRQ's (not done in reset) */
s/IRQ's/IRQs/
> + word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
> + pcic_writel(word, SH4_PCIPINT);
> +
> + /* set the command/status bits to:
> + * Wait Cycle Control + Parity Enable + Bus Master +
> + * Mem space enable
> + */
> + word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
> + SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
> + pcic_writel(word, SH7751_PCICONF1);
> +
> + /* define this host as the host bridge */
> + word = PCI_BASE_CLASS_BRIDGE << 24;
> + pcic_writel(word, SH7751_PCICONF2);
> +
> + /* Set IO and Mem windows to local address
> + * Make PCI and local address the same for easy 1 to 1 mapping
> + */
> + word = wres->end - wres->start - 1;
> + pcic_writel(word, SH4_PCILSR0);
> + /* Set the values on window 0 PCI config registers */
> + word = P2SEGADDR(wres->start);
> + pcic_writel(word, SH4_PCILAR0);
> + pcic_writel(word, SH7751_PCICONF5);
> +
> + /* check BCR for SDRAM in specified area */
> + area_sdram_check(pci_reg_base, bcr, (wres->start >> 27) & 0x07);
> +
> + /* configure the wait control registers */
> + word = __raw_readl(bcr + SH7751_WCR1);
> + pcic_writel(word, SH4_PCIWCR1);
> + word = __raw_readl(bcr + SH7751_WCR2);
> + pcic_writel(word, SH4_PCIWCR2);
> + word = __raw_readl(bcr + SH7751_WCR3);
> + pcic_writel(word, SH4_PCIWCR3);
> + word = __raw_readl(bcr + SH7751_MCR);
> + pcic_writel(word, SH4_PCIMCR);
> +
> + pcic_fixups(pdev->dev.of_node, pci_reg_base, bcr);
> +
> + /* SH7751 init done, set central function init complete */
> + /* use round robin mode to stop a device starving/overruning */
Please use normal block comment style here and elsewhere, e.g.,
/*
* text...
* more text...
*/
> + word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
> + pcic_writel(word, SH4_PCICR);
> +
> + pci->cfg.ops = &pci_sh7751_ops;
> + return pci_host_common_probe(pdev, pci);
> +}
> +
> +static __refdata struct platform_driver sh7751_pci_driver = {
> + .driver = {
> + .name = "sh7751-pci",
> + .of_match_table = sh7751_pci_of_match,
> + },
> + .probe = sh7751_pci_probe,
> +};
> +module_platform_driver(sh7751_pci_driver);
> +
> +MODULE_DESCRIPTION("SH7751 PCI driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/pci/host/pci-sh7751.h b/drivers/pci/host/pci-sh7751.h
> new file mode 100644
> index 0000000..4f8230e
> --- /dev/null
> +++ b/drivers/pci/host/pci-sh7751.h
> @@ -0,0 +1,269 @@
> +/*
> + * Low-Level PCI Support for SH7751 targets
> + *
> + * Dustin McIntire (dustin@sensoria.com) (c) 2001
> + * Paul Mundt (lethal@linux-sh.org) (c) 2003
> + *
> + * May be copied or modified under the terms of the GNU General Public
> + * License. See linux/COPYING for more information.
> + *
> + */
Since these definitions are only used in pci-sh7751.c, please move
them there so there's only one source file instead of two.
Many of the bitfield definitions are unused; you can also remove them.
> +#ifndef _PCI_SH7751_H_
> +#define _PCI_SH7751_H_
> +
> +#define SH4_PCICR 0x100 /* PCI Control Register */
> + #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
> + #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
> + #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */
> + #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */
> + #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
> + #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
> + #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */
> + #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */
> + #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */
> + #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
> + #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
> +#define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
> +#define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
> +#define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
> +#define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
> +#define SH4_PCIINT 0x114 /* PCI Interrupt Register */
> + #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */
> + #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */
> + #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */
> + #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
> + #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */
> + #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */
> + #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
> + #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */
> + #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
> + #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
> + #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
> + #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
> +#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
> + #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
> + #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
> + #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
> + #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
> + #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
> + #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
> + #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
> + #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
> + #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
> + #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
> + #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
> +#define SH4_PCIALR 0x11C /* Error Address Register */
> +#define SH4_PCICLR 0x120 /* Error Command/Data */
> + #define SH4_PCICLR_MPIO 0x80000000
> + #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
> + #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
> + #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
> + #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
> + #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
> + #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
> +#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
> + #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
> + #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
> + #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
> + #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
> + #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
> + #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
> + #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
> +#define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
> +#define SH4_PCIBMLR 0x138 /* Error Bus Master Register */
> + #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
> + #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
> + #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
> + #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
> + #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
> +#define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
> + #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
> +#define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
> +#define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */
> +#define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
> +#define SH4_PCIDCR0 0x18C /* DMA0 Control Register */
> + #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
> + #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
> + #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
> + #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
> + #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */
> + #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
> + #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
> + #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
> + #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
> + #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */
> +#define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
> +#define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */
> +#define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
> +#define SH4_PCIDCR1 0x19C /* DMA1 Control Register */
> +#define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
> +#define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */
> +#define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
> +#define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
> +#define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
> +#define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */
> +#define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
> +#define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
> +#define SH4_PCIPAR 0x1C0 /* PIO Address Register */
> + #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
> + #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
> + #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
> + #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */
> +#define SH4_PCIMBR 0x1C4 /* Memory Base Address */
> + #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
> + #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
> +#define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
> + #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
> + #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
> +#define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
> + #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
> + #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
> +#define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
> +#define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */
> + #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
> + #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
> +/* For definitions of BCR, MCR see ... */
> +#define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
> + #define SH4_PCIMBR0 SH4_PCIBCR1
> +#define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
> + #define SH4_PCIMBMR0 SH4_PCIBCR2
> +#define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */
> +#define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */
> +#define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */
> + #define SH4_PCIMBR2 SH4_PCIWCR3
> +#define SH4_PCIMCR 0x1F4 /* Memory Control Register */
> +#define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
> +#define SH4_PCIPCTR 0x200 /* Port Control Register */
> + #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
> + #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
> + #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
> + #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
> + #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
> + #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
> + #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
> + #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
> + #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
> +#define SH4_PCIPDTR 0x204 /* Port Data Register */
> + #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
> + #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
> + #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
> + #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
> + #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
> + #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
> +#define SH4_PCIPDR 0x220 /* Port IO Data Register */
> +
> +/* Platform Specific Values */
> +#define SH7751_VENDOR_ID 0x1054
> +#define SH7751_DEVICE_ID 0x3505
> +#define SH7751R_DEVICE_ID 0x350e
> +
> +/* SH7751 Specific Values */
> +#define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
> +#define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
> +#define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
> +#define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
> +#define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
> +#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
> +
> +#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
> +
> +#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
> + #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
> + #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */
> +#define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
> + #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */
> + #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */
> + #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */
> + #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */
> + #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */
> + #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */
> + #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */
> + #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */
> + #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */
> + #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */
> + #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */
> + #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */
> + #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */
> + #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */
> + #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */
> + #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */
> + #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
> + #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */
> + #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */
> + #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
> + #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */
> +#define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
> + #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
> + #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
> + #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
> + #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
> +#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
> + #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
> + #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
> + #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
> + #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */
> + #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */
> + #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */
> + #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */
> +#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
> + #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
> + #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */
> +#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
> + #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
> + #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
> + #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
> + #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
> +#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
> + #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
> + #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
> + #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
> + #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
> +/* PCICONF7 - PCICONF10 are undefined */
> +#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
> + #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
> + #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */
> +/* PCICONF12 is undefined */
> +#define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
> + #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */
> +/* PCICONF14 is undefined */
> +#define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
> + #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */
> +#define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
> + #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */
> + #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */
> + #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */
> + #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */
> + #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */
> + #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */
> + #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */
> + #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */
> +#define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
> + #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */
> + #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */
> + #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */
> + #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */
> + #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */
> + #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */
> +/* SH7751 Internal PCI Registers */
> +
> +/* Memory Control Registers */
> +#define SH7751_BCR1 0x0000 /* Memory BCR1 Register */
> +#define SH7751_BCR2 0x0004 /* Memory BCR2 Register */
> +#define SH7751_BCR3 0x0050 /* Memory BCR3 Register */
> +#define SH7751_WCR1 0x0008 /* Wait Control 1 Register */
> +#define SH7751_WCR2 0x000C /* Wait Control 2 Register */
> +#define SH7751_WCR3 0x0010 /* Wait Control 3 Register */
> +#define SH7751_MCR 0x0014 /* Memory Control Register */
> +
> +/* General Memory Config Addresses */
> +#define SH7751_CS0_BASE_ADDR 0x0
> +#define SH7751_MEM_REGION_SIZE 0x04000000
> +#define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
> +#define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
> +#define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
> +#define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
> +#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
> +#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
> +
> +#endif /* _PCI_SH7751_H_ */
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver
2016-05-01 5:08 ` [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver Yoshinori Sato
2016-05-02 16:48 ` Bjorn Helgaas
@ 2016-05-02 19:33 ` Bjorn Helgaas
1 sibling, 0 replies; 29+ messages in thread
From: Bjorn Helgaas @ 2016-05-02 19:33 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-pci, linux-sh, linux-kernel
On Sun, May 01, 2016 at 02:08:31PM +0900, Yoshinori Sato wrote:
> +static __init int sh7751_pci_probe(struct platform_device *pdev)
> +{
> ...
> + pci->cfg.ops = &pci_sh7751_ops;
> + return pci_host_common_probe(pdev, pci);
> +}
> +
> +static __refdata struct platform_driver sh7751_pci_driver = {
> + .driver = {
> + .name = "sh7751-pci",
> + .of_match_table = sh7751_pci_of_match,
> + },
> + .probe = sh7751_pci_probe,
> +};
> +module_platform_driver(sh7751_pci_driver);
I *think* that if you use builtin_platform_driver_probe() or
module_platform_driver_probe() here, you can get rid of the __refdata
on sh7751_pci_driver while keeping sh7751_pci_probe() as __init.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH RESEND 08/12] intc: sh: Renesas Super H INTC driver
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (6 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 07/12] pci: sh: SH7751 PCI host bridge driver Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 09/12] sh: Add I/O DATA HDL-U support drivers Yoshinori Sato
` (3 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
SuperH IPR based driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../interrupt-controller/renesas,sh7751-intc.txt | 25 ++++
drivers/irqchip/Kconfig | 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-shipr.c | 138 +++++++++++++++++++++
4 files changed, 169 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.txt
create mode 100644 drivers/irqchip/irq-renesas-shipr.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.txt
new file mode 100644
index 0000000..6d9bf6c
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.txt
@@ -0,0 +1,25 @@
+DT bindings for the SH7751 interrupt controller
+
+Required properties:
+
+ - compatible: has to be "renesas,sh7751-intc".
+
+ - reg: Base address and length of interrupt controller register
+ and extend register.
+
+ - interrupt-controller: Identifies the node as an interrupt controller.
+
+ - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined
+ in interrupts.txt in this directory.
+
+Example
+-------
+
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ };
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3e12479..273f19d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -244,3 +244,8 @@ config IRQ_MXS
config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
+
+config RENESAS_SH_INTC
+ def_bool y if SH_DEVICE_TREE
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b03cfcb..3f9fc5c 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
+obj-$(CONFIG_RENESAS_SH_INTC) += irq-renesas-shipr.o irq-io-landisk.o
diff --git a/drivers/irqchip/irq-renesas-shipr.c b/drivers/irqchip/irq-renesas-shipr.c
new file mode 100644
index 0000000..67cce6a
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-shipr.c
@@ -0,0 +1,138 @@
+/*
+ * SH IPR-INTC interrupt contoller driver
+ *
+ * Copyright 2016 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of.h>
+#include <asm/io.h>
+
+static struct sh7751_intc_regs {
+ void *icr;
+ void *ipr;
+ void *intpri00;
+ void *intreq00;
+ void *intmsk00;
+ void *intmskclr00;
+} sh7751_regs;
+
+static const unsigned int ipr_table[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0 - 7 */
+ 0x41, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, /* 8 - 15 */
+ 0x03, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x11, /* 16 - 23 */
+ 0x11, 0x11, 0x11, 0x13, 0x12, 0x12, 0xff, 0xff, /* 24 - 31 */
+ 0x30, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x21, /* 32 - 39 */
+ 0x21, 0x21, 0x21, 0x21, 0x32, 0x32, 0x32, 0x32, /* 40 - 47 */
+ 0xff, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, /* 48 - 55 */
+ 0xff, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, /* 56 - 63 */
+};
+
+static const unsigned int pri_table[] = {
+ 0, 4, 4, 4, 4, 4, 4, 4,
+ 8, 32, 32, 32, 12, 32, 32, 32,
+};
+
+static void sh_disable_irq(struct irq_data *data)
+{
+ int pos;
+ unsigned int addr;
+ unsigned long pri;
+ int irq = data->irq;
+ struct sh7751_intc_regs *reg = data->chip_data;
+
+ if (irq < 64) {
+ if (ipr_table[irq] != 0xff) {
+ addr = (ipr_table[irq] & 0xf0) >> 2;
+ pos = (ipr_table[irq] & 0x0f) << 4;
+ pri = ~(0x000f << pos);
+ pri &= __raw_readw(reg->ipr + addr);
+ __raw_writew(pri, reg->ipr + addr);
+ }
+ } else {
+ if (pri_table[irq - 64] < 32) {
+ pos = pri_table[irq - 64];
+ pri = ~(0x000f << pos);
+ pri &= __raw_readw(reg->intpri00);
+ __raw_writew(pri, reg->intpri00);
+ }
+ }
+}
+
+static void sh_enable_irq(struct irq_data *data)
+{
+ int pos;
+ unsigned int addr;
+ unsigned long pri;
+ int irq = data->irq;
+ struct sh7751_intc_regs *reg = data->chip_data;
+
+ if (irq < 64) {
+ if (ipr_table[irq] != 0xff) {
+ addr = (ipr_table[irq] & 0xf0) >> 2;
+ pos = (ipr_table[irq] & 0x0f) * 4;
+ pri = ~(0x000f << pos);
+ pri &= __raw_readw(reg->ipr + addr);
+ pri |= 1 << pos;
+ __raw_writew(pri, reg->ipr + addr);
+ }
+ } else {
+ if (pri_table[irq - 64] < 32) {
+ pos = pri_table[irq - 64];
+ pri = ~(0x000f << pos);
+ pri &= __raw_readw(reg->intpri00);
+ pri |= 1 << pos;
+ __raw_writew(pri, reg->intpri00);
+ }
+ }
+}
+
+struct irq_chip sh_irq_chip = {
+ .name = "SH-IPR",
+ .irq_unmask = sh_enable_irq,
+ .irq_mask = sh_disable_irq,
+};
+
+static __init int irq_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh_irq_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+
+ return 0;
+}
+
+static struct irq_domain_ops irq_ops = {
+ .map = irq_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sh_intc_of_init(struct device_node *intc,
+ struct device_node *parent)
+{
+ struct irq_domain *domain;
+ void *intc_baseaddr;
+ void *intc_baseaddr2;
+
+ intc_baseaddr = of_iomap(intc, 0);
+ intc_baseaddr2 = of_iomap(intc, 1);
+ BUG_ON(!intc_baseaddr);
+
+ sh7751_regs.icr = intc_baseaddr;
+ sh7751_regs.ipr = intc_baseaddr + 4;
+ sh7751_regs.intpri00 = intc_baseaddr2;
+ sh7751_regs.intreq00 = intc_baseaddr2 + 0x20;
+ sh7751_regs.intmsk00 = intc_baseaddr2 + 0x40;
+ sh7751_regs.intmskclr00 = intc_baseaddr2 + 0x60;
+
+ domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, &sh7751_regs);
+ BUG_ON(!domain);
+ irq_set_default_host(domain);
+ return 0;
+}
+
+IRQCHIP_DECLARE(sh_7751_intc, "renesas,sh7751-intc", sh_intc_of_init);
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 09/12] sh: Add I/O DATA HDL-U support drivers.
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (7 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 08/12] intc: sh: Renesas Super H INTC driver Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 10/12] sh: I/O DATA HDL-U (aka landisk) support dts Yoshinori Sato
` (2 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
PCI host fixup and external interrupt controller.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../interrupt-controller/iodata-landisk.txt | 28 +++++++++
drivers/irqchip/irq-io-landisk.c | 71 ++++++++++++++++++++++
drivers/pci/host/pci-sh7751.c | 25 ++++++++
3 files changed, 124 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt
create mode 100644 drivers/irqchip/irq-io-landisk.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt b/Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt
new file mode 100644
index 0000000..09c2841
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/iodata-landisk.txt
@@ -0,0 +1,28 @@
+DT bindings for the I/O DATA HDL-U interrupt controler
+
+Required properties:
+
+ - compatible: has to be "iodata,landisk-intc".
+
+ - reg: Base address and length of interrupt controller register.
+
+ - interrupt-controller: Identifies the node as an interrupt controller.
+
+ - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined
+ in interrupts.txt in this directory.
+
+ - interrupt-map: Interrupt mapping on parent controler.
+
+Example
+-------
+
+ cpldintc: cpld@b0000000 {
+ compatible = "iodata,landisk-intc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xb0000000 8>;
+ interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>,
+ <2 &shintc 2 0>, <3 &shintc 3 0>,
+ <4 &shintc 4 0>, <5 &shintc 5 0>,
+ <6 &shintc 6 0>, <7 &shintc 7 0>;
+ };
diff --git a/drivers/irqchip/irq-io-landisk.c b/drivers/irqchip/irq-io-landisk.c
new file mode 100644
index 0000000..c351925
--- /dev/null
+++ b/drivers/irqchip/irq-io-landisk.c
@@ -0,0 +1,71 @@
+/*
+ * IO-DATA LANDISK CPLD IRQ driver
+ *
+ * Copyright 2016 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+
+static void landisk_mask_irq(struct irq_data *data)
+{
+ u8 mask = __raw_readb(data->chip_data + 5);
+
+ mask &= !(1 << (data->irq - 5));
+ __raw_writeb(mask, data->chip_data + 5);
+}
+
+static void landisk_unmask_irq(struct irq_data *data)
+{
+ u8 mask = __raw_readb(data->chip_data + 5);
+
+ mask |= (1 << (data->irq - 5));
+ __raw_writeb(mask, data->chip_data + 5);
+}
+
+static struct irq_chip cpld_irq_chip = {
+ .name = "LANDISK-CPLD",
+ .irq_unmask = landisk_unmask_irq,
+ .irq_mask = landisk_mask_irq,
+};
+
+static int cpld_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &cpld_irq_chip,
+ handle_simple_irq);
+ irq_set_chip_data(virq, d->host_data);
+
+ return 0;
+}
+
+static struct irq_domain_ops irq_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .map = cpld_map,
+};
+
+static int __init landisk_intc_of_init(struct device_node *intc,
+ struct device_node *parent)
+{
+ struct irq_domain *domain, *pdomain;
+ int num_irqpin;
+ void *baseaddr;
+
+ baseaddr = of_iomap(intc, 0);
+ pdomain = irq_find_host(parent);
+ of_get_property(intc, "interrupt-map", &num_irqpin);
+ num_irqpin /= sizeof(u32) * 3;
+ domain = irq_domain_create_hierarchy(pdomain, 0, num_irqpin,
+ of_node_to_fwnode(intc),
+ &irq_ops, baseaddr);
+ BUG_ON(!domain);
+ irq_domain_associate_many(domain, 0, 0, 8);
+ return 0;
+}
+
+IRQCHIP_DECLARE(cpld_intc, "iodata,landisk-intc", landisk_intc_of_init);
diff --git a/drivers/pci/host/pci-sh7751.c b/drivers/pci/host/pci-sh7751.c
index fd6548b..3fa0da5 100644
--- a/drivers/pci/host/pci-sh7751.c
+++ b/drivers/pci/host/pci-sh7751.c
@@ -26,10 +26,35 @@ DEFINE_RAW_SPINLOCK(pci_config_lock);
* PCIC fixups
*/
+#define PCIMCR_MRSET 0x40000000
+#define PCIMCR_RFSH 0x00000004
+
+static void __init landisk_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
+{
+ unsigned long bcr1, mcr;
+
+ bcr1 = __raw_readl(bcr + SH7751_BCR1);
+ bcr1 |= 0x00080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
+ pcic_writel(bcr1, SH4_PCIBCR1);
+
+ mcr = __raw_readl(bcr + SH7751_MCR);
+ mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
+ pcic_writel(mcr, SH4_PCIMCR);
+
+ pcic_writel(0x0c000000, SH7751_PCICONF5);
+ pcic_writel(0xd0000000, SH7751_PCICONF6);
+ pcic_writel(0x0c000000, SH4_PCILAR0);
+ pcic_writel(0x00000000, SH4_PCILAR1);
+}
+
static __initconst const struct fixups {
char *compatible;
void (*fixup)(void __iomem *, void __iomem *);
} fixup_list[] = {
+ {
+ .compatible = "iodata,landisk",
+ .fixup = landisk_fixup,
+ },
};
static __init void pcic_fixups(struct device_node *np,
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 10/12] sh: I/O DATA HDL-U (aka landisk) support dts
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (8 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 09/12] sh: Add I/O DATA HDL-U support drivers Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
[not found] ` <1462079316-27771-11-git-send-email-ysato-Rn4VEauK+AKRv+LV9MX5uooqe+aC9MnS@public.gmane.org>
2016-05-01 5:08 ` [PATCH RESEND 11/12] sh: I/O DATA HDL-U defconfig (DT mode) Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 12/12] of: Add sh support Yoshinori Sato
11 siblings, 1 reply; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: devicetree, linux-sh, linux-kernel; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/landisk.dts | 150 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
create mode 100644 arch/sh/boot/dts/landisk.dts
diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index 0000000..a994d19
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,150 @@
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+
+/dts-v1/;
+/ {
+ model = "I/O DATA HDL-U";
+ compatible = "iodata,hdl-u";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+ chosen {
+ stdout-path = &sci1;
+ bootargs = "console=ttySC1,115200";
+ };
+ aliases {
+ serial0 = &sci0;
+ serial1 = &sci1;
+ };
+
+ oclk: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+ pllclk: pllclk {
+ compatible = "renesas,sh7750-pll-clock";
+ clocks = <&oclk>;
+ #clock-cells = <0>;
+ renesas,mult = <12>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
+ iclk: iclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <6>;
+ clock-output-names = "ick";
+ };
+ bclk: bclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <3>;
+ clock-output-names = "bck";
+ };
+ fclk: fclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <0>;
+ clock-output-names = "fck";
+ };
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ clock-frequency = <266666666>;
+ };
+ };
+ memory@0c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+
+ };
+ cpldintc: cpld@b0000000 {
+ compatible = "iodata,landisk-intc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xb0000000 8>;
+ interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>,
+ <2 &shintc 2 0>, <3 &shintc 3 0>,
+ <4 &shintc 4 0>, <5 &shintc 5 0>,
+ <6 &shintc 6 0>, <7 &shintc 7 0>;
+ };
+ sci0: serial@ffe00000 {
+ compatible = "renesas,scif";
+ reg = <0xffe00000 0x20>;
+ interrupts = <evt2irq(0x4e0) 0
+ evt2irq(0x500) 0
+ evt2irq(0x520) 0
+ evt2irq(0x540) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
+ sci1: serial@ffe80000 {
+ compatible = "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0
+ evt2irq(0x720) 0
+ evt2irq(0x760) 0
+ evt2irq(0x740) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
+ tmu: timer@ffd80008 {
+ compatible = "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0
+ evt2irq(0x420) 0
+ evt2irq(0x440) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ renesas,channels-mask = <0x03>;
+ };
+
+ pci: pci-controller@fe200000 {
+ compatible = "renesas,sh7751-pci", "iodata,landisk";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x02000000 0x00000000 0xfd000000 0xfd000000 0x00000000 0x01000000>,
+ <0x01000000 0x00000000 0xfe240000 0x00000000 0x00000000 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x1800 0 7>;
+ interrupt-map = <0x0000 0 1 &cpldintc evt2irq(0x2a0) 0
+ 0x0000 0 2 &cpldintc evt2irq(0x2c0) 0
+ 0x0000 0 3 &cpldintc evt2irq(0x2e0) 0
+ 0x0000 0 4 &cpldintc evt2irq(0x300) 0
+
+ 0x0800 0 1 &cpldintc evt2irq(0x2c0) 0
+ 0x0800 0 2 &cpldintc evt2irq(0x2e0) 0
+ 0x0800 0 3 &cpldintc evt2irq(0x300) 0
+ 0x0800 0 4 &cpldintc evt2irq(0x2a0) 0
+
+ 0x1000 0 1 &cpldintc evt2irq(0x2e0) 0
+ 0x1000 0 2 &cpldintc evt2irq(0x300) 0
+ 0x1000 0 3 &cpldintc evt2irq(0x2a0) 0
+ 0x1000 0 4 &cpldintc evt2irq(0x2c0) 0
+
+ 0x1800 0 1 &cpldintc evt2irq(0x300) 0
+ 0x1800 0 2 &cpldintc evt2irq(0x2a0) 0
+ 0x1800 0 3 &cpldintc evt2irq(0x2c0) 0
+ 0x1800 0 4 &cpldintc evt2irq(0x2e0) 0>;
+ };
+};
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 11/12] sh: I/O DATA HDL-U defconfig (DT mode)
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (9 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 10/12] sh: I/O DATA HDL-U (aka landisk) support dts Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-01 5:08 ` [PATCH RESEND 12/12] of: Add sh support Yoshinori Sato
11 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: linux-sh, linux-kernel; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/configs/landisk-dt_defconfig | 100 +++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 arch/sh/configs/landisk-dt_defconfig
diff --git a/arch/sh/configs/landisk-dt_defconfig b/arch/sh/configs/landisk-dt_defconfig
new file mode 100644
index 0000000..aa52fdb
--- /dev/null
+++ b/arch/sh/configs/landisk-dt_defconfig
@@ -0,0 +1,100 @@
+CONFIG_SYSVIPC=y
+# CONFIG_FHANDLE is not set
+CONFIG_LOG_BUF_SHIFT\x14
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_SH_DEVICE_TREE=y
+CONFIG_SH_PCLK_FREQ3333333
+CONFIG_HEARTBEAT=y
+CONFIG_KEXEC=y
+CONFIG_PCI=y
+CONFIG_PCI_SH7751=y
+CONFIG_PCCARD=y
+CONFIG_YENTA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_PATA_ARTOP=y
+CONFIG_NETDEVICES=y
+CONFIG_8139CP=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_USB_SUPPORT is not set
+CONFIG_COMMON_CLK_SH7750=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_UFS_FS=m
+CONFIG_NFS_FS=y
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=1
+CONFIG_LOCK_STAT=y
+# CONFIG_FTRACE is not set
+CONFIG_CRC_T10DIF=y
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH RESEND 12/12] of: Add sh support
2016-05-01 5:08 [PATCH RESEND 00/12] SH: landisk convert to devicetree Yoshinori Sato
` (10 preceding siblings ...)
2016-05-01 5:08 ` [PATCH RESEND 11/12] sh: I/O DATA HDL-U defconfig (DT mode) Yoshinori Sato
@ 2016-05-01 5:08 ` Yoshinori Sato
2016-05-02 12:35 ` Rob Herring
11 siblings, 1 reply; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-01 5:08 UTC (permalink / raw)
To: devicetree, linux-sh, linux-kernel; +Cc: Yoshinori Sato
sh fdt access in VA. But memory reservation use PA.
So sh need convert to PA.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/of/fdt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index 3349d2a..fb357be 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -593,6 +593,9 @@ void __init early_init_fdt_scan_reserved_mem(void)
fdt_get_mem_rsv(initial_boot_params, n, &base, &size);
if (!size)
break;
+#ifdef CONFIG_SUPERH
+ base = virt_to_phys(base);
+#endif
early_init_dt_reserve_memory_arch(base, size, 0);
}
--
2.7.0
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH RESEND 12/12] of: Add sh support
2016-05-01 5:08 ` [PATCH RESEND 12/12] of: Add sh support Yoshinori Sato
@ 2016-05-02 12:35 ` Rob Herring
2016-05-10 7:46 ` Yoshinori Sato
0 siblings, 1 reply; 29+ messages in thread
From: Rob Herring @ 2016-05-02 12:35 UTC (permalink / raw)
To: Yoshinori Sato
Cc: devicetree@vger.kernel.org, SH-Linux,
linux-kernel@vger.kernel.org
On Sun, May 1, 2016 at 12:08 AM, Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> sh fdt access in VA. But memory reservation use PA.
> So sh need convert to PA.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> drivers/of/fdt.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 3349d2a..fb357be 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -593,6 +593,9 @@ void __init early_init_fdt_scan_reserved_mem(void)
> fdt_get_mem_rsv(initial_boot_params, n, &base, &size);
> if (!size)
> break;
> +#ifdef CONFIG_SUPERH
> + base = virt_to_phys(base);
> +#endif
> early_init_dt_reserve_memory_arch(base, size, 0);
This is not right. base is already a physical address and
early_init_dt_reserve_memory_arch takes a physical address. The
default implementation using memblock also works on physical
addresses. It is a weak function so you can override it if you need to
do something special. But it seems something else is wrong here if you
need this.
Rob
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH RESEND 12/12] of: Add sh support
2016-05-02 12:35 ` Rob Herring
@ 2016-05-10 7:46 ` Yoshinori Sato
0 siblings, 0 replies; 29+ messages in thread
From: Yoshinori Sato @ 2016-05-10 7:46 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, SH-Linux,
linux-kernel@vger.kernel.org
On Mon, 02 May 2016 21:35:28 +0900,
Rob Herring wrote:
>
> On Sun, May 1, 2016 at 12:08 AM, Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > sh fdt access in VA. But memory reservation use PA.
> > So sh need convert to PA.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> > drivers/of/fdt.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > index 3349d2a..fb357be 100644
> > --- a/drivers/of/fdt.c
> > +++ b/drivers/of/fdt.c
> > @@ -593,6 +593,9 @@ void __init early_init_fdt_scan_reserved_mem(void)
> > fdt_get_mem_rsv(initial_boot_params, n, &base, &size);
> > if (!size)
> > break;
> > +#ifdef CONFIG_SUPERH
> > + base = virt_to_phys(base);
> > +#endif
> > early_init_dt_reserve_memory_arch(base, size, 0);
>
> This is not right. base is already a physical address and
> early_init_dt_reserve_memory_arch takes a physical address. The
> default implementation using memblock also works on physical
> addresses. It is a weak function so you can override it if you need to
> do something special. But it seems something else is wrong here if you
> need this.
Thank you very much for your advice.
The function of the sh specific is defined.
> Rob
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply [flat|nested] 29+ messages in thread