[PATCH 0/8] SH7786 PCIe support fixes

[PATCH 0/8] SH7786 PCIe support fixes

[Thomas Petazzoni]

Hello,

The following patches fix a number of issues I encountered while
making PCIe work on a SH7786 platform (both a SH7786 SH4-AP board
running little-endian with a basic E1000E NIC on PCIe, and a custom
SH7786 board running big-endian with a custom IP in an FPGA accessed
over PCIe).

A quick summary of the issues:

 - Some PCI MEM resources were used even if they conflict with RAM

 - The addresses of the PCI MEM and IO regions did not match the
   SH7786 datasheet (the first MEM region and the IO region were
   inverted), causing the device MEM BARs to be unusable.

 - The PCI -> SuperHyway mapping was not correct in some memory
   configurations:

   - With 64 MB or 128 MB and the RAM starting at 0x0800_0000, there
     is an offset of 0x0800_0000 between PCI and memory addresses that
     the DMA mapping API should observe.

   - With 256 MB of RAM starting at 0x0800_0000, we have a region that
     is not aligned on its size, to its must be expanded to 512 MB
     with a base address of 0.

The commit logs have much more details about the fixes.

Best regards,

Thomas Petazzoni

Thomas Petazzoni (8):
  arch/sh: add sh7786_mm_sel() function
  arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset
  arch/sh: pci: don't use disabled resources
  arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
  arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
  arch/sh: pcie-sh7786: adjust PCI MEM and IO regions
  arch/sh: pcie-sh7786: adjust the memory mapping
  arch/sh: pcie-sh7786: handle non-zero DMA offset

 arch/sh/drivers/pci/pci.c            |  5 +++
 arch/sh/drivers/pci/pcie-sh7786.c    | 78 +++++++++++++++++++++++++-----------
 arch/sh/include/cpu-sh4/cpu/sh7786.h |  7 ++++
 arch/sh/kernel/dma-nommu.c           |  7 +++-
 arch/sh/mm/consistent.c              |  4 +-
 5 files changed, 74 insertions(+), 27 deletions(-)

-- 
2.13.6

[PATCH 1/8] arch/sh: add sh7786_mm_sel() function

[Thomas Petazzoni]

The SH7786 has different physical memory layout configurations,
configurable through the MMSELR register. The configuration is
typically defined by the bootloader, so Linux generally doesn't care.

Except that depending on the configuration, some PCI MEM areas may or
may not be available. This commit adds a helper function that allows
to retrieve the current physical memory layout configuration. It will
be used in a following patch to exclude unusable PCI MEM areas during
the PCI initialization.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/include/cpu-sh4/cpu/sh7786.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/sh/include/cpu-sh4/cpu/sh7786.h b/arch/sh/include/cpu-sh4/cpu/sh7786.h
index 0df09e638f09..96b8cb1f754a 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7786.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7786.h
@@ -14,6 +14,8 @@
 #ifndef __CPU_SH7786_H__
 #define __CPU_SH7786_H__
 
+#include <linux/io.h>
+
 enum {
 	/* PA */
 	GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
@@ -131,4 +133,9 @@ enum {
 	GPIO_FN_IRL7, GPIO_FN_IRL6, GPIO_FN_IRL5, GPIO_FN_IRL4,
 };
 
+static inline u32 sh7786_mm_sel(void)
+{
+	return __raw_readl(0xFC400020) & 0x7;
+}
+
 #endif /* __CPU_SH7786_H__ */
-- 
2.13.6

[PATCH 2/8] arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset

[Thomas Petazzoni]

Some devices may have a non-zero DMA offset, i.e an offset between the
DMA address and the physical address. Such an offset can be encoded
into the dma_pfn_offset field of "struct device", but the SuperH
implementation of the DMA mapping API does not observe this
information.

This commit fixes that by ensuring the DMA address is properly
calculated depending on this DMA offset.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/kernel/dma-nommu.c | 7 +++++--
 arch/sh/mm/consistent.c    | 4 ++--
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/sh/kernel/dma-nommu.c b/arch/sh/kernel/dma-nommu.c
index 62b485107eae..178457d7620c 100644
--- a/arch/sh/kernel/dma-nommu.c
+++ b/arch/sh/kernel/dma-nommu.c
@@ -16,7 +16,8 @@ static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
 				 enum dma_data_direction dir,
 				 unsigned long attrs)
 {
-	dma_addr_t addr = page_to_phys(page) + offset;
+	dma_addr_t addr = page_to_phys(page) + offset
+		- PFN_PHYS(dev->dma_pfn_offset);
 
 	WARN_ON(size = 0);
 
@@ -36,12 +37,14 @@ static int nommu_map_sg(struct device *dev, struct scatterlist *sg,
 	WARN_ON(nents = 0 || sg[0].length = 0);
 
 	for_each_sg(sg, s, nents, i) {
+		dma_addr_t offset = PFN_PHYS(dev->dma_pfn_offset);
+
 		BUG_ON(!sg_page(s));
 
 		if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
 			sh_sync_dma_for_device(sg_virt(s), s->length, dir);
 
-		s->dma_address = sg_phys(s);
+		s->dma_address = sg_phys(s) - offset;
 		s->dma_length = s->length;
 	}
 
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index 6ea3aab508f2..8ce98691d822 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -59,7 +59,7 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
 
 	split_page(pfn_to_page(virt_to_phys(ret) >> PAGE_SHIFT), order);
 
-	*dma_handle = virt_to_phys(ret);
+	*dma_handle = virt_to_phys(ret) - PFN_PHYS(dev->dma_pfn_offset);
 
 	return ret_nocache;
 }
@@ -69,7 +69,7 @@ void dma_generic_free_coherent(struct device *dev, size_t size,
 			       unsigned long attrs)
 {
 	int order = get_order(size);
-	unsigned long pfn = dma_handle >> PAGE_SHIFT;
+	unsigned long pfn = (dma_handle >> PAGE_SHIFT) + dev->dma_pfn_offset;
 	int k;
 
 	for (k = 0; k < (1 << order); k++)
-- 
2.13.6

[PATCH 3/8] arch/sh: pci: don't use disabled resources

[Thomas Petazzoni]

In pcibios_scanbus(), we provide to the PCI core the usable MEM and IO
regions using pci_add_resource_offset(). We travel through all
resources available in the "struct pci_channel".

Also, in register_pci_controller(), we travel through all resources to
request them, making sure they don't conflict with already requested
resources.

However, some resources may be disabled, in which case they should not
be requested nor provided to the PCI core.

In the current situation, none of the resources are disabled. However,
follow-up patches in this series will make some resources disabled,
making this preliminary change necessary.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/drivers/pci/pci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 5976a2c8a3e3..e5b7437ab4af 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -49,6 +49,8 @@ static void pcibios_scanbus(struct pci_channel *hose)
 	for (i = 0; i < hose->nr_resources; i++) {
 		res = hose->resources + i;
 		offset = 0;
+		if (res->flags & IORESOURCE_DISABLED)
+			continue;
 		if (res->flags & IORESOURCE_IO)
 			offset = hose->io_offset;
 		else if (res->flags & IORESOURCE_MEM)
@@ -102,6 +104,9 @@ int register_pci_controller(struct pci_channel *hose)
 	for (i = 0; i < hose->nr_resources; i++) {
 		struct resource *res = hose->resources + i;
 
+		if (res->flags & IORESOURCE_DISABLED)
+			continue;
+
 		if (res->flags & IORESOURCE_IO) {
 			if (request_resource(&ioport_resource, res) < 0)
 				goto out;
-- 
2.13.6

[PATCH 4/8] arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled

[Thomas Petazzoni]

Some PCI MEM resources are marked as IORESOURCE_MEM_32BIT, which means
they are only usable when the SH core runs in 32-bit mode. In 29-bit
mode, such memory regions are not usable.

The existing code for SH7786 properly skips such regions when
configuring the PCIe controller registers. However, because such
regions are still described in the resource array, the
pcibios_scanbus() function in the SuperH pci.c will register them to
the PCI core. Due to this, the PCI core will allocate MEM areas from
this resource, and assign BARs pointing to this area, even though it's
unusable.

In order to prevent this from happening, we mark such regions as
IORESOURCE_DISABLED, which tells the SuperH pci.c pcibios_scanbus()
function to skip them.

Note that we separate marking the region as disabled from skipping it,
because other regions will be marked as disabled in follow-up patches.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/drivers/pci/pcie-sh7786.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 45bbe6927251..c2f877b4ef7e 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -419,6 +419,9 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
 		 * mode, so just skip them entirely.
 		 */
 		if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
+			res->flags |= IORESOURCE_DISABLED;
+
+		if (res->flags & IORESOURCE_DISABLED)
 			continue;
 
 		pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
-- 
2.13.6

[PATCH 5/8] arch/sh: pcie-sh7786: exclude unusable PCI MEM areas

[Thomas Petazzoni]

Depending on the physical memory layout, some PCI MEM areas are not
usable. According to the SH7786 datasheet, the PCI MEM area from
1000_0000 to 13FF_FFFF is only usable if the physical memory layout
(in MMSELR) is 1, 2, 5 or 6. In all other configurations, this PCI MEM
area is not usable (because it overlaps with DRAM).

Therefore, this commit adjusts the PCI SH7786 initialization to mark
the relevant PCI resource as IORESOURCE_DISABLED if we can't use it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/drivers/pci/pcie-sh7786.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index c2f877b4ef7e..8d7c328b1899 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -19,6 +19,7 @@
 #include <linux/clk.h>
 #include <linux/sh_clk.h>
 #include <linux/sh_intc.h>
+#include <cpu/sh7786.h>
 #include "pcie-sh7786.h"
 #include <asm/sizes.h>
 
@@ -511,6 +512,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
 static int __init sh7786_pcie_init(void)
 {
 	struct clk *platclk;
+	u32 mm_sel;
 	int i;
 
 	printk(KERN_NOTICE "PCI: Starting initialization.\n");
@@ -544,6 +546,16 @@ static int __init sh7786_pcie_init(void)
 
 	clk_enable(platclk);
 
+	mm_sel = sh7786_mm_sel();
+
+	/*
+	 * Depending on the MMSELR register value, the PCIe0 MEM 1
+	 * area may not be available. See Table 13.11 of the SH7786
+	 * datasheet.
+	 */
+	if (mm_sel != 1 && mm_sel != 2 && mm_sel != 5 && mm_sel != 6)
+		sh7786_pci0_resources[2].flags |= IORESOURCE_DISABLED;
+
 	printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
 
 	for (i = 0; i < nr_ports; i++) {
-- 
2.13.6

[PATCH 6/8] arch/sh: pcie-sh7786: adjust PCI MEM and IO regions

[Thomas Petazzoni]

The current definition of the PCIe IO and MEM resources for SH7786
doesn't match what the datasheet says. For example, for PCIe0
0xfe100000 is advertised by the datasheet as a PCI IO region, while
0xfd000000 is advertised as a PCI MEM region. The code currently
inverts the two.

The SH4A_PCIEPARL and SH4A_PCIEPTCTLR registers allow to define the
base address and role of the different regions (including whether it's
a MEM or IO region). However, practical experience on a SH7786 shows
that if 0xfe100000 is used for LEL and 0xfd000000 for IO, a PCIe
device using two MEM BARs cannot be accessed at all. Simply using
0xfe100000 for IO and 0xfd000000 for MEM makes the PCIe device
accessible.

It is very likely that this was never seen because there are two other
PCI MEM region listed in the resources. However, for different
reasons, none of the two other MEM regions are usable on the specific
SH7786 platform the problem was encountered. Therefore, the last MEM
region at 0xfe100000 was used to place the BARs, making the device
non-functional.

This commit therefore adjusts those PCI MEM and IO resources
definitions so that they match what the datasheet says. They have only
been tested with PCIe 0.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/drivers/pci/pcie-sh7786.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 8d7c328b1899..69da026682ba 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -41,73 +41,73 @@ static struct sh7786_pcie_hwops {
 
 static struct resource sh7786_pci0_resources[] = {
 	{
-		.name	= "PCIe0 IO",
+		.name	= "PCIe0 MEM 0",
 		.start	= 0xfd000000,
 		.end	= 0xfd000000 + SZ_8M - 1,
-		.flags	= IORESOURCE_IO,
+		.flags	= IORESOURCE_MEM,
 	}, {
-		.name	= "PCIe0 MEM 0",
+		.name	= "PCIe0 MEM 1",
 		.start	= 0xc0000000,
 		.end	= 0xc0000000 + SZ_512M - 1,
 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 	}, {
-		.name	= "PCIe0 MEM 1",
+		.name	= "PCIe0 MEM 2",
 		.start	= 0x10000000,
 		.end	= 0x10000000 + SZ_64M - 1,
 		.flags	= IORESOURCE_MEM,
 	}, {
-		.name	= "PCIe0 MEM 2",
+		.name	= "PCIe0 IO",
 		.start	= 0xfe100000,
 		.end	= 0xfe100000 + SZ_1M - 1,
-		.flags	= IORESOURCE_MEM,
+		.flags	= IORESOURCE_IO,
 	},
 };
 
 static struct resource sh7786_pci1_resources[] = {
 	{
-		.name	= "PCIe1 IO",
+		.name	= "PCIe1 MEM 0",
 		.start	= 0xfd800000,
 		.end	= 0xfd800000 + SZ_8M - 1,
-		.flags	= IORESOURCE_IO,
+		.flags	= IORESOURCE_MEM,
 	}, {
-		.name	= "PCIe1 MEM 0",
+		.name	= "PCIe1 MEM 1",
 		.start	= 0xa0000000,
 		.end	= 0xa0000000 + SZ_512M - 1,
 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 	}, {
-		.name	= "PCIe1 MEM 1",
+		.name	= "PCIe1 MEM 2",
 		.start	= 0x30000000,
 		.end	= 0x30000000 + SZ_256M - 1,
 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 	}, {
-		.name	= "PCIe1 MEM 2",
+		.name	= "PCIe1 IO",
 		.start	= 0xfe300000,
 		.end	= 0xfe300000 + SZ_1M - 1,
-		.flags	= IORESOURCE_MEM,
+		.flags	= IORESOURCE_IO,
 	},
 };
 
 static struct resource sh7786_pci2_resources[] = {
 	{
-		.name	= "PCIe2 IO",
+		.name	= "PCIe2 MEM 0",
 		.start	= 0xfc800000,
 		.end	= 0xfc800000 + SZ_4M - 1,
-		.flags	= IORESOURCE_IO,
+		.flags	= IORESOURCE_MEM,
 	}, {
-		.name	= "PCIe2 MEM 0",
+		.name	= "PCIe2 MEM 1",
 		.start	= 0x80000000,
 		.end	= 0x80000000 + SZ_512M - 1,
 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 	}, {
-		.name	= "PCIe2 MEM 1",
+		.name	= "PCIe2 MEM 2",
 		.start	= 0x20000000,
 		.end	= 0x20000000 + SZ_256M - 1,
 		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 	}, {
-		.name	= "PCIe2 MEM 2",
+		.name	= "PCIe2 IO",
 		.start	= 0xfcd00000,
 		.end	= 0xfcd00000 + SZ_1M - 1,
-		.flags	= IORESOURCE_MEM,
+		.flags	= IORESOURCE_IO,
 	},
 };
 
-- 
2.13.6

[PATCH 7/8] arch/sh: pcie-sh7786: adjust the memory mapping

[Thomas Petazzoni]

The code setting up the PCI -> SuperHighway mapping doesn't take into
account the fact that the address stored in PCIELARx must be aligned
with the size stored in PCIELAMRx.

For example, when your physical memory starts at 0x0800_0000 (128 MB),
a size of 64 MB or 128 MB is fine. However, if you have 256 MB of
memory, it doesn't work because the base address is not aligned on the
size.

In such situation, we have to round down the base address to make sure
it is aligned on the size of the area. For for a 0x0800_0000 base
address with 256 MB of memory, we will round down to 0x0, and extend
the size of the mapping to 512 MB.

This allows the mapping to work on platforms that have 256 MB of
RAM. The current setup would only work with 128 MB of RAM or less.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/drivers/pci/pcie-sh7786.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 69da026682ba..224bcad24dca 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -284,7 +284,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
 {
 	struct pci_channel *chan = port->hose;
 	unsigned int data;
-	phys_addr_t memphys;
+	phys_addr_t memstart, memend;
 	size_t memsize;
 	int ret, i, win;
 
@@ -339,15 +339,24 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
 	data |= (0xff << 16);
 	pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
 
-	memphys = __pa(memory_start);
-	memsize = roundup_pow_of_two(memory_end - memory_start);
+	memstart = __pa(memory_start);
+	memend   = __pa(memory_end);
+	memsize = roundup_pow_of_two(memend - memstart);
+
+	/*
+	 * The start address must be aligned on its size. So we round
+	 * it down, and then recalculate the size so that it covers
+	 * the entire memory.
+	 */
+	memstart = ALIGN_DOWN(memstart, memsize);
+	memsize = roundup_pow_of_two(memend - memstart);
 
 	/*
 	 * If there's more than 512MB of memory, we need to roll over to
 	 * LAR1/LAMR1.
 	 */
 	if (memsize > SZ_512M) {
-		pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1);
+		pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1);
 		pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
 			      SH4A_PCIELAMR1);
 		memsize = SZ_512M;
@@ -363,7 +372,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
 	 * LAR0/LAMR0 covers up to the first 512MB, which is enough to
 	 * cover all of lowmem on most platforms.
 	 */
-	pci_write_reg(chan, memphys, SH4A_PCIELAR0);
+	pci_write_reg(chan, memstart, SH4A_PCIELAR0);
 	pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
 
 	/* Finish initialization */
-- 
2.13.6

[PATCH 8/8] arch/sh: pcie-sh7786: handle non-zero DMA offset

[Thomas Petazzoni]

On SuperH, the base of the physical memory might be different from
zero. In this case, PCI address zero will map to a non-zero physical
address. In order to make sure that the DMA mapping API takes care of
this DMA offset, we must fill in the dev->dma_pfn_offset field for PCI
devices. This gets done in the pcibios_bus_add_device() hook, called
for each new PCI device detected.

The dma_pfn_offset global variable is re-calculated for every PCI
controller available on the platform, but that's not an issue because
its value will each time be exactly the same, as it only depends on
the memory start address and memory size.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/sh/drivers/pci/pcie-sh7786.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 224bcad24dca..95f9a3536a93 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -33,6 +33,7 @@ struct sh7786_pcie_port {
 
 static struct sh7786_pcie_port *sh7786_pcie_ports;
 static unsigned int nr_ports;
+static unsigned long dma_pfn_offset;
 
 static struct sh7786_pcie_hwops {
 	int (*core_init)(void);
@@ -351,6 +352,8 @@ static int __init pcie_init(struct sh7786_pcie_port *port)
 	memstart = ALIGN_DOWN(memstart, memsize);
 	memsize = roundup_pow_of_two(memend - memstart);
 
+	dma_pfn_offset = memstart >> PAGE_SHIFT;
+
 	/*
 	 * If there's more than 512MB of memory, we need to roll over to
 	 * LAR1/LAMR1.
@@ -466,6 +469,11 @@ int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
         return evt2irq(0xae0);
 }
 
+void pcibios_bus_add_device(struct pci_dev *pdev)
+{
+	pdev->dev.dma_pfn_offset = dma_pfn_offset;
+}
+
 static int __init sh7786_pcie_core_init(void)
 {
 	/* Return the number of ports */
-- 
2.13.6

Re: [PATCH 0/8] SH7786 PCIe support fixes

[Thomas Petazzoni]

Hello,

On Mon,  4 Dec 2017 16:08:59 +0100, Thomas Petazzoni wrote:

> Thomas Petazzoni (8):
>   arch/sh: add sh7786_mm_sel() function
>   arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset
>   arch/sh: pci: don't use disabled resources
>   arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
>   arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
>   arch/sh: pcie-sh7786: adjust PCI MEM and IO regions
>   arch/sh: pcie-sh7786: adjust the memory mapping
>   arch/sh: pcie-sh7786: handle non-zero DMA offset

It's been a month. Any feedback on those patches ?

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 0/8] SH7786 PCIe support fixes

[Bjorn Helgaas]

On Sun, Jan 07, 2018 at 04:06:27PM +0100, Thomas Petazzoni wrote:
> Hello,
> 
> On Mon,  4 Dec 2017 16:08:59 +0100, Thomas Petazzoni wrote:
> 
> > Thomas Petazzoni (8):
> >   arch/sh: add sh7786_mm_sel() function
> >   arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset
> >   arch/sh: pci: don't use disabled resources
> >   arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
> >   arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
> >   arch/sh: pcie-sh7786: adjust PCI MEM and IO regions
> >   arch/sh: pcie-sh7786: adjust the memory mapping
> >   arch/sh: pcie-sh7786: handle non-zero DMA offset
> 
> It's been a month. Any feedback on those patches ?

I'm assuming Yoshinori and Rich will handle these.  Let me know if
otherwise.

Re: [PATCH 0/8] SH7786 PCIe support fixes

[Thomas Petazzoni]

Hello,

On Mon, 8 Jan 2018 16:12:58 -0600, Bjorn Helgaas wrote:

> > > Thomas Petazzoni (8):
> > >   arch/sh: add sh7786_mm_sel() function
> > >   arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset
> > >   arch/sh: pci: don't use disabled resources
> > >   arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
> > >   arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
> > >   arch/sh: pcie-sh7786: adjust PCI MEM and IO regions
> > >   arch/sh: pcie-sh7786: adjust the memory mapping
> > >   arch/sh: pcie-sh7786: handle non-zero DMA offset  
> > 
> > It's been a month. Any feedback on those patches ?  
> 
> I'm assuming Yoshinori and Rich will handle these.  Let me know if
> otherwise.

Yes, it's all in arch/sh, so I assume the SH maintainers will take care
of those patches. I mainly CC'ed the PCI maintainers + mailing list for
information, and to get additional feedback on PCI specific topics if
there's any.

Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 0/8] SH7786 PCIe support fixes

[Thomas Petazzoni]

Hello,

+Andrew Morton in To.

On Sun, 7 Jan 2018 16:06:27 +0100, Thomas Petazzoni wrote:
> Hello,
> 
> On Mon,  4 Dec 2017 16:08:59 +0100, Thomas Petazzoni wrote:
> 
> > Thomas Petazzoni (8):
> >   arch/sh: add sh7786_mm_sel() function
> >   arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset
> >   arch/sh: pci: don't use disabled resources
> >   arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
> >   arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
> >   arch/sh: pcie-sh7786: adjust PCI MEM and IO regions
> >   arch/sh: pcie-sh7786: adjust the memory mapping
> >   arch/sh: pcie-sh7786: handle non-zero DMA offset  
> 
> It's been a month. Any feedback on those patches ?

It's been another month. Patches have been sent on December 4, pinged
on January 7, we're February 26, and I had no feedback.

Since it's touching a very old SoC that no many people care about
anymore, I do understand the lack of interest. But in this case, could
we please just merge those patches ? If nobody is interested, it is
also unlikely to break things for people, right ?

Andrew, would you be willing to take those patches, which are not
receiving any attention ?

Thanks a lot,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

Re: [PATCH 0/8] SH7786 PCIe support fixes

[Thomas Petazzoni]

Hello,

On Mon,  4 Dec 2017 16:08:59 +0100, Thomas Petazzoni wrote:

> Thomas Petazzoni (8):
>   arch/sh: add sh7786_mm_sel() function
>   arch/sh: make the DMA mapping operations observe dev->dma_pfn_offset
>   arch/sh: pci: don't use disabled resources
>   arch/sh: pcie-sh7786: mark unavailable PCI resource as disabled
>   arch/sh: pcie-sh7786: exclude unusable PCI MEM areas
>   arch/sh: pcie-sh7786: adjust PCI MEM and IO regions
>   arch/sh: pcie-sh7786: adjust the memory mapping
>   arch/sh: pcie-sh7786: handle non-zero DMA offset

It's been more than 2 months, and I haven't received any review on this
patch series.

It is very likely that I am one of the only active user of a SH7786
platform, so I don't think those patches will break things for anybody.
Would it be possible to just merge them ? I doubt anyone will be
interested in doing a very careful and detailed review, since I doubt
anyone is interested in this SH7786 platform anymore.

The only patch that can potentially break things for other is "arch/sh:
make the DMA mapping operations observe dev->dma_pfn_offset" but I
believe it is useful to have it and fix any fallout (which should be
trivial).

So please, please, merge :-)

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com