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[202.79.124.123]) by smtp.gmail.com with ESMTPSA id x10-20020a170902ea8a00b001c20c608373sm9099756plb.296.2023.10.25.05.34.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Oct 2023 05:34:50 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.7\)) Subject: Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU. From: "D. Jeff Dionne" In-Reply-To: Date: Wed, 25 Oct 2023 21:34:46 +0900 Cc: Yoshinori Sato , "open list:SUPERH" , John Paul Adrian Glaubitz , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <2ED29F7F-5DC0-43C6-B125-795D9DA6567B@gmail.com> References: <46ef748dd27127ef9b39fa6c97fe51e8d3422a4f.1697199949.git.ysato@users.sourceforge.jp> <87ttqf6jjq.wl-ysato@users.sourceforge.jp> <38FB33F7-7740-4181-9F0F-902AC7D7C11C@gmail.com> To: Geert Uytterhoeven X-Mailer: Apple Mail (2.3608.120.23.2.7) Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org > On Oct 25, 2023, at 21:17, Geert Uytterhoeven = wrote: >=20 > Hi Jeff, >=20 > On Wed, Oct 25, 2023 at 2:10=E2=80=AFPM D. Jeff Dionne = wrote: >> On Oct 25, 2023, at 21:04, Geert Uytterhoeven = wrote: >>> On Wed, Oct 25, 2023 at 1:33=E2=80=AFPM D. Jeff Dionne = wrote: >>>>> On Oct 25, 2023, at 20:14, Yoshinori Sato = wrote: >>>>> On Wed, 18 Oct 2023 23:27:43 +0900, >>>>> Geert Uytterhoeven wrote: >>>>>> On Sat, Oct 14, 2023 at 4:54=E2=80=AFPM Yoshinori Sato >>>>>> wrote: >>>>>>> Renesas SuperH binding definition. >>>>>>>=20 >>>>>>> Signed-off-by: Yoshinori Sato >>>=20 >>>>>>> --- /dev/null >>>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml >=20 >>>>>>> +properties: >>>>>>> + compatible: >>>>>>> + items: >>>>>>> + - enum: >>>>>>=20 >>>>>> Missing >>>>>>=20 >>>>>> - jcore,j2 >>>=20 >>>> We must not imply that Renesas is responsible for J2, or that it is = a sanctioned SH core. >>>=20 >>> Compatible values do not declare any such endorsement. >>>=20 >>>> J-Core has the responsibility for maintenance of those SH ISA = compatible cores. >>>=20 >>> The question is: does J2 implement the same instruction set as SH2, >>> i.e. can it run unmodified SH2 code? >>=20 >> It can run all SH2 code, but an SH2 cannot run all J2 code. >=20 > This is exactly what >=20 > compatible =3D "jcore,j2", "renesas,sh2"; Oh, yes. I agree, this is correct. Once this is settled upon, we can = change new J2 cores so they will export their ROM device tree with the = sh2 fallback. Down thread, Sato-san proposes =E2=80=9Crenesas,sh4=E2=80=9D, = =E2=80=9Crenesas,sh=E2=80=9D I=E2=80=99m not sure I understand what a = =E2=80=9Crenesas,sh=E2=80=9D base fallback is. J. > represents. > Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification > https://www.devicetree.org/specifications >=20 > Gr{oetje,eeting}s, >=20 > Geert >=20 > --=20 > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- = geert@linux-m68k.org >=20 > In personal conversations with technical people, I call myself a = hacker. But > when I'm talking to journalists I just say "programmer" or something = like that. > -- Linus Torvalds