diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 4ba2c0f..7a09c22 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/pm_runtime.h>
+#include <linux/sh_clk.h>
 #include <linux/sh_timer.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
@@ -92,10 +93,12 @@ static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
 	if (reg_nr == TSTR) {
 		switch (ch->tmu->model) {
 		case SH_TMU_LEGACY:
+			dev_err(&ch->tmu->pdev->dev, "ch%u: reading TSTR @%p\n", ch->index, ch->tmu->mapbase);
 			return ioread8(ch->tmu->mapbase);
 		case SH_TMU_SH3:
 			return ioread8(ch->tmu->mapbase + 2);
 		case SH_TMU:
+			dev_err(&ch->tmu->pdev->dev, "ch%u: reading TSTR @%p\n", ch->index, ch->tmu->mapbase + 4);
 			return ioread8(ch->tmu->mapbase + 4);
 		}
 	}
@@ -116,10 +119,12 @@ static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
 	if (reg_nr == TSTR) {
 		switch (ch->tmu->model) {
 		case SH_TMU_LEGACY:
+			dev_err(&ch->tmu->pdev->dev, "ch%u: reading TSTR @%p\n", ch->index, ch->tmu->mapbase);
 			return iowrite8(value, ch->tmu->mapbase);
 		case SH_TMU_SH3:
 			return iowrite8(value, ch->tmu->mapbase + 2);
 		case SH_TMU:
+			dev_err(&ch->tmu->pdev->dev, "ch%u: writing TSTR @%p\n", ch->index, ch->tmu->mapbase + 4);
 			return iowrite8(value, ch->tmu->mapbase + 4);
 		}
 	}
@@ -170,6 +175,7 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)
 
 	/* configure channel to parent clock / 4, irq off */
 	ch->rate = clk_get_rate(ch->tmu->clk) / 4;
+	dev_err(&ch->tmu->pdev->dev, "ch%u: clock rate is %lu\n", ch->index, ch->rate);
 	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
 
 	/* enable channel */
@@ -443,6 +449,8 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
 
 	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
 
+	dev_info(&ch->tmu->pdev->dev, "ch%u: requesting IRQ %u for clock event device\n",
+		 ch->index, ch->irq);
 	ret = request_irq(ch->irq, sh_tmu_interrupt,
 			  IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 			  dev_name(&ch->tmu->pdev->dev), ch);
@@ -498,6 +506,9 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
 			ch->base = tmu->mapbase + 8 + ch->index * 12;
 	}
 
+	dev_info(&tmu->pdev->dev, "ch%u: base %p\n",
+		 ch->index, ch->base);
+
 	ch->irq = platform_get_irq(tmu->pdev, ch->index);
 	if (ch->irq < 0) {
 		dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
@@ -526,6 +537,9 @@ static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
 	if (tmu->mapbase == NULL)
 		return -ENXIO;
 
+	dev_info(&tmu->pdev->dev, "phys base 0x%08x virt base %p size %u\n",
+		res->start, tmu->mapbase, resource_size(res));
+
 	/*
 	 * In legacy platform device configuration (with one device per channel)
 	 * the resource points to the channel base address.
@@ -571,6 +585,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
 		return PTR_ERR(tmu->clk);
 	}
 
+	dev_err(&tmu->pdev->dev, "MSTP clock %u @%p\n", tmu->clk->enable_bit, tmu->clk->enable_reg);
 	ret = clk_prepare(tmu->clk);
 	if (ret < 0)
 		goto err_clk_put;