Hi all
I would propose an other version of suspend in ram.

In ST we have several constraints:
- Several SOCs with different Clock IPs
- No cache memory mapped (it was removed in recently version of ST40)
- No IPREF instruction..
- 29/32 bits supports (where in 32 bits we are managing the PMB in a 
different manner respect the original kernel.org code).

For these reason an hard-coded suspend assembly code isn't easy to use 
for us.

To address the issue we are using a mini interpreter able to execute 
macro instructions SOC based.
The assembly code preloads (with a jump sequence) in cache (both I$ and 
D$) the 'instruction-table'
and after that it executes the instruction-table.

This solution allow me to have no assembly code SOCs specific and
for each SOC I have only to produce the right "tables" for standby 
and/or mem-standby.

Moreover a 3rd table is supported to be able to produce or save data on 
the fly for the standby it-self (for example if we have different action 
on the same SOC but different Cut).

Let me know.
Regards
Francesco

P.S.: in attach an example on how I'm using the suspend core code.