From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Dooks Date: Mon, 31 Mar 2014 14:30:00 +0000 Subject: Re: [PATCH 4/5] ARM: shmobile: r8a7791: Add IPMMU DT nodes Message-Id: <53397BE8.6030707@codethink.co.uk> List-Id: References: <1396049781-12941-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com> <1396049781-12941-5-git-send-email-laurent.pinchart+renesas@ideasonboard.com> <2517875.vv2t3ch4DC@avalon> In-Reply-To: <2517875.vv2t3ch4DC@avalon> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Laurent Pinchart , Geert Uytterhoeven Cc: Laurent Pinchart , iommu@lists.linux-foundation.org, Linux-sh list On 31/03/14 15:01, Laurent Pinchart wrote: > Hi Geert, > > On Monday 31 March 2014 10:52:28 Geert Uytterhoeven wrote: >> On Sat, Mar 29, 2014 at 12:36 AM, Laurent Pinchart wrote: >>> + ipmmu_sy0: mmu@e6280800 { >>> + compatible = "renesas,ipmmu-vmsa"; >>> + reg = <0 0xe6280800 0 0x800>; >> >> Shouldn't this be "reg = <0 0xe6280000 0 0x1000>", i.e. expose both >> banks? >> >> Is there any specific reason you're using the second bank of registers? >> These may read as zero, depending on the SoC mode. > > That's a very good question, and I have no clear answer. According to the > datasheet the second bank of registers is an alias for the non-secure IPMMU > registers. It looks like we're running in secure mode (that's what I assume > the "CPU: All CPU(s) started in SVC mode." kernel log message means), and the > secure IPMMU didn't seem to be functional when I've tested it. > > This requires more investigation, but I'm not familiar with secure mode, and > the IPMMU documentation is really sparse in that area. The default for the R8A7790 is to start in secure-svc mode. I would test it in non-secure SVC but the security framework we are using blocks access to the IPMMU blocks :/ -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius