* [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
@ 2014-03-31 14:50 Ben Dooks
2014-03-31 18:13 ` Mike Turquette
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Ben Dooks @ 2014-03-31 14:50 UTC (permalink / raw)
To: linux-sh
The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks
parented to pll1_div2 where the hardware diagram shows these to be
directly fed from pll1.
This fixes the initial rate for sdh0 clock to be 97.5MHz instead of
the reported 48MHz where the manual says the default register values
are for 97.5MHz.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-sh@vger.kernel.org
Cc: Simon Horman <horms+renesas@verge.net.au>
---
drivers/clk/shmobile/clk-rcar-gen2.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 01cb49c..7c6be44 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -249,22 +249,22 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
parent_name = "main";
mult = config->pll3_mult;
} else if (!strcmp(name, "lb")) {
- parent_name = "pll1_div2";
+ parent_name = "pll1";
div = cpg_mode & BIT(18) ? 36 : 24;
} else if (!strcmp(name, "qspi")) {
parent_name = "pll1_div2";
div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) = BIT(2)
? 8 : 10;
} else if (!strcmp(name, "sdh")) {
- parent_name = "pll1_div2";
+ parent_name = "pll1";
table = cpg_sdh_div_table;
shift = 8;
} else if (!strcmp(name, "sd0")) {
- parent_name = "pll1_div2";
+ parent_name = "pll1";
table = cpg_sd01_div_table;
shift = 4;
} else if (!strcmp(name, "sd1")) {
- parent_name = "pll1_div2";
+ parent_name = "pll1";
table = cpg_sd01_div_table;
shift = 0;
} else if (!strcmp(name, "z")) {
--
1.9.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
2014-03-31 14:50 [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 Ben Dooks
@ 2014-03-31 18:13 ` Mike Turquette
2014-03-31 23:38 ` Laurent Pinchart
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Mike Turquette @ 2014-03-31 18:13 UTC (permalink / raw)
To: linux-sh
Quoting Ben Dooks (2014-03-31 07:50:34)
> The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks
> parented to pll1_div2 where the hardware diagram shows these to be
> directly fed from pll1.
>
> This fixes the initial rate for sdh0 clock to be 97.5MHz instead of
> the reported 48MHz where the manual says the default register values
> are for 97.5MHz.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Taken into clk-next.
Regards,
Mike
> ---
> Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: linux-sh@vger.kernel.org
> Cc: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/clk/shmobile/clk-rcar-gen2.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
> index 01cb49c..7c6be44 100644
> --- a/drivers/clk/shmobile/clk-rcar-gen2.c
> +++ b/drivers/clk/shmobile/clk-rcar-gen2.c
> @@ -249,22 +249,22 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
> parent_name = "main";
> mult = config->pll3_mult;
> } else if (!strcmp(name, "lb")) {
> - parent_name = "pll1_div2";
> + parent_name = "pll1";
> div = cpg_mode & BIT(18) ? 36 : 24;
> } else if (!strcmp(name, "qspi")) {
> parent_name = "pll1_div2";
> div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) = BIT(2)
> ? 8 : 10;
> } else if (!strcmp(name, "sdh")) {
> - parent_name = "pll1_div2";
> + parent_name = "pll1";
> table = cpg_sdh_div_table;
> shift = 8;
> } else if (!strcmp(name, "sd0")) {
> - parent_name = "pll1_div2";
> + parent_name = "pll1";
> table = cpg_sd01_div_table;
> shift = 4;
> } else if (!strcmp(name, "sd1")) {
> - parent_name = "pll1_div2";
> + parent_name = "pll1";
> table = cpg_sd01_div_table;
> shift = 0;
> } else if (!strcmp(name, "z")) {
> --
> 1.9.0
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
2014-03-31 14:50 [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 Ben Dooks
2014-03-31 18:13 ` Mike Turquette
@ 2014-03-31 23:38 ` Laurent Pinchart
2014-04-01 0:00 ` Mike Turquette
2014-04-01 9:53 ` Ben Dooks
3 siblings, 0 replies; 5+ messages in thread
From: Laurent Pinchart @ 2014-03-31 23:38 UTC (permalink / raw)
To: linux-sh
Hi Mike,
On Monday 31 March 2014 11:13:10 Mike Turquette wrote:
> Quoting Ben Dooks (2014-03-31 07:50:34)
>
> > The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks
> > parented to pll1_div2 where the hardware diagram shows these to be
> > directly fed from pll1.
> >
> > This fixes the initial rate for sdh0 clock to be 97.5MHz instead of
> > the reported 48MHz where the manual says the default register values
> > are for 97.5MHz.
> >
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>
> Taken into clk-next.
I'm glad to see the clock patches being applied quickly, but it would make
sense to wait at least a couple of days for acks or nacks :-) In this case the
patch looks good to me, so there's no issue.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: Mike Turquette <mturquette@linaro.org>
> > Cc: linux-sh@vger.kernel.org
> > Cc: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >
> > drivers/clk/shmobile/clk-rcar-gen2.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c
> > b/drivers/clk/shmobile/clk-rcar-gen2.c index 01cb49c..7c6be44 100644
> > --- a/drivers/clk/shmobile/clk-rcar-gen2.c
> > +++ b/drivers/clk/shmobile/clk-rcar-gen2.c
> > @@ -249,22 +249,22 @@ rcar_gen2_cpg_register_clock(struct device_node *np,
> > struct rcar_gen2_cpg *cpg,>
> > parent_name = "main";
> > mult = config->pll3_mult;
> >
> > } else if (!strcmp(name, "lb")) {
> >
> > - parent_name = "pll1_div2";
> > + parent_name = "pll1";
> >
> > div = cpg_mode & BIT(18) ? 36 : 24;
> >
> > } else if (!strcmp(name, "qspi")) {
> >
> > parent_name = "pll1_div2";
> > div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) = BIT(2)
> >
> > ? 8 : 10;
> >
> > } else if (!strcmp(name, "sdh")) {
> >
> > - parent_name = "pll1_div2";
> > + parent_name = "pll1";
> >
> > table = cpg_sdh_div_table;
> > shift = 8;
> >
> > } else if (!strcmp(name, "sd0")) {
> >
> > - parent_name = "pll1_div2";
> > + parent_name = "pll1";
> >
> > table = cpg_sd01_div_table;
> > shift = 4;
> >
> > } else if (!strcmp(name, "sd1")) {
> >
> > - parent_name = "pll1_div2";
> > + parent_name = "pll1";
> >
> > table = cpg_sd01_div_table;
> > shift = 0;
> >
> > } else if (!strcmp(name, "z")) {
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
2014-03-31 14:50 [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 Ben Dooks
2014-03-31 18:13 ` Mike Turquette
2014-03-31 23:38 ` Laurent Pinchart
@ 2014-04-01 0:00 ` Mike Turquette
2014-04-01 9:53 ` Ben Dooks
3 siblings, 0 replies; 5+ messages in thread
From: Mike Turquette @ 2014-04-01 0:00 UTC (permalink / raw)
To: linux-sh
Quoting Laurent Pinchart (2014-03-31 16:38:55)
> Hi Mike,
>
> On Monday 31 March 2014 11:13:10 Mike Turquette wrote:
> > Quoting Ben Dooks (2014-03-31 07:50:34)
> >
> > > The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks
> > > parented to pll1_div2 where the hardware diagram shows these to be
> > > directly fed from pll1.
> > >
> > > This fixes the initial rate for sdh0 clock to be 97.5MHz instead of
> > > the reported 48MHz where the manual says the default register values
> > > are for 97.5MHz.
> > >
> > > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> >
> > Taken into clk-next.
>
> I'm glad to see the clock patches being applied quickly, but it would make
> sense to wait at least a couple of days for acks or nacks :-) In this case the
> patch looks good to me, so there's no issue.
Normally I would, and I did hesitate on the point of waiting for your
Ack. However the change is a trivial fix and I wanted to get this into
my pull request for 3.15, so it's not an ordinary circumstance. I've
added your Ack now.
Regards,
Mike
>
> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> > > ---
> > > Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > Cc: Mike Turquette <mturquette@linaro.org>
> > > Cc: linux-sh@vger.kernel.org
> > > Cc: Simon Horman <horms+renesas@verge.net.au>
> > > ---
> > >
> > > drivers/clk/shmobile/clk-rcar-gen2.c | 8 ++++----
> > > 1 file changed, 4 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c
> > > b/drivers/clk/shmobile/clk-rcar-gen2.c index 01cb49c..7c6be44 100644
> > > --- a/drivers/clk/shmobile/clk-rcar-gen2.c
> > > +++ b/drivers/clk/shmobile/clk-rcar-gen2.c
> > > @@ -249,22 +249,22 @@ rcar_gen2_cpg_register_clock(struct device_node *np,
> > > struct rcar_gen2_cpg *cpg,>
> > > parent_name = "main";
> > > mult = config->pll3_mult;
> > >
> > > } else if (!strcmp(name, "lb")) {
> > >
> > > - parent_name = "pll1_div2";
> > > + parent_name = "pll1";
> > >
> > > div = cpg_mode & BIT(18) ? 36 : 24;
> > >
> > > } else if (!strcmp(name, "qspi")) {
> > >
> > > parent_name = "pll1_div2";
> > > div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) = BIT(2)
> > >
> > > ? 8 : 10;
> > >
> > > } else if (!strcmp(name, "sdh")) {
> > >
> > > - parent_name = "pll1_div2";
> > > + parent_name = "pll1";
> > >
> > > table = cpg_sdh_div_table;
> > > shift = 8;
> > >
> > > } else if (!strcmp(name, "sd0")) {
> > >
> > > - parent_name = "pll1_div2";
> > > + parent_name = "pll1";
> > >
> > > table = cpg_sd01_div_table;
> > > shift = 4;
> > >
> > > } else if (!strcmp(name, "sd1")) {
> > >
> > > - parent_name = "pll1_div2";
> > > + parent_name = "pll1";
> > >
> > > table = cpg_sd01_div_table;
> > > shift = 0;
> > >
> > > } else if (!strcmp(name, "z")) {
>
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1
2014-03-31 14:50 [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 Ben Dooks
` (2 preceding siblings ...)
2014-04-01 0:00 ` Mike Turquette
@ 2014-04-01 9:53 ` Ben Dooks
3 siblings, 0 replies; 5+ messages in thread
From: Ben Dooks @ 2014-04-01 9:53 UTC (permalink / raw)
To: linux-sh
On 01/04/14 01:00, Mike Turquette wrote:
> Quoting Laurent Pinchart (2014-03-31 16:38:55)
>> Hi Mike,
>>
>> On Monday 31 March 2014 11:13:10 Mike Turquette wrote:
>>> Quoting Ben Dooks (2014-03-31 07:50:34)
>>>
>>>> The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks
>>>> parented to pll1_div2 where the hardware diagram shows these to be
>>>> directly fed from pll1.
>>>>
>>>> This fixes the initial rate for sdh0 clock to be 97.5MHz instead of
>>>> the reported 48MHz where the manual says the default register values
>>>> are for 97.5MHz.
>>>>
>>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>>
>>> Taken into clk-next.
>>
>> I'm glad to see the clock patches being applied quickly, but it would make
>> sense to wait at least a couple of days for acks or nacks :-) In this case the
>> patch looks good to me, so there's no issue.
>
> Normally I would, and I did hesitate on the point of waiting for your
> Ack. However the change is a trivial fix and I wanted to get this into
> my pull request for 3.15, so it's not an ordinary circumstance. I've
> added your Ack now.
This isn't exactly a trivial fix. I know it works for the R8A7790 but
it may not work for all rcar-gen2.
Thanks for sorting this.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
^ permalink raw reply [flat|nested] 5+ messages in thread
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2014-03-31 14:50 [PATCH] clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 Ben Dooks
2014-03-31 18:13 ` Mike Turquette
2014-03-31 23:38 ` Laurent Pinchart
2014-04-01 0:00 ` Mike Turquette
2014-04-01 9:53 ` Ben Dooks
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