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From: Marc Zyngier <marc.zyngier@arm.com>
To: Rich Felker <dalias@libc.org>,
	linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH v2 08/12] irqchip: add J-Core AIC driver
Date: Fri, 20 May 2016 08:15:56 +0000	[thread overview]
Message-ID: <573EC7BC.6070709@arm.com> (raw)
In-Reply-To: <2afd392ff334c996970e3a9eacdd5ec5d839b608.1463708766.git.dalias@libc.org>

On 20/05/16 03:53, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> My previous post of the patch series accidentally omitted omitted
> Cc'ing of subsystem maintainers for the necessary clocksource,
> irqchip, and spi drivers. Please ack if this looks ok because I want
> to get it merged as part of the arch/sh pull request for 4.7.

For a start, a decent commit message wouldn't hurt.

> 
>  drivers/irqchip/Kconfig         |  6 +++
>  drivers/irqchip/Makefile        |  1 +
>  drivers/irqchip/irq-jcore-aic.c | 95 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 102 insertions(+)
>  create mode 100644 drivers/irqchip/irq-jcore-aic.c
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3e12479..3cb37d6 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -149,6 +149,12 @@ config PIC32_EVIC
>  	select GENERIC_IRQ_CHIP
>  	select IRQ_DOMAIN
>  
> +config JCORE_AIC
> +	bool "J-Core integrated AIC"
> +	select IRQ_DOMAIN
> +	help
> +	  Support for the J-Core integrated AIC.
> +
>  config RENESAS_INTC_IRQPIN
>  	bool
>  	select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b03cfcb..5a1f1bf 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_I8259)			+= irq-i8259.o
>  obj-$(CONFIG_IMGPDC_IRQ)		+= irq-imgpdc.o
>  obj-$(CONFIG_IRQ_MIPS_CPU)		+= irq-mips-cpu.o
>  obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
> +obj-$(CONFIG_JCORE_AIC)			+= irq-jcore-aic.o
>  obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
>  obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
>  obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
> diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
> new file mode 100644
> index 0000000..68178fb
> --- /dev/null
> +++ b/drivers/irqchip/irq-jcore-aic.c
> @@ -0,0 +1,95 @@
> +/*
> + * J-Core SoC AIC driver
> + *
> + * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
> +#include <linux/cpu.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#define AIC1_INTPRI 8
> +
> +struct aic_data {
> +	unsigned char __iomem *base;
> +	u32 cpu_offset;
> +	struct irq_chip chip;
> +	struct irq_domain *domain;
> +	struct notifier_block nb;
> +} aic_data;
> +
> +static int aic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
> +{
> +	struct aic_data *aic = d->host_data;
> +
> +	irq_set_chip_data(irq, aic);
> +	irq_set_chip_and_handler(irq, &aic->chip, handle_simple_irq);
> +	irq_set_probe(irq);
> +
> +	return 0;
> +}
> +
> +static const struct irq_domain_ops aic_irqdomain_ops = {
> +	.map = aic_irqdomain_map,
> +	.xlate = irq_domain_xlate_onecell,
> +};
> +
> +static void noop(struct irq_data *data)
> +{
> +}
> +
> +static void aic1_localenable(struct aic_data *aic)
> +{
> +	unsigned cpu = smp_processor_id();
> +	pr_info("Local AIC enable on cpu %u\n", cpu);
> +	writel(0xffffffff, aic->base + cpu * aic->cpu_offset + AIC1_INTPRI);
> +}
> +
> +static int aic1_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
> +{
> +	switch (action & ~CPU_TASKS_FROZEN) {
> +	case CPU_STARTING:
> +		aic1_localenable(container_of(self, struct aic_data, nb));
> +		break;
> +	}

And nothing happens when the CPU goes down?

> +	return NOTIFY_OK;
> +}
> +
> +int __init aic_irq_of_init(struct device_node *node, struct device_node *parent)
> +{
> +	struct aic_data *aic = &aic_data;
> +
> +	aic->base = of_iomap(node, 0);
> +	of_property_read_u32(node, "cpu-offset", &aic->cpu_offset);
> +
> +	pr_info("Initializing J-Core AIC at %p\n", aic->base);
> +
> +	if (of_device_is_compatible(node, "jcore,aic1")) {
> +		/* For aic1, need to enabled zero-priority-by-default irqs */
> +		aic->nb.notifier_call = aic1_cpu_notify;
> +		register_cpu_notifier(&aic->nb);
> +		aic1_localenable(aic);
> +	}
> +
> +	aic->chip.name = node->name;
> +	aic->chip.irq_mask = noop;
> +	aic->chip.irq_unmask = noop;

So this driver is doing exactly nothing. Not even an EOI. How does it
work? How is this driver involved in the interrupt flow?

> +
> +	aic->domain = irq_domain_add_linear(node, 128, &aic_irqdomain_ops, aic);

The DT binding says that aic1 has 8 interrupts, and aic2 has 64. Why are
you allocating 128 of them?

> +	irq_create_strict_mappings(aic->domain, 16, 16, 112);

What are the first 16 interrupts for? By the look of it, this is a
legacy domain in disguise.

> +
> +	return 0;
> +}
> +
> +IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
> +IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);
> 

To be honest, this doesn't look like an irqchip driver. More like a
glorified probe function. Maybe this is a property of the architecture,
but I'd really like at least a comment explaining this.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  parent reply	other threads:[~2016-05-20  8:15 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-20  2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
2016-05-20  2:53 ` [PATCH v2 02/12] of: add J-Core cpu bindings Rich Felker
     [not found]   ` <f3c89e4834665790ff13478c571cc9aaa9de5559.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-23 20:48     ` Rob Herring
2016-05-23 21:03       ` Rich Felker
2016-05-23 23:29         ` Rob Herring
2016-05-24  2:39           ` Rich Felker
2016-05-24 21:30           ` Rob Landley
2016-05-25  1:13             ` Rob Herring
2016-05-25  2:33               ` Rich Felker
2016-05-25 13:13                 ` Rob Herring
2016-05-20  2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-20  8:05   ` Geert Uytterhoeven
2016-05-23 21:00   ` Rob Herring
2016-05-23 21:06     ` Rich Felker
     [not found]       ` <20160523210618.GF21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-23 23:16         ` Rob Herring
2016-05-20  2:53 ` [PATCH v2 08/12] irqchip: add J-Core AIC driver Rich Felker
2016-05-20  8:08   ` Geert Uytterhoeven
2016-05-20  8:15   ` Marc Zyngier [this message]
2016-05-25  4:29     ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 10/12] spi: add driver for J-Core SPI controller Rich Felker
2016-05-20  8:15   ` Geert Uytterhoeven
2016-05-20 22:50     ` Rich Felker
2016-05-20 10:23   ` Mark Brown
2016-05-20 23:24     ` Rich Felker
2016-05-23 15:30       ` Mark Brown
2016-05-23 20:29         ` Rich Felker
     [not found]           ` <20160523202938.GD21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-23 22:11             ` Mark Brown
2016-05-20  2:53 ` [PATCH v2 11/12] sh: add defconfig for J-Core J2 Rich Felker
2016-05-20  2:53 ` [PATCH v2 06/12] sh: add support for J-Core J2 processor Rich Felker
2016-05-20  2:53 ` [PATCH v2 07/12] sh: add AT_HWCAP flag for J-Core cas.l instruction Rich Felker
2016-05-20  2:53 ` [PATCH v2 09/12] clocksource: add J-Core PIT/RTC driver Rich Felker
2016-05-20 14:01   ` Daniel Lezcano
2016-05-21  3:15     ` Rich Felker
2016-05-21 15:55       ` Rob Landley
2016-05-23 20:32       ` Daniel Lezcano
2016-05-24  2:25         ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
2016-05-20  8:04   ` Geert Uytterhoeven
     [not found]     ` <CAMuHMdVs9=8BGwmCBuYch2abJBnCLKoEx7i3EMghW3UUjXc7dA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-05-20 22:34       ` Rich Felker
2016-05-21 18:07         ` Geert Uytterhoeven
2016-05-21 19:17           ` Rich Felker
2016-05-23 20:53   ` Rob Herring
2016-05-23 21:13     ` Rich Felker
     [not found]       ` <20160523211342.GG21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-24  8:09         ` Marc Zyngier
     [not found]           ` <57440C45.5040105-5wv7dgnIgG8@public.gmane.org>
2016-05-25  2:25             ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
2016-05-20  8:03   ` Geert Uytterhoeven
     [not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20  2:53   ` [PATCH v2 01/12] of: add vendor prefix for J-Core Rich Felker
2016-05-23 20:49     ` Rob Herring
2016-05-20  2:53   ` [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
     [not found]     ` <9960d6526523727d1bee3d11c6704e09e600c6fe.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20  8:17       ` Geert Uytterhoeven
2016-05-20 22:42         ` Rich Felker

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