From mboxrd@z Thu Jan 1 00:00:00 1970 From: Logan Gunthorpe Date: Mon, 02 Mar 2020 21:20:07 +0000 Subject: Re: [PATCH v3 7/7] mm/memremap: Set caching mode for PCI P2PDMA memory to WC Message-Id: <6e2591ad-4605-aba4-c7b8-2345940e91b4@deltatee.com> List-Id: References: <20200221182503.28317-1-logang@deltatee.com> <20200221182503.28317-8-logang@deltatee.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Dan Williams Cc: linux-ia64@vger.kernel.org, Linux-sh , Peter Zijlstra , Catalin Marinas , Dave Hansen , platform-driver-x86@vger.kernel.org, Linux MM , Will Deacon , Christoph Hellwig , linux-s390 , David Hildenbrand , Jason Gunthorpe , Ingo Molnar , Benjamin Herrenschmidt , Borislav Petkov , Andy Lutomirski , Thomas Gleixner , Michal Hocko , Linux ARM , Eric Badger , Linux Kernel Mailing List , Andrew Morton , linuxppc-dev On 2020-02-29 3:47 p.m., Dan Williams wrote: > On Fri, Feb 21, 2020 at 10:25 AM Logan Gunthorpe wrote: >> >> PCI BAR IO memory should never be mapped as WB, however prior to this >> the PAT bits were set WB and it was typically overridden by MTRR >> registers set by the firmware. >> >> Set PCI P2PDMA memory to be WC (writecombining) as the only current >> user (the NVMe CMB) was originally mapped WC before the P2PDMA code >> replaced the mapping with devm_memremap_pages(). > > Will the change to UC regress this existing use case? I don't think so. They've been essentially mapped UC for a long time now (since the P2PDMA patch set was merged) and nobody has complained.