* [RFC PATCH v3 01/35] arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 17:11 ` Sergei Shtylyov
2023-10-14 14:53 ` [RFC PATCH v3 02/35] arch/sh/boards/Kconfig: unified OF supported targets Yoshinori Sato
` (34 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
R4 is caller saved in SH ABI.
Save it so it doesn't get corrupted until it's needed for initialization.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/compressed/head_32.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 7bb168133dbb..c5227ef636c3 100644
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -15,7 +15,8 @@ startup:
/* Load initial status register */
mov.l init_sr, r1
ldc r1, sr
-
+ /* Save FDT address */
+ mov r4, r13
/* Move myself to proper location if necessary */
mova 1f, r0
mov.l 1f, r2
@@ -84,7 +85,7 @@ l1:
/* Jump to the start of the decompressed kernel */
mov.l kernel_start_addr, r0
jmp @r0
- nop
+ mov r13,r4
.align 2
bss_start_addr:
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 01/35] arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function.
2023-10-14 14:53 ` [RFC PATCH v3 01/35] arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function Yoshinori Sato
@ 2023-10-14 17:11 ` Sergei Shtylyov
0 siblings, 0 replies; 88+ messages in thread
From: Sergei Shtylyov @ 2023-10-14 17:11 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: glaubitz
On 10/14/23 5:53 PM, Yoshinori Sato wrote:
> R4 is caller saved in SH ABI.
> Save it so it doesn't get corrupted until it's needed for initialization.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> arch/sh/boot/compressed/head_32.S | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
> index 7bb168133dbb..c5227ef636c3 100644
> --- a/arch/sh/boot/compressed/head_32.S
> +++ b/arch/sh/boot/compressed/head_32.S
> @@ -15,7 +15,8 @@ startup:
> /* Load initial status register */
> mov.l init_sr, r1
> ldc r1, sr
> -
> + /* Save FDT address */
> + mov r4, r13
> /* Move myself to proper location if necessary */
> mova 1f, r0
> mov.l 1f, r2
> @@ -84,7 +85,7 @@ l1:
> /* Jump to the start of the decompressed kernel */
> mov.l kernel_start_addr, r0
> jmp @r0
> - nop
> + mov r13,r4
I thought the usual convention for the delay slots is to do extra indentation
with 1 space, no? And you need a space after comma too... :-)
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 02/35] arch/sh/boards/Kconfig: unified OF supported targets.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 01/35] arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 03/35] arch/sh: Disable SH specific modules in OF enabled Yoshinori Sato
` (33 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Targets that support OF should be treated as one board.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boards/Kconfig | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index fafe15d3ba1d..745543e4fece 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -19,16 +19,10 @@ config SH_DEVICE_TREE
select TIMER_OF
select COMMON_CLK
select GENERIC_CALIBRATE_DELAY
-
-config SH_JCORE_SOC
- bool "J-Core SoC"
- select SH_DEVICE_TREE
- select CLKSRC_JCORE_PIT
- select JCORE_AIC
- depends on CPU_J2
- help
- Select this option to include drivers core components of the
- J-Core SoC, including interrupt controllers and timers.
+ select GENERIC_IOMAP
+ select GENERIC_IRQ_CHIP
+ select SYS_SUPPORTS_PCI
+ select GENERIC_PCI_IOMAP if PCI
config SH_SOLUTION_ENGINE
bool "SolutionEngine"
@@ -300,6 +294,7 @@ config SH_LANDISK
bool "LANDISK"
depends on CPU_SUBTYPE_SH7751R
select HAVE_PCI
+ select SYS_SUPPORTS_PCI
help
I-O DATA DEVICE, INC. "LANDISK Series" support.
@@ -376,6 +371,16 @@ config SH_APSH4AD0A
help
Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A.
+config SH_OF_BOARD
+ bool "General Open Firmware boards"
+ select SH_DEVICE_TREE
+ select CLKSRC_JCORE_PIT if CPU_J2
+ select JCORE_AIC if CPU_J2
+ select HAVE_PCI if CPU_SUBTYPE_SH7751R
+ help
+ This board means general OF supported targets.
+
+
source "arch/sh/boards/mach-r2d/Kconfig"
source "arch/sh/boards/mach-highlander/Kconfig"
source "arch/sh/boards/mach-sdk7780/Kconfig"
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 03/35] arch/sh: Disable SH specific modules in OF enabled.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 01/35] arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 02/35] arch/sh/boards/Kconfig: unified OF supported targets Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 04/35] include/linux/sh_intc.h: Add stub function "intc_finalize" Yoshinori Sato
` (32 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
IRQ, CLK and PCI will be migrated to a common driver.
So if OF, disable the SH specific driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/Kconfig | 7 ++++---
arch/sh/drivers/Makefile | 2 ++
arch/sh/kernel/cpu/Makefile | 9 +++++++--
arch/sh/kernel/cpu/sh4/Makefile | 2 ++
4 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 33530b044953..a03dbfc92aad 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -65,10 +65,10 @@ config SUPERH
select MODULES_USE_ELF_RELA
select NEED_SG_DMA_LENGTH
select NO_DMA if !MMU && !DMA_COHERENT
- select NO_GENERIC_PCI_IOPORT_MAP if PCI
+ select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE
select OLD_SIGACTION
select OLD_SIGSUSPEND
- select PCI_DOMAINS if PCI
+ select PCI_DOMAINS if PCI && !SH_DEVICE_TREE
select PERF_EVENTS
select PERF_USE_VMALLOC
select RTC_LIB
@@ -179,7 +179,7 @@ config CPU_SH4
select CPU_HAS_INTEVT
select CPU_HAS_SR_RB
select CPU_HAS_FPU if !CPU_SH4AL_DSP
- select SH_INTC
+ select SH_INTC if !SH_DEVICE_TREE
select SYS_SUPPORTS_SH_TMU
config CPU_SH4A
@@ -527,6 +527,7 @@ config SH_PCLK_FREQ
config SH_CLK_CPG
def_bool y
+ depends on !COMMON_CLK
config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG
diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile
index 56b0acace6e7..eacbcefb26b2 100644
--- a/arch/sh/drivers/Makefile
+++ b/arch/sh/drivers/Makefile
@@ -5,7 +5,9 @@
obj-y += dma/ platform_early.o
+ifndef CONFIG_SH_DEVICE_TREE
obj-$(CONFIG_PCI) += pci/
+endif
obj-$(CONFIG_SUPERHYWAY) += superhyway/
obj-$(CONFIG_PUSH_SWITCH) += push-switch.o
obj-$(CONFIG_HEARTBEAT) += heartbeat.o
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 46118236bf04..e00ebf134985 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -16,6 +16,11 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
# Common interfaces.
obj-$(CONFIG_SH_ADC) += adc.o
+ifndef CONFIG_COMMON_CLK
+obj-y += clock.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
-
-obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o
+endif
+ifndef CONFIG_GENERIC_IRQ_CHIP
+obj-y += irq/
+endif
+obj-y += init.o fpu.o pfc.o proc.o
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 00c16331e07e..d8c3242c4a9f 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o
+ifndef CONFIG_SH_DEVICE_TREE
# CPU subtype setup
obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -32,6 +33,7 @@ endif
# Additional clocks by subtype
clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
+endif # CONFIG_SH_DEVICE_TREE
obj-y += $(clock-y)
obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 04/35] include/linux/sh_intc.h: Add stub function "intc_finalize".
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (2 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 03/35] arch/sh: Disable SH specific modules in OF enabled Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 05/35] arch/sh/kernel/setup.c: Update DT support Yoshinori Sato
` (31 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, Geert Uytterhoeven
This function is not used with OF.
Using a static inline function avoids an external call.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/linux/sh_intc.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index 27ae79191bdc..994b5b05a0d7 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -139,8 +139,13 @@ struct intc_desc symbol __initdata = { \
int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
+#ifndef CONFIG_SH_DEVICE_TREE
void intc_finalize(void);
-
+#else
+static inline void intc_finalize(void)
+{
+}
+#endif
#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 05/35] arch/sh/kernel/setup.c: Update DT support.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (3 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 04/35] include/linux/sh_intc.h: Add stub function "intc_finalize" Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-19 10:01 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup Yoshinori Sato
` (30 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Fix fdt initialize.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/kernel/setup.c | 36 +++++++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index b3da2757faaf..8fdbb9836134 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -31,6 +31,7 @@
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
#include <linux/uaccess.h>
#include <uapi/linux/mount.h>
#include <asm/io.h>
@@ -79,7 +80,13 @@ extern int root_mountflags;
#define RAMDISK_PROMPT_FLAG 0x8000
#define RAMDISK_LOAD_FLAG 0x4000
+#if defined(CONFIG_OF) || !defined(USE_BUILTIN_DTB)
+#define CHOSEN_BOOTARGS
+#endif
+
+#ifndef CHOSEN_BOOTARGS
static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, };
+#endif
static struct resource code_resource = {
.name = "Kernel code",
@@ -104,6 +111,8 @@ unsigned long memory_limit = 0;
static struct resource mem_resources[MAX_NUMNODES];
+static void *dt_virt;
+
int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
static int __init early_parse_mem(char *p)
@@ -249,7 +258,6 @@ void __init __weak plat_early_device_setup(void)
void __ref sh_fdt_init(phys_addr_t dt_phys)
{
static int done = 0;
- void *dt_virt;
/* Avoid calling an __init function on secondary cpus. */
if (done) return;
@@ -274,8 +282,17 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#ifdef CONFIG_OF
+#ifdef CONFIG_USE_BUILTIN_DTB
+ unflatten_and_copy_device_tree();
+#else
+ memblock_reserve(__pa(dt_virt), fdt_totalsize(dt_virt));
+ unflatten_device_tree();
+#endif
+#endif
enable_mmu();
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -304,6 +321,9 @@ void __init setup_arch(char **cmdline_p)
bss_resource.start = virt_to_phys(__bss_start);
bss_resource.end = virt_to_phys(__bss_stop)-1;
+#endif
+
+#ifndef CHOSEN_BOOTARGS
#ifdef CONFIG_CMDLINE_OVERWRITE
strscpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
#else
@@ -312,11 +332,13 @@ void __init setup_arch(char **cmdline_p)
strlcat(command_line, " ", sizeof(command_line));
strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
#endif
-#endif
-
+#endif /* CONFIG_CMDLINE_OVERWRITE */
/* Save unparsed command line copy for /proc/cmdline */
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
+#else
+ *cmdline_p = boot_command_line;
+#endif
parse_early_param();
@@ -327,14 +349,6 @@ void __init setup_arch(char **cmdline_p)
/* Let earlyprintk output early console messages */
sh_early_platform_driver_probe("earlyprintk", 1, 1);
-#ifdef CONFIG_OF_EARLY_FLATTREE
-#ifdef CONFIG_USE_BUILTIN_DTB
- unflatten_and_copy_device_tree();
-#else
- unflatten_device_tree();
-#endif
-#endif
-
paging_init();
/* Perform the machine specific initialisation */
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 05/35] arch/sh/kernel/setup.c: Update DT support.
2023-10-14 14:53 ` [RFC PATCH v3 05/35] arch/sh/kernel/setup.c: Update DT support Yoshinori Sato
@ 2023-10-19 10:01 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 10:01 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Fix fdt initialize.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> ---
> arch/sh/kernel/setup.c | 36 +++++++++++++++++++++++++-----------
> 1 file changed, 25 insertions(+), 11 deletions(-)
>
> diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
> index b3da2757faaf..8fdbb9836134 100644
> --- a/arch/sh/kernel/setup.c
> +++ b/arch/sh/kernel/setup.c
> @@ -31,6 +31,7 @@
> #include <linux/memblock.h>
> #include <linux/of.h>
> #include <linux/of_fdt.h>
> +#include <linux/libfdt.h>
> #include <linux/uaccess.h>
> #include <uapi/linux/mount.h>
> #include <asm/io.h>
> @@ -79,7 +80,13 @@ extern int root_mountflags;
> #define RAMDISK_PROMPT_FLAG 0x8000
> #define RAMDISK_LOAD_FLAG 0x4000
>
> +#if defined(CONFIG_OF) || !defined(USE_BUILTIN_DTB)
This breaks non-DT. I assume you meant "&&" instead?
Also, USE_BUILTIN_DTB lacks the CONFIG_-prefix.
However, I'm not sure this works as expected, as I have CONFIG_USE_BUILTIN_DTB=y
on qemu/r2d, but the kernel command line passed to qemu is not used
by Linux?
> +#define CHOSEN_BOOTARGS
> +#endif
> +
> +#ifndef CHOSEN_BOOTARGS
> static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, };
> +#endif
>
> static struct resource code_resource = {
> .name = "Kernel code",
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (4 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 05/35] arch/sh/kernel/setup.c: Update DT support Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 18:37 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 07/35] arch/sh/kernel/time.c: support COMMON_CLK Yoshinori Sato
` (29 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boards/of-generic.c | 28 ++++------------------------
1 file changed, 4 insertions(+), 24 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index f7f3e618e85b..f1ca5a914c11 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -8,6 +8,7 @@
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <asm/machvec.h>
@@ -98,16 +99,7 @@ static void sh_of_smp_probe(void)
#endif
-static void noop(void)
-{
-}
-
-static int noopi(void)
-{
- return 0;
-}
-
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
@@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)
irqchip_init();
}
-static int __init sh_of_clk_init(void)
-{
-#ifdef CONFIG_COMMON_CLK
- /* Disabled pending move to COMMON_CLK framework. */
- pr_info("SH generic board support: scanning for clk providers\n");
- of_clk_init(NULL);
-#endif
- return 0;
-}
-
static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_setup = sh_of_setup,
.mv_name = "devicetree", /* replaced by DT root's model */
.mv_irq_demux = sh_of_irq_demux,
.mv_init_irq = sh_of_init_irq,
- .mv_clk_init = sh_of_clk_init,
- .mv_mode_pins = noopi,
- .mv_mem_init = noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mode_pins = generic_mode_pins,
+ .mv_mem_init = sh_of_mem_init,
};
struct sh_clk_ops;
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup.
2023-10-14 14:53 ` [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup Yoshinori Sato
@ 2023-10-18 18:37 ` Geert Uytterhoeven
2023-10-26 3:40 ` Yoshinori Sato
0 siblings, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 18:37 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/arch/sh/boards/of-generic.c
> +++ b/arch/sh/boards/of-generic.c
> @@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)
> irqchip_init();
> }
>
> -static int __init sh_of_clk_init(void)
> -{
> -#ifdef CONFIG_COMMON_CLK
> - /* Disabled pending move to COMMON_CLK framework. */
> - pr_info("SH generic board support: scanning for clk providers\n");
> - of_clk_init(NULL);
> -#endif
> - return 0;
> -}
> -
Removing this breaks J2 for sure? I guess this should be merged with
"[RFC PATCH v3 07/35] arch/sh/kernel/time.c: support COMMON_CLK."
to avoid a bisection regression?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup.
2023-10-18 18:37 ` Geert Uytterhoeven
@ 2023-10-26 3:40 ` Yoshinori Sato
2023-10-26 7:20 ` Geert Uytterhoeven
0 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-26 3:40 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz
On Thu, 19 Oct 2023 03:37:57 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> Thanks for your patch!
>
> > --- a/arch/sh/boards/of-generic.c
> > +++ b/arch/sh/boards/of-generic.c
> > @@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)
> > irqchip_init();
> > }
> >
> > -static int __init sh_of_clk_init(void)
> > -{
> > -#ifdef CONFIG_COMMON_CLK
> > - /* Disabled pending move to COMMON_CLK framework. */
> > - pr_info("SH generic board support: scanning for clk providers\n");
> > - of_clk_init(NULL);
> > -#endif
> > - return 0;
> > -}
> > -
>
> Removing this breaks J2 for sure? I guess this should be merged with
> "[RFC PATCH v3 07/35] arch/sh/kernel/time.c: support COMMON_CLK."
> to avoid a bisection regression?
>
J2 timer (jcore-pit) used TIMER_OF_DECLARE
This is the correct OF implementation, so it is initialized with timer_probe.
I would like to eliminate as many SH-specific methods as possible.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup.
2023-10-26 3:40 ` Yoshinori Sato
@ 2023-10-26 7:20 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-26 7:20 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Thu, Oct 26, 2023 at 5:40 AM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> On Thu, 19 Oct 2023 03:37:57 +0900,
> Geert Uytterhoeven wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >
> > Thanks for your patch!
> >
> > > --- a/arch/sh/boards/of-generic.c
> > > +++ b/arch/sh/boards/of-generic.c
> > > @@ -140,25 +132,13 @@ static void __init sh_of_init_irq(void)
> > > irqchip_init();
> > > }
> > >
> > > -static int __init sh_of_clk_init(void)
> > > -{
> > > -#ifdef CONFIG_COMMON_CLK
> > > - /* Disabled pending move to COMMON_CLK framework. */
> > > - pr_info("SH generic board support: scanning for clk providers\n");
> > > - of_clk_init(NULL);
> > > -#endif
> > > - return 0;
> > > -}
> > > -
> >
> > Removing this breaks J2 for sure? I guess this should be merged with
> > "[RFC PATCH v3 07/35] arch/sh/kernel/time.c: support COMMON_CLK."
> > to avoid a bisection regression?
>
> J2 timer (jcore-pit) used TIMER_OF_DECLARE
> This is the correct OF implementation, so it is initialized with timer_probe.
> I would like to eliminate as many SH-specific methods as possible.
Oh right, I missed that (a) there still is a call to timer_init()
in SH's time_init(), and (b) more importantly, J-core does not have
any other clock drivers, so it does not need of_clk_init().
Still, I think it would make sense to merge the two patches.
And the call to timer_init() should be removed from the non-DT
variant of time_init(), as timer_init() handles only DT and ACPI.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 07/35] arch/sh/kernel/time.c: support COMMON_CLK.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (5 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 06/35] arch/sh/boards/of-generic.c: some cleanup Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 08/35] arch/sh/include/asm: Disable SH specific PCI define in OF enabled Yoshinori Sato
` (28 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Initialize the clock and timer using the COMMON_CLK procedure.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/kernel/time.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 821a09cbd605..ce5b7c2f8628 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -19,7 +19,9 @@
#include <asm/clock.h>
#include <asm/rtc.h>
#include <asm/platform_early.h>
+#include <linux/of_clk.h>
+#ifndef CONFIG_SH_DEVICE_TREE
static void __init sh_late_time_init(void)
{
/*
@@ -43,3 +45,13 @@ void __init time_init(void)
late_time_init = sh_late_time_init;
}
+#else
+/* CONFIG_SH_DEVICE_TREE */
+void __init time_init(void)
+{
+ pr_info("SH generic board support: scanning for clk providers\n");
+
+ of_clk_init(NULL);
+ timer_probe();
+}
+#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 08/35] arch/sh/include/asm: Disable SH specific PCI define in OF enabled.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (6 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 07/35] arch/sh/kernel/time.c: support COMMON_CLK Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 09/35] drivers/pci/controller: SH7751 PCI Host bridge driver Yoshinori Sato
` (27 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
For OF support, the PCI driver will be migrated to a common one.
Switch PCI-related headers to the common version.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/include/asm/io.h | 14 ++++++++++++--
arch/sh/include/asm/pci.h | 4 ++++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index f2f38e9d489a..3519eb6a9715 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -311,10 +311,20 @@ unsigned long long poke_real_address_q(unsigned long long addr,
#define xlate_dev_mem_ptr(p) __va(p)
#define unxlate_dev_mem_ptr(p, v) do { } while (0)
-#include <asm-generic/io.h>
-
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+
+#ifdef __KERNEL__
+#define PCI_IOBASE 0xfe240000UL
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET PCI_IOBASE
+#define PIO_MASK 0x3ffffUL
+#define PIO_RESERVED 0x40000UL
+#endif /* __KERNEL__ */
+
+#include <asm-generic/io.h>
+
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 54c30126ea17..92b3bd604319 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -2,6 +2,7 @@
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H
+#ifndef CONFIG_SH_DEVICE_TREE
/* Can be used to override the logic in pci_scan_bus for skipping
already-configured bus numbers - to be used for buggy BIOSes
or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
return hose->need_domain_info;
}
+#else /* CONFIG_SH_DEVICE_TREE */
+#include <asm-generic/pci.h>
+#endif
#endif /* __ASM_SH_PCI_H */
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 09/35] drivers/pci/controller: SH7751 PCI Host bridge driver.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (7 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 08/35] arch/sh/include/asm: Disable SH specific PCI define in OF enabled Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-16 17:27 ` Bjorn Helgaas
2023-10-14 14:53 ` [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file Yoshinori Sato
` (26 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, lpieralisi, kw, robh, linux-pci
pci-sh7751.h move from "arch/sh/drivers/pci/pci-sh7751.h"
pci-sh7751.c convert from "arch/sh/drivers/pci/pci-sh7751.c"
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pci-sh7751.c | 285 ++++++++++++++++++++++++++++
drivers/pci/controller/pci-sh7751.h | 267 ++++++++++++++++++++++++++
4 files changed, 562 insertions(+)
create mode 100644 drivers/pci/controller/pci-sh7751.c
create mode 100644 drivers/pci/controller/pci-sh7751.h
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index c0c3f2824990..037ff44bd1e8 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -342,6 +342,15 @@ config PCIE_XILINX_CPM
Say 'Y' here if you want kernel support for the
Xilinx Versal CPM host bridge.
+config PCI_SH7751
+ bool "Renesas SH7751 PCI controller"
+ depends on OF
+ depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
+ select PCI_HOST_COMMON
+ help
+ Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
+ Host Bridge driver.
+
source "drivers/pci/controller/cadence/Kconfig"
source "drivers/pci/controller/dwc/Kconfig"
source "drivers/pci/controller/mobiveil/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 37c8663de7fe..ce96cfe9f1f2 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
+obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c
new file mode 100644
index 000000000000..4aecd0224eb1
--- /dev/null
+++ b/drivers/pci/controller/pci-sh7751.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 PCI driver
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci-ecam.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <asm-generic/pci.h>
+#include <asm/addrspace.h>
+#include "pci-sh7751.h"
+
+#define pcic_writel(val, base, reg) __raw_writel(val, base + (reg))
+#define pcic_readl(base, reg) __raw_readl(base + (reg))
+
+/*
+ * PCIC fixups
+ */
+
+static inline void pci_fixup_write_regs(struct device_node *np,
+ const char *prop,
+ void __iomem *pcic, int reg,
+ int nr_regs)
+{
+ int i;
+ u32 val;
+
+ for (i = 0; i < nr_regs; i++) {
+ if (of_property_read_u32_index(np, prop, i, &val))
+ pcic_writel(val, pcic, reg + i * 4);
+ }
+}
+
+#define SH7751_NUM_CONFIG 18
+static void pcic_fixups(struct device_node *np,
+ void __iomem *pcic, void __iomem *bcr)
+{
+ unsigned long bcr1, mcr;
+ u32 val;
+ int i, r;
+ u32 pci_config[SH7751_NUM_CONFIG * 2];
+
+ const struct {
+ const char *name;
+ int reg;
+ int nr;
+ } reg_prop[] = {
+ /*
+ * The bus timing uses the bootloader settings,
+ * so do not change them here.
+ */
+ { "renesas,intm", SH4_PCIINTM, 1, },
+ { "renesas,aintm", SH4_PCIAINTM, 1, },
+ { "renesas,lsr", SH4_PCILSR0, 2, },
+ { "renesas,lar", SH4_PCILAR0, 2, },
+ { "renesas,dmabt", SH4_PCIDMABT, 1, },
+ { "renesas,pintm", SH4_PCIPINTM, 1, },
+ };
+
+ if (of_property_read_u32(np, "sh7751-pci,bcr1", &val)) {
+ bcr1 = ioread32(bcr + SH7751_BCR1);
+ bcr1 |= val;
+ pcic_writel(bcr1, pcic, SH4_PCIBCR1);
+ }
+ if (of_property_read_u32(np, "renesas,clkr", &val)) {
+ val |= 0xa5 << 24;
+ pcic_writel(val, pcic, SH4_PCIBCR1);
+ }
+ for (i = 0; i < ARRAY_SIZE(reg_prop); i++)
+ pci_fixup_write_regs(np, reg_prop[i].name, pcic,
+ reg_prop[i].reg, reg_prop[i].nr);
+
+ memset(pci_config, 0, sizeof(pci_config));
+ if (of_property_read_u32_array(np, "renesas,config",
+ pci_config, SH7751_NUM_CONFIG) == 0) {
+ for (i = 0; i < SH7751_NUM_CONFIG; i++) {
+ r = pci_config[i * 2];
+ /* CONFIG0 is read-only, so make it a sentinel. */
+ if (r == 0)
+ break;
+ pcic_writel(pci_config[i * 2 + 1], pcic,
+ SH7751_PCICONF0 + r * 4);
+ }
+ }
+
+ if (of_property_read_u32(np, "sh7751-pci,mcrmask", &val)) {
+ mcr = ioread32(bcr + SH7751_MCR);
+ mcr &= ~val;
+ pcic_writel(mcr, pcic, SH4_PCIMCR);
+ }
+}
+
+/*
+ * Direct access to PCI hardware...
+ */
+#define CONFIG_CMD(bus, devfn, where) \
+ (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
+
+/*
+ * We need to avoid collisions with `mirrored' VGA ports
+ * and other strange ISA hardware, so we always want the
+ * addresses to be allocated in the 0x000-0x0ff region
+ * modulo 0x400.
+ */
+#define IO_REGION_BASE 0x1000
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+ resource_size_t size, resource_size_t align)
+{
+ resource_size_t start = res->start;
+
+ if (res->flags & IORESOURCE_IO) {
+ if (start < PCIBIOS_MIN_IO + IO_REGION_BASE)
+ start = PCIBIOS_MIN_IO + IO_REGION_BASE;
+
+ /*
+ * Put everything into 0x00-0xff region modulo 0x400.
+ */
+ if (start & 0x300)
+ start = (start + 0x3ff) & ~0x3ff;
+ }
+
+ return start;
+}
+
+static int area_sdram_check(struct device *dev, void __iomem *pcic,
+ void __iomem *bcr, unsigned int area)
+{
+ unsigned long word;
+
+ word = __raw_readl(bcr + SH7751_BCR1);
+ /* check BCR for SDRAM in area */
+ if (((word >> area) & 1) == 0) {
+ dev_info(dev, "PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, pcic, SH4_PCIBCR1);
+
+ word = __raw_readw(bcr + SH7751_BCR2);
+ /* check BCR2 for 32bit SDRAM interface*/
+ if (((word >> (area << 1)) & 0x3) != 0x3) {
+ dev_info(dev, "PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, pcic, SH4_PCIBCR2);
+
+ return 1;
+}
+
+static void set_pci_window(void __iomem *pcic, int no, struct resource *res)
+{
+ u32 word;
+
+ word = res->end - res->start - 1;
+ pcic_writel(word, pcic, SH4_PCILSR0 + no * 4);
+ word = P2SEGADDR(res->start);
+ pcic_writel(word, pcic, SH4_PCILAR0 + no * 4);
+ pcic_writel(word, pcic, SH7751_PCICONF5 + no * 4);
+}
+
+static int sh7751_pci_probe(struct platform_device *pdev)
+{
+ struct resource *res, *w0res;
+ u32 id;
+ u32 reg, word;
+ void __iomem *pcic;
+ void __iomem *bcr;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pcic = (void __iomem *)res->start;
+ if (IS_ERR(pcic))
+ return PTR_ERR(pcic);
+
+ w0res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (IS_ERR(w0res))
+ return PTR_ERR(w0res);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ bcr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(bcr))
+ return PTR_ERR(bcr);
+
+ /* check for SH7751/SH7751R hardware */
+ id = pcic_readl(pcic, SH7751_PCICONF0);
+ if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
+ id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
+ dev_warn(&pdev->dev, "PCI: This is not an SH7751(R)\n");
+ return -ENODEV;
+ }
+ dev_info(&pdev->dev, "PCI core found at %pR\n", pcic);
+
+ /* Set the BCR's to enable PCI access */
+ reg = __raw_readl(bcr);
+ reg |= 0x80000;
+ __raw_writel(reg, bcr);
+
+ /* Turn the clocks back on (not done in reset)*/
+ pcic_writel(0, pcic, SH4_PCICLKR);
+ /* Clear Powerdown IRQ's (not done in reset) */
+ word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
+ pcic_writel(word, pcic, SH4_PCIPINT);
+
+ /* set the command/status bits to:
+ * Wait Cycle Control + Parity Enable + Bus Master +
+ * Mem space enable
+ */
+ word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
+ SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
+ pcic_writel(word, pcic, SH7751_PCICONF1);
+
+ /* define this host as the host bridge */
+ word = PCI_BASE_CLASS_BRIDGE << 24;
+ pcic_writel(word, pcic, SH7751_PCICONF2);
+
+ /* Set IO and Mem windows to local address
+ * Make PCI and local address the same for easy 1 to 1 mapping
+ */
+ set_pci_window(pcic, 0, w0res); /* memory */
+
+ /* check BCR for SDRAM in specified area */
+ area_sdram_check(&pdev->dev, pcic, bcr, (w0res->start >> 27) & 0x07);
+
+ /* configure the wait control registers */
+ word = __raw_readl(bcr + SH7751_WCR1);
+ pcic_writel(word, pcic, SH4_PCIWCR1);
+ word = __raw_readl(bcr + SH7751_WCR2);
+ pcic_writel(word, pcic, SH4_PCIWCR2);
+ word = __raw_readl(bcr + SH7751_WCR3);
+ pcic_writel(word, pcic, SH4_PCIWCR3);
+ word = __raw_readl(bcr + SH7751_MCR);
+ pcic_writel(word, pcic, SH4_PCIMCR);
+
+ /* Override register setting */
+ pcic_fixups(pdev->dev.of_node, pcic, bcr);
+
+ /* SH7751 init done, set central function init complete */
+ /* use round robin mode to stop a device starving/overrunning */
+ word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
+ pcic_writel(word, pcic, SH4_PCICR);
+
+ return pci_host_common_probe(pdev);
+}
+
+static void __iomem *sh4_pci_map_bus(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pcic = (void __iomem *)cfg->res.start;
+
+ pcic_writel(CONFIG_CMD(bus, devfn, where), pcic, SH4_PCIPAR);
+ return pcic + SH4_PCIPDR;
+}
+
+static const struct pci_ecam_ops pci_sh7751_bus_ops = {
+ .pci_ops = {
+ .map_bus = sh4_pci_map_bus,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+ }
+};
+
+static const struct of_device_id sh7751_pci_of_match[] = {
+ { .compatible = "renesas,pci-sh7751",
+ .data = &pci_sh7751_bus_ops },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sh7751_pci_of_match);
+
+static struct platform_driver sh7751_pci_driver = {
+ .driver = {
+ .name = "pci-sh7751",
+ .of_match_table = sh7751_pci_of_match,
+ },
+ .probe = sh7751_pci_probe,
+};
+module_platform_driver(sh7751_pci_driver);
+
+MODULE_DESCRIPTION("SH7751 PCI driver");
diff --git a/drivers/pci/controller/pci-sh7751.h b/drivers/pci/controller/pci-sh7751.h
new file mode 100644
index 000000000000..b2d74d57addb
--- /dev/null
+++ b/drivers/pci/controller/pci-sh7751.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Low-Level PCI Support for SH7751 targets
+ *
+ * Dustin McIntire (dustin@sensoria.com) (c) 2001
+ * Paul Mundt (lethal@linux-sh.org) (c) 2003
+ *
+ */
+
+#ifndef _PCI_SH7751_H_
+#define _PCI_SH7751_H_
+
+#define SH4_PCICR 0x100 /* PCI Control Register */
+ #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
+ #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
+ #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */
+ #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */
+ #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
+ #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
+ #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */
+ #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */
+ #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */
+ #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
+ #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
+#define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
+#define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
+#define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
+#define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
+#define SH4_PCIINT 0x114 /* PCI Interrupt Register */
+ #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */
+ #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */
+ #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */
+ #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
+ #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */
+ #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */
+ #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
+ #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */
+ #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
+ #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
+ #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
+ #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
+#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
+ #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
+ #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
+ #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
+ #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
+ #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
+ #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
+ #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
+ #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
+ #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
+ #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
+ #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
+#define SH4_PCIALR 0x11C /* Error Address Register */
+#define SH4_PCICLR 0x120 /* Error Command/Data */
+ #define SH4_PCICLR_MPIO 0x80000000
+ #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
+ #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
+ #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
+ #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
+ #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
+ #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
+#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
+ #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
+ #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
+ #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
+ #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
+ #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
+ #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
+ #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
+#define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
+#define SH4_PCIBMLR 0x138 /* Error Bus Master Register */
+ #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
+ #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
+ #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
+ #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
+ #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
+#define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
+ #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
+#define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
+#define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */
+#define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
+#define SH4_PCIDCR0 0x18C /* DMA0 Control Register */
+ #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
+ #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
+ #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
+ #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
+ #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */
+ #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
+ #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
+ #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
+ #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
+ #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */
+#define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
+#define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */
+#define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
+#define SH4_PCIDCR1 0x19C /* DMA1 Control Register */
+#define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
+#define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */
+#define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
+#define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
+#define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
+#define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */
+#define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
+#define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
+#define SH4_PCIPAR 0x1C0 /* PIO Address Register */
+ #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
+ #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
+ #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
+ #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */
+#define SH4_PCIMBR 0x1C4 /* Memory Base Address */
+ #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
+ #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
+#define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
+ #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
+ #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
+#define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
+ #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
+ #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
+#define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
+#define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */
+ #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
+ #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
+/* For definitions of BCR, MCR see ... */
+#define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
+ #define SH4_PCIMBR0 SH4_PCIBCR1
+#define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
+ #define SH4_PCIMBMR0 SH4_PCIBCR2
+#define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */
+#define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */
+#define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */
+ #define SH4_PCIMBR2 SH4_PCIWCR3
+#define SH4_PCIMCR 0x1F4 /* Memory Control Register */
+#define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
+#define SH4_PCIPCTR 0x200 /* Port Control Register */
+ #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
+ #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
+ #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
+ #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
+ #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
+ #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
+ #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
+ #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
+ #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
+#define SH4_PCIPDTR 0x204 /* Port Data Register */
+ #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
+ #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
+ #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
+ #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
+ #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
+ #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
+#define SH4_PCIPDR 0x220 /* Port IO Data Register */
+
+/* Platform Specific Values */
+#define SH7751_VENDOR_ID 0x1054
+#define SH7751_DEVICE_ID 0x3505
+#define SH7751R_DEVICE_ID 0x350e
+
+/* SH7751 Specific Values */
+#define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
+#define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
+#define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
+#define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
+#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
+
+#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
+
+#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
+ #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
+ #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */
+#define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
+ #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */
+ #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */
+ #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */
+ #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */
+ #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */
+ #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */
+ #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */
+ #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */
+ #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */
+ #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */
+ #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */
+ #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */
+ #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */
+ #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */
+ #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */
+ #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */
+ #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
+ #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */
+ #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */
+ #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
+ #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */
+#define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
+ #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
+ #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
+ #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
+ #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
+#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
+ #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
+ #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
+ #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
+ #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */
+ #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */
+ #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */
+ #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */
+#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
+ #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
+ #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
+ #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
+ #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
+/* PCICONF7 - PCICONF10 are undefined */
+#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
+ #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
+ #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */
+/* PCICONF12 is undefined */
+#define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
+ #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */
+/* PCICONF14 is undefined */
+#define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
+ #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */
+#define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
+ #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */
+ #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */
+ #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */
+ #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */
+ #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */
+ #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */
+ #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */
+ #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */
+#define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
+ #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */
+ #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */
+ #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */
+ #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */
+ #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */
+ #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */
+/* SH7751 Internal PCI Registers */
+
+/* Memory Control Registers */
+#define SH7751_BCR1 0x0000 /* Memory BCR1 Register */
+#define SH7751_BCR2 0x0004 /* Memory BCR2 Register */
+#define SH7751_BCR3 0x0050 /* Memory BCR3 Register */
+#define SH7751_WCR1 0x0008 /* Wait Control 1 Register */
+#define SH7751_WCR2 0x000C /* Wait Control 2 Register */
+#define SH7751_WCR3 0x0010 /* Wait Control 3 Register */
+#define SH7751_MCR 0x0014 /* Memory Control Register */
+
+/* General Memory Config Addresses */
+#define SH7751_CS0_BASE_ADDR 0x0
+#define SH7751_MEM_REGION_SIZE 0x04000000
+#define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+
+#endif /* _PCI_SH7751_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 09/35] drivers/pci/controller: SH7751 PCI Host bridge driver.
2023-10-14 14:53 ` [RFC PATCH v3 09/35] drivers/pci/controller: SH7751 PCI Host bridge driver Yoshinori Sato
@ 2023-10-16 17:27 ` Bjorn Helgaas
2023-10-16 19:52 ` Bjorn Helgaas
0 siblings, 1 reply; 88+ messages in thread
From: Bjorn Helgaas @ 2023-10-16 17:27 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, lpieralisi, kw, robh, linux-pci
"git am" complained about a couple whitespace errors elsewhere in this
series:
Applying: arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function.
.git/rebase-apply/patch:25: trailing whitespace.
Applying: drivers/irqchip: SH7751 IRL external encoder with enable gate.
.git/rebase-apply/patch:33: new blank line at EOF.
On Sat, Oct 14, 2023 at 11:53:44PM +0900, Yoshinori Sato wrote:
> pci-sh7751.h move from "arch/sh/drivers/pci/pci-sh7751.h"
> pci-sh7751.c convert from "arch/sh/drivers/pci/pci-sh7751.c"
Note the subject line conventions in drivers/pci (use "git log
--oneline" to see them): use something like this:
PCI: sh7751: Add SH7751 PCI host bridge driver
with no period at the end.
arch/sh/drivers/pci/pci-sh7751.h and arch/sh/drivers/pci/pci-sh7751.c
still exist after applying this series. Better to have a single patch
that moves the content from arch/sh/drivers/pci/ to
drivers/pci/controller/.
Neither file looks like a simple move; there's a lot of reorganization
going on at the same time. It's really difficult to review a patch
like that because we can't compare the content from before and after.
If you make a patch that does the cleanup/reorganization, and a
separate patch that is just a simple move, and you use "git mv" for
the move, git should notice that this is just a rename, and that diff
will be tiny.
One of the reorganization patches should be to incorporate the
pci-sh7751.h content directly into pci-sh7751.c. Since it's only used
in pci-sh7751.c, there's really no advantage to having it in a
separate file.
Bjorn
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> drivers/pci/controller/Kconfig | 9 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pci-sh7751.c | 285 ++++++++++++++++++++++++++++
> drivers/pci/controller/pci-sh7751.h | 267 ++++++++++++++++++++++++++
> 4 files changed, 562 insertions(+)
> create mode 100644 drivers/pci/controller/pci-sh7751.c
> create mode 100644 drivers/pci/controller/pci-sh7751.h
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index c0c3f2824990..037ff44bd1e8 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -342,6 +342,15 @@ config PCIE_XILINX_CPM
> Say 'Y' here if you want kernel support for the
> Xilinx Versal CPM host bridge.
>
> +config PCI_SH7751
> + bool "Renesas SH7751 PCI controller"
> + depends on OF
> + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
> + select PCI_HOST_COMMON
> + help
> + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
> + Host Bridge driver.
Move this so the menu entries stay sorted by vendor name.
Bjorn
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [RFC PATCH v3 09/35] drivers/pci/controller: SH7751 PCI Host bridge driver.
2023-10-16 17:27 ` Bjorn Helgaas
@ 2023-10-16 19:52 ` Bjorn Helgaas
0 siblings, 0 replies; 88+ messages in thread
From: Bjorn Helgaas @ 2023-10-16 19:52 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, lpieralisi, kw, robh, linux-pci
On Mon, Oct 16, 2023 at 12:27:42PM -0500, Bjorn Helgaas wrote:
> "git am" complained about a couple whitespace errors elsewhere in this
> series:
>
> Applying: arch/sh/boot/compressed/head_32.S: passing FDT address to initialize function.
> .git/rebase-apply/patch:25: trailing whitespace.
> Applying: drivers/irqchip: SH7751 IRL external encoder with enable gate.
> .git/rebase-apply/patch:33: new blank line at EOF.
BTW, I mentioned all these things and more a month or so ago:
https://lore.kernel.org/r/20230918191602.GA201859@bhelgaas
https://lore.kernel.org/r/20230918193337.GA203483@bhelgaas
https://lore.kernel.org/r/20230918193036.GA203163@bhelgaas
I *thought* this seemed familiar ;)
Bjorn
> On Sat, Oct 14, 2023 at 11:53:44PM +0900, Yoshinori Sato wrote:
> > pci-sh7751.h move from "arch/sh/drivers/pci/pci-sh7751.h"
> > pci-sh7751.c convert from "arch/sh/drivers/pci/pci-sh7751.c"
>
> Note the subject line conventions in drivers/pci (use "git log
> --oneline" to see them): use something like this:
>
> PCI: sh7751: Add SH7751 PCI host bridge driver
>
> with no period at the end.
>
> arch/sh/drivers/pci/pci-sh7751.h and arch/sh/drivers/pci/pci-sh7751.c
> still exist after applying this series. Better to have a single patch
> that moves the content from arch/sh/drivers/pci/ to
> drivers/pci/controller/.
>
> Neither file looks like a simple move; there's a lot of reorganization
> going on at the same time. It's really difficult to review a patch
> like that because we can't compare the content from before and after.
>
> If you make a patch that does the cleanup/reorganization, and a
> separate patch that is just a simple move, and you use "git mv" for
> the move, git should notice that this is just a rename, and that diff
> will be tiny.
>
> One of the reorganization patches should be to incorporate the
> pci-sh7751.h content directly into pci-sh7751.c. Since it's only used
> in pci-sh7751.c, there's really no advantage to having it in a
> separate file.
>
> Bjorn
>
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > ---
> > drivers/pci/controller/Kconfig | 9 +
> > drivers/pci/controller/Makefile | 1 +
> > drivers/pci/controller/pci-sh7751.c | 285 ++++++++++++++++++++++++++++
> > drivers/pci/controller/pci-sh7751.h | 267 ++++++++++++++++++++++++++
> > 4 files changed, 562 insertions(+)
> > create mode 100644 drivers/pci/controller/pci-sh7751.c
> > create mode 100644 drivers/pci/controller/pci-sh7751.h
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index c0c3f2824990..037ff44bd1e8 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -342,6 +342,15 @@ config PCIE_XILINX_CPM
> > Say 'Y' here if you want kernel support for the
> > Xilinx Versal CPM host bridge.
> >
> > +config PCI_SH7751
> > + bool "Renesas SH7751 PCI controller"
> > + depends on OF
> > + depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
> > + select PCI_HOST_COMMON
> > + help
> > + Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
> > + Host Bridge driver.
>
> Move this so the menu entries stay sorted by vendor name.
>
> Bjorn
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (8 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 09/35] drivers/pci/controller: SH7751 PCI Host bridge driver Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-16 5:28 ` Krzysztof Kozlowski
2023-10-16 11:55 ` Krzysztof Kozlowski
2023-10-14 14:53 ` [RFC PATCH v3 11/35] include/dt-bindings/clock/sh7750.h: cpg-sh7750 binding header Yoshinori Sato
` (25 subsequent siblings)
35 siblings, 2 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, lpieralisi, kw, robh,
krzysztof.kozlowski+dt, conor+dt
binding document for renesas,pci-sh7751.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../bindings/pci/renesas,pci-sh7751.yaml | 123 ++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml
new file mode 100644
index 000000000000..a6081c3de51d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,pci-sh7751.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 PCI Host controller
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,pci-sh7751
+
+ reg:
+ minItems: 3
+
+ "#interrupt-cells":
+ const: 1
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ ranges:
+ description: |
+ The PCI bus memory area and I/O area.
+
+ interrupt-controller: true
+
+ renesas,bcr1:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCIBCR1 value. This value makes add the value of BSC's BCR1.
+
+ renesas,mcrmask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCIMCR value. This value makes clear bit in the value of BSC's MCR.
+
+ renesas,intm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCIINTM value.
+
+ renesas,aintm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCIIANTM value.
+
+ renesas,lsr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCILSR0 and PCILSR1 values.
+ First word is PCILSR0, Second word is PCILSR1.
+
+ renesas,lar:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCILSA0 and PCILAR1 values.
+ First word is PCILAR0, Second word is PCILAR1.
+
+ renesas,dmabt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCIDMABT value.
+
+ renesas,pintm:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ SH7751 PCIC PCIPINTM value.
+
+ renesas,config:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ SH7751 PCIC PCICONFIG values array. Register Number and value pair list.
+
+required:
+ - compatible
+ - reg
+ - "#interrupt-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - interrupt-map
+ - interrupt-map-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pci@fe200000 {
+ compatible = "renesas,pci-sh7751";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ interrupt-map = <0x0000 0 0 1 &julianintc 5>,
+ <0x0000 0 0 2 &julianintc 6>,
+ <0x0000 0 0 3 &julianintc 7>,
+ <0x0000 0 0 4 &julianintc 8>,
+ <0x0800 0 0 1 &julianintc 6>,
+ <0x0800 0 0 2 &julianintc 7>,
+ <0x0800 0 0 3 &julianintc 8>,
+ <0x0800 0 0 4 &julianintc 5>,
+ <0x1000 0 0 1 &julianintc 7>,
+ <0x1000 0 0 2 &julianintc 8>,
+ <0x1000 0 0 3 &julianintc 5>,
+ <0x1000 0 0 4 &julianintc 6>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file.
2023-10-14 14:53 ` [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file Yoshinori Sato
@ 2023-10-16 5:28 ` Krzysztof Kozlowski
2023-10-16 11:55 ` Krzysztof Kozlowski
1 sibling, 0 replies; 88+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-16 5:28 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh
Cc: glaubitz, lpieralisi, kw, robh, krzysztof.kozlowski+dt, conor+dt
On 14/10/2023 16:53, Yoshinori Sato wrote:
> binding document for renesas,pci-sh7751.
It's still RFC, so I assume it is not ready for merging and it is not
meant to be reviewed. In case it is not correct - some people actually
expect RFC to be merged - trivial comments:
1. Please use subject prefixes matching the subsystem. You can get them
for example with `git log --oneline -- DIRECTORY_OR_FILE` on the
directory your patch is touching.
2. Drop final full stop from subject.
3. Missing commit msg
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> .../bindings/pci/renesas,pci-sh7751.yaml | 123 ++++++++++++++++++
> 1 file changed, 123 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml
If sh7751 is the name of SoC or device:
renesas,sh7751-pci.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml
> new file mode 100644
> index 000000000000..a6081c3de51d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/renesas,pci-sh7751.yaml
> @@ -0,0 +1,123 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/renesas,pci-sh7751.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 PCI Host controller
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> + compatible:
> + items:
You can drop items
> + - enum:
> + - renesas,pci-sh7751
renesas,sh7751-pci
> +
> + reg:
> + minItems: 3
maxItems instead
> +
> + "#interrupt-cells":
> + const: 1
> +
> + "#address-cells":
> + const: 3
> +
> + "#size-cells":
> + const: 2
> +
> + ranges:
> + description: |
> + The PCI bus memory area and I/O area.
Drop description, just ranges: true.
....
> +
> +examples:
> + - |
> + pci@fe200000 {
Use 4 spaces for example indentation.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file.
2023-10-14 14:53 ` [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file Yoshinori Sato
2023-10-16 5:28 ` Krzysztof Kozlowski
@ 2023-10-16 11:55 ` Krzysztof Kozlowski
1 sibling, 0 replies; 88+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-16 11:55 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh
Cc: glaubitz, lpieralisi, kw, robh, krzysztof.kozlowski+dt, conor+dt
On 14/10/2023 16:53, Yoshinori Sato wrote:
> binding document for renesas,pci-sh7751.
>
>
One more comment - this was not tested so is not ready for review.
Standard disclaimer:
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.
You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time, thus I will skip this patch entirely till you follow
the process allowing the patch to be tested.
Please kindly resend and include all necessary To/Cc entries.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 11/35] include/dt-bindings/clock/sh7750.h: cpg-sh7750 binding header.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (9 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 10/35] Documentation/devicetree/bindings/pci: renesas,pci-sh7751.yaml new file Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 13:49 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver Yoshinori Sato
` (24 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-clk
SH7750 CPG driver binding definition.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/dt-bindings/clock/sh7750.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 include/dt-bindings/clock/sh7750.h
diff --git a/include/dt-bindings/clock/sh7750.h b/include/dt-bindings/clock/sh7750.h
new file mode 100644
index 000000000000..10be4eb63bdb
--- /dev/null
+++ b/include/dt-bindings/clock/sh7750.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
+#define __DT_BINDINGS_CLOCK_SH7750_H__
+
+#define SH7750_CPG_PLLOUT 0
+
+#define SH7750_CPG_FCK 1
+#define SH7750_CPG_BCK 2
+#define SH7750_CPG_ICK 3
+
+#define SH7750_CPG_SCI_CLK 4
+#define SH7750_CPG_RTC_CLK 5
+#define SH7750_CPG_TMU012_CLK 6
+#define SH7750_CPG_SCIF_CLK 7
+#define SH7750_CPG_DMAC_CLK 8
+#define SH7750_CPG_UBC_CLK 9
+#define SH7750_CPG_SQ_CLK 10
+#define SH7750_CPG_INTC_CLK 11
+#define SH7750_CPG_TMU34_CLK 12
+#define SH7750_CPG_PCIC_CLK 13
+
+#endif
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 11/35] include/dt-bindings/clock/sh7750.h: cpg-sh7750 binding header.
2023-10-14 14:53 ` [RFC PATCH v3 11/35] include/dt-bindings/clock/sh7750.h: cpg-sh7750 binding header Yoshinori Sato
@ 2023-10-18 13:49 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 13:49 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-clk
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> SH7750 CPG driver binding definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/include/dt-bindings/clock/sh7750.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright 2023 Yoshinori Sato
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_SH7750_H__
> +#define __DT_BINDINGS_CLOCK_SH7750_H__
> +
> +#define SH7750_CPG_PLLOUT 0
> +
> +#define SH7750_CPG_FCK 1
> +#define SH7750_CPG_BCK 2
> +#define SH7750_CPG_ICK 3
> +
> +#define SH7750_CPG_SCI_CLK 4
> +#define SH7750_CPG_RTC_CLK 5
> +#define SH7750_CPG_TMU012_CLK 6
> +#define SH7750_CPG_SCIF_CLK 7
> +#define SH7750_CPG_DMAC_CLK 8
> +#define SH7750_CPG_UBC_CLK 9
> +#define SH7750_CPG_SQ_CLK 10
The above 7 clocks are not CPG core clocks, but part of the Power-Down
Modes block. The documentation calls them MSTPx (Module Stop).
So I'd go for SH7750_MSTP_SCI_CLK etc.
And perhaps drop the "_CLK" suffix?
> +#define SH7750_CPG_INTC_CLK 11
> +#define SH7750_CPG_TMU34_CLK 12
> +#define SH7750_CPG_PCIC_CLK 13
Similarly, but the documentation calls these CSTPx (Clock Stop).
So I'd go for SH7750_CSTP_INTC_CLK etc.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (10 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 11/35] include/dt-bindings/clock/sh7750.h: cpg-sh7750 binding header Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 13:02 ` Geert Uytterhoeven
2023-10-19 7:18 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document Yoshinori Sato
` (23 subsequent siblings)
35 siblings, 2 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, mturquette, sboyd, linux-clk
This driver supported SH7750/7751 PLL/Divider clock and module stop.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clk/renesas/Kconfig | 21 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/clk-sh7750.c | 787 +++++++++++++++++++++++++++++++
3 files changed, 807 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/renesas/clk-sh7750.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 37632a0659d8..c52c038ce715 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
config CLK_RENESAS
- bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
- default y if ARCH_RENESAS
+ bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS && SUPERH
+ default y if ARCH_RENESAS || SUPERH
select CLK_EMEV2 if ARCH_EMEV2
select CLK_RZA1 if ARCH_R7S72100
select CLK_R7S9210 if ARCH_R7S9210
@@ -39,6 +39,11 @@ config CLK_RENESAS
select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_R9A09G011 if ARCH_R9A09G011
select CLK_SH73A0 if ARCH_SH73A0
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750S
+ select CLK_SH7750 if CPU_SUBTYPE_SH7750R
+ select CLK_SH7750 if CPU_SUBTYPE_SH7751
+ select CLK_SH7750 if CPU_SUBTYPE_SH7751R
if CLK_RENESAS
@@ -188,6 +193,10 @@ config CLK_SH73A0
select CLK_RENESAS_CPG_MSTP
select CLK_RENESAS_DIV6
+config CLK_SH7750
+ bool "SH7750/7751 family clock support" if COMPILE_TEST
+ help
+ This is a driver for SH7750 / SH7751 CPG.
# Family
config CLK_RCAR_CPG_LIB
@@ -218,6 +227,14 @@ config CLK_RZG2L
bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
+config CLK_SH7750
+ bool "Renesas SH7750/7751 family clock support"
+ depends on CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+ CPU_SUBTYPE_SH7750R || \
+ CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
+ help
+ This is a driver for SH7750 / SH7751 CPG.
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index de907623fe3f..1be5f4caf1d2 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
+obj-$(CONFIG_CLK_SH7750) += clk-sh7750.o
# Family
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
diff --git a/drivers/clk/renesas/clk-sh7750.c b/drivers/clk/renesas/clk-sh7750.c
new file mode 100644
index 000000000000..94f836a2451b
--- /dev/null
+++ b/drivers/clk/renesas/clk-sh7750.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7750/51 CPG driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/sh7750.h>
+
+/* PCLK divide rate selector */
+static const struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { }
+};
+
+/* ICLK and BCLK divide rate selector */
+static const struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { }
+};
+
+struct cpg_priv {
+ struct clk_hw hw;
+ spinlock_t clklock;
+ void __iomem *frqcr;
+ void __iomem *clkstp00;
+ u32 mode;
+ bool have_div1;
+};
+
+enum clk_type {CLK_DIV, CLK_GATE};
+
+struct sh_clk_reg_arg {
+ enum clk_type type;
+ const char *name;
+ const char *parent;
+ void __iomem *reg;
+ const struct clk_ops *ops;
+ union {
+ struct {
+ /* divider */
+ u8 shift;
+ u8 width;
+ const struct clk_div_table *table;
+ } div;
+ struct {
+ /* gate */
+ u8 bit_idx;
+ u8 flags;
+ } gate;
+ };
+};
+
+enum {
+ FRQCR = 0,
+ STBCR = 4,
+ WTCNT = 8,
+ WTCSR = 12,
+ STBCR2 = 16,
+ CLKSTP00 = 0,
+ CLKSTPCLR00 = 8,
+};
+
+static struct cpg_priv *cpg_data;
+
+#define to_priv(_hw) container_of(_hw, struct cpg_priv, hw)
+
+#define div_mask(width) ((1U << (width)) - 1)
+
+static unsigned int _get_maxdiv(const struct clk_div_table *table,
+ u8 width)
+{
+ unsigned int maxdiv = 0, limit = div_mask(width);
+ const struct clk_div_table *clkt;
+
+ if (table) {
+ for (clkt = table; clkt->div; clkt++)
+ if (maxdiv < clkt->div && clkt->div <= limit)
+ maxdiv = clkt->div;
+
+ return maxdiv;
+ } else
+ return limit + 1;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ if (table) {
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+ return 0;
+ } else
+ return val + 1;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ if (table) {
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return clkt->val;
+ return 0;
+ } else
+ return div - 1;
+}
+
+static unsigned long sh_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int val;
+ unsigned int div;
+
+ val = __raw_readw(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ div = _get_div(divider->table, val);
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ if (!table)
+ return true;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return true;
+ return false;
+}
+
+static int _round_up_table(const struct clk_div_table *table, int div)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static inline int _div_round(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (table)
+ div = _round_up_table(table, div);
+
+ return div;
+}
+
+static inline bool _is_best_div(unsigned long rate, unsigned long now,
+ unsigned long best)
+{
+ return now <= rate && now > best;
+}
+
+static inline int _next_div(const struct clk_div_table *table, int div)
+{
+ div++;
+
+ if (table)
+ return _round_up_table(table, div);
+
+ return div;
+}
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ int bestdiv = 0;
+ unsigned int i;
+ unsigned long parent_rate, best = 0, now, maxdiv;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ maxdiv = _get_maxdiv(table, width);
+
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestdiv = _div_round(table, parent_rate, rate);
+ bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+ return bestdiv;
+ }
+
+ /*
+ * The maximum divider we can use without overflowing
+ * unsigned long in rate * i below
+ */
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (i = _next_div(table, 0); i <= maxdiv;
+ i = _next_div(table, i)) {
+ if (rate * i == parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+ rate * i);
+ now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
+ if (_is_best_div(rate, now, best)) {
+ bestdiv = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestdiv) {
+ bestdiv = _get_maxdiv(table, width);
+ *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
+ }
+
+ return bestdiv;
+}
+
+static int sh_clk_divider_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned long prate;
+ int div;
+
+ prate = req->best_parent_rate;
+
+ div = clk_divider_bestdiv(hw, req->rate, &prate,
+ divider->table, divider->width);
+ req->rate = DIV_ROUND_UP_ULL(prate, div);
+ req->best_parent_rate = prate;
+ return 0;
+}
+
+static int sh_divider_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ unsigned int div, value;
+
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (!_is_valid_div(table, div))
+ return -EINVAL;
+
+ value = _get_val(table, div);
+
+ return min(value, div_mask(width));
+}
+
+static int sh_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ int value;
+ unsigned long flags = 0;
+ u16 val;
+
+ value = sh_divider_get_val(rate, parent_rate, divider->table,
+ divider->width);
+ if (value < 0)
+ return value;
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ val = __raw_readw(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ val |= value << divider->shift;
+ __raw_writew(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static const struct clk_ops sh_clk_divider_ops = {
+ .recalc_rate = sh_clk_divider_recalc_rate,
+ .determine_rate = sh_clk_divider_determine_rate,
+ .set_rate = sh_clk_divider_set_rate,
+};
+
+#define FRQCR_PLL1EN BIT(10)
+static const unsigned int pll1mult[] = { 12, 12, 6, 12, 6, 12, 1};
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct cpg_priv *cpg = to_priv(hw);
+ unsigned long rate = parent_rate;
+ u16 frqcr;
+
+ frqcr = ioread16(cpg->frqcr);
+ if (frqcr & FRQCR_PLL1EN) {
+ rate *= pll1mult[cpg->mode];
+ if (cpg->mode < 6 && cpg->have_div1)
+ rate /= 2;
+ }
+ return rate;
+}
+
+static void get_round_rate(struct cpg_priv *cpg,
+ unsigned long *out, bool *pllen,
+ unsigned long rate, unsigned long prate)
+{
+ long pllout, res;
+ bool pll;
+
+ if (cpg->mode < 6 && cpg->have_div1)
+ prate /= 2;
+
+ pllout = prate * pll1mult[cpg->mode];
+ if (abs(pllout - rate) > abs(prate - rate)) {
+ res = prate;
+ pll = false;
+ } else {
+ res = pllout;
+ pll = true;
+ }
+ if (out)
+ *out = res;
+ if (pllen)
+ *pllen = pll;
+}
+
+static int pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct cpg_priv *cpg = to_priv(hw);
+
+ get_round_rate(cpg, &req->rate, NULL, req->rate, req->best_parent_rate);
+ return 0;
+}
+
+static int pll_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long prate)
+{
+ struct cpg_priv *cpg = to_priv(hw);
+ bool oldpll, newpll;
+ u16 frqcr;
+
+ frqcr = ioread16(cpg->frqcr);
+ get_round_rate(cpg, NULL, &newpll, rate, prate);
+ oldpll = frqcr & FRQCR_PLL1EN;
+ frqcr &= ~FRQCR_PLL1EN;
+
+ if (newpll) {
+ frqcr |= FRQCR_PLL1EN;
+ if (!oldpll) {
+ /* set PLL wakeup delay time */
+ iowrite16(0xa500, cpg->frqcr + WTCNT);
+ iowrite16(0xa507, cpg->frqcr + WTCNT);
+ iowrite16(0x5a00, cpg->frqcr + WTCSR);
+ }
+ }
+ iowrite16(frqcr, cpg->frqcr);
+
+ /* Test for new PLL state */
+ frqcr = ioread16(cpg->frqcr);
+ oldpll = frqcr & FRQCR_PLL1EN;
+ return !(oldpll == newpll);
+}
+
+static const struct clk_ops pll_ops = {
+ .recalc_rate = pll_recalc_rate,
+ .determine_rate = pll_determine_rate,
+ .set_rate = pll_set_rate,
+};
+
+#define PLLOUT "pllout"
+
+static int register_pll(struct device_node *node, struct cpg_priv *cpg)
+{
+ const char *clk_name = node->name;
+ const char *parent_name;
+ struct clk_init_data init;
+ int ret;
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.name = PLLOUT;
+ init.ops = &pll_ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ cpg->hw.init = &init;
+
+ ret = of_clk_hw_register(node, &cpg->hw);
+ if (ret < 0) {
+ pr_err("%s: failed to register %s pll clock (%d)\n",
+ __func__, clk_name, ret);
+ return ret;
+ }
+ if (ret < 0)
+ pr_err("%s: failed to add provider %s (%d)\n",
+ __func__, clk_name, ret);
+ return ret;
+}
+
+static void sbcr_sw(struct clk_hw *hw, bool on)
+{
+ struct clk_gate *gate = to_clk_gate(hw);
+ u8 msk = BIT(gate->bit_idx);
+ u8 val;
+
+ val = readb(gate->reg);
+ if (on)
+ val &= ~msk;
+ else
+ val |= msk;
+ writeb(val, gate->reg);
+}
+
+static int sbcr_enable(struct clk_hw *hw)
+{
+ sbcr_sw(hw, true);
+ return 0;
+}
+
+static void sbcr_disable(struct clk_hw *hw)
+{
+ sbcr_sw(hw, false);
+}
+
+static int sbcr_is_enabled(struct clk_hw *hw)
+{
+ u8 val;
+ struct clk_gate *gate = to_clk_gate(hw);
+
+ val = readb(gate->reg);
+ val &= 1 << gate->bit_idx;
+ return val != 0;
+}
+
+static const struct clk_ops gate_stbcr_ops = {
+ .enable = sbcr_enable,
+ .disable = sbcr_disable,
+ .is_enabled = sbcr_is_enabled,
+};
+
+static void clkstp00_sw(struct clk_hw *hw, bool on)
+{
+ u32 val;
+ struct clk_gate *gate = to_clk_gate(hw);
+
+ val = BIT(gate->bit_idx);
+ if (on)
+ writel(val, gate->reg + CLKSTPCLR00);
+ else
+ writel(val, gate->reg);
+}
+
+static int clkstp00_enable(struct clk_hw *hw)
+{
+ clkstp00_sw(hw, true);
+ return 0;
+}
+
+static void clkstp00_disable(struct clk_hw *hw)
+{
+ clkstp00_sw(hw, false);
+}
+
+static int clkstp00_is_enabled(struct clk_hw *hw)
+{
+ u8 val;
+ struct clk_gate *gate = to_clk_gate(hw);
+
+ val = readb(gate->reg);
+ val &= 1 << gate->bit_idx;
+ return val == 0;
+}
+
+static const struct clk_ops gate_clkstp00_ops = {
+ .enable = clkstp00_enable,
+ .disable = clkstp00_disable,
+ .is_enabled = clkstp00_is_enabled,
+};
+
+
+static void set_init_data(struct clk_init_data *init,
+ const char *name, const char **parent_name,
+ const struct clk_ops *ops)
+{
+ init->name = name;
+ init->ops = ops;
+ init->flags = 0;
+ init->parent_names = (parent_name ? parent_name : NULL);
+ init->num_parents = (parent_name ? 1 : 0);
+}
+
+static int _clk_register(struct device_node *node,
+ unsigned int num_clk, struct sh_clk_reg_arg *args,
+ spinlock_t *lock, struct clk_hw *pll_hw)
+{
+ struct clk_hw_onecell_data *data;
+ struct sh_clk_reg_arg *arg;
+ struct clk_divider *div = NULL, *divp;
+ struct clk_gate *gate = NULL, *gatep;
+ struct clk_init_data init;
+ struct clk_hw *reg_hw;
+ const char *parent;
+ unsigned int num_div, num_gate;
+ unsigned int i;
+ int ret = 0;
+
+ for (arg = args, num_div = 0, num_gate = 0, i = 0;
+ i < num_clk; arg++, i++) {
+ switch (arg->type) {
+ case CLK_DIV:
+ num_div++;
+ break;
+ case CLK_GATE:
+ num_gate++;
+ break;
+ }
+ }
+
+ data = kzalloc(struct_size(data, hws, num_clk + 1), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+ if (num_div > 0) {
+ div = kcalloc(num_div, sizeof(*div), GFP_KERNEL);
+ if (!div) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ }
+ if (num_gate > 0) {
+ gate = kcalloc(num_gate, sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ }
+
+ divp = div;
+ gatep = gate;
+ data->hws[0] = pll_hw;
+ data->num = num_clk + 1;
+
+ for (arg = args, i = 0; i < num_clk; arg++, i++) {
+ parent = arg->parent;
+ set_init_data(&init, arg->name, &parent, arg->ops);
+ switch (arg->type) {
+ case CLK_DIV:
+ divp->reg = arg->reg;
+ divp->shift = arg->div.shift;
+ divp->width = arg->div.width;
+ divp->lock = lock;
+ divp->hw.init = &init;
+ divp->table = arg->div.table;
+ reg_hw = &divp->hw;
+ divp++;
+ break;
+ case CLK_GATE:
+ gatep->reg = arg->reg;
+ gatep->bit_idx = arg->gate.bit_idx;
+ gatep->flags = arg->gate.flags;
+ gatep->lock = lock;
+ gatep->hw.init = &init;
+ reg_hw = &gatep->hw;
+ gatep++;
+ break;
+ }
+ ret = of_clk_hw_register(node, reg_hw);
+ if (ret < 0)
+ goto error;
+
+ data->hws[i + 1] = reg_hw;
+ }
+
+ ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
+ if (ret < 0)
+ goto error;
+ return 0;
+error:
+ kfree(data);
+ kfree(div);
+ kfree(gate);
+ return ret;
+}
+
+static int register_div(struct device_node *node, struct cpg_priv *cpg)
+{
+ static const char * const divout[] = {
+ "fck", "bck", "ick",
+ };
+ static const char * const mstpout[] = {
+ "sci_clk", "rtc_clk", "tmu012_clk", /* STBCR */
+ "scif_clk", "dmac_clk", /* STBCR */
+ "ubc_clk", "sq_clk", /* STBCR2 */
+ "intc_clk", "tmu34_clk", "pcic_clk", /* CLKSTP00 */
+ };
+ struct sh_clk_reg_arg args[ARRAY_SIZE(divout) + ARRAY_SIZE(mstpout)];
+ unsigned int i, j;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(divout); i++) {
+ args[i].type = CLK_DIV;
+ args[i].name = divout[i];
+ args[i].parent = PLLOUT;
+ args[i].reg = cpg->frqcr;
+ args[i].ops = &sh_clk_divider_ops;
+ args[i].div.shift = i * 3;
+ args[i].div.width = 3;
+ args[i].div.table = (i == 0) ? pdiv_table : div_table;
+ }
+ for (i = 0, j = ARRAY_SIZE(divout); j < ARRAY_SIZE(args); i++, j++) {
+ args[j].type = CLK_GATE;
+ args[j].name = mstpout[i];
+ args[j].parent = divout[0];
+ switch (i) {
+ case 0 ... 4:
+ args[j].reg = cpg->frqcr + STBCR;
+ args[j].gate.bit_idx = i;
+ args[j].ops = &gate_stbcr_ops;
+ break;
+ case 5 ... 6:
+ args[j].reg = cpg->frqcr + STBCR2;
+ args[j].gate.bit_idx = i - 5;
+ args[j].ops = &gate_stbcr_ops;
+ break;
+ case 7 ... 9:
+ args[j].reg = cpg->clkstp00;
+ args[j].gate.bit_idx = i - 7;
+ args[j].ops = &gate_clkstp00_ops;
+ break;
+ }
+ }
+
+ ret = _clk_register(node, ARRAY_SIZE(args), args,
+ &cpg->clklock, &cpg->hw);
+ if (ret < 0)
+ pr_err("%pOF: failed to register clock (%d)\n",
+ node, ret);
+ return ret;
+}
+
+static struct cpg_priv *sh7750_cpg_setup(struct device_node *node)
+{
+ unsigned int num_parents;
+ u32 mode;
+ struct cpg_priv *cpg;
+ int ret = 0;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: no parent found", node->name);
+ return ERR_PTR(-ENODEV);
+ }
+
+ of_property_read_u32_index(node, "renesas,mode", 0, &mode);
+ if (mode >= 7) {
+ pr_err("%s: Invalid clock mode setting (%u)\n",
+ node->name, mode);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cpg = kzalloc(sizeof(struct cpg_priv), GFP_KERNEL);
+ if (!cpg) {
+ pr_err("%pOF: failed to alloc memory", node);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ cpg->frqcr = of_iomap(node, 0);
+ if (cpg->frqcr == NULL) {
+ pr_err("%pOF: failed to map divide register", node);
+ ret = -ENODEV;
+ goto cpg_free;
+ }
+
+ cpg->clkstp00 = of_iomap(node, 1);
+ if (cpg->clkstp00 == NULL) {
+ pr_err("%pOF: failed to map clkstp00 register", node);
+ ret = -ENODEV;
+ goto unmap_frqcr;
+ }
+ cpg->mode = mode;
+
+ ret = register_pll(node, cpg);
+ if (ret < 0)
+ goto unmap_clkstp00;
+
+ ret = register_div(node, cpg);
+ if (ret < 0)
+ goto unmap_clkstp00;
+
+ return cpg;
+
+unmap_clkstp00:
+ iounmap(cpg->clkstp00);
+unmap_frqcr:
+ iounmap(cpg->frqcr);
+cpg_free:
+ kfree(cpg);
+ return ERR_PTR(ret);
+}
+
+static void __init sh7750_cpg_init(struct device_node *node)
+{
+ cpg_data = sh7750_cpg_setup(node);
+ if (IS_ERR(cpg_data))
+ cpg_data = NULL;
+ else
+ cpg_data->have_div1 = !of_device_is_compatible(node, "renesas,sh7750r");
+}
+
+CLK_OF_DECLARE_DRIVER(sh7750_cpg, "renesas,sh7750-cpg",
+ sh7750_cpg_init);
+
+static int sh7750_cpg_probe(struct platform_device *pdev)
+{
+ if (cpg_data)
+ return 0;
+ cpg_data = sh7750_cpg_setup(pdev->dev.of_node);
+ if (IS_ERR(cpg_data))
+ return PTR_ERR(cpg_data);
+ cpg_data->have_div1 = (of_device_get_match_data(&pdev->dev) != NULL);
+ return 0;
+}
+
+static const struct of_device_id sh7750_cpg_of_match[] = {
+ { .compatible = "renesas,sh7750-cpg",
+ .data = (void *)1 },
+ { .compatible = "renesas,sh7750s-cpg",
+ .data = (void *)1 },
+ { .compatible = "renesas,sh7750r-cpg",
+ .data = 0 },
+ { .compatible = "renesas,sh7751-cpg",
+ .data = (void *)1 },
+ { .compatible = "renesas,sh7751r-cpg",
+ .data = 0 },
+ { }
+};
+
+static struct platform_driver sh7750_cpg_driver = {
+ .probe = sh7750_cpg_probe,
+ .driver = {
+ .name = "sh7750-cpg",
+ .of_match_table = sh7750_cpg_of_match,
+ },
+};
+builtin_platform_driver(sh7750_cpg_driver);
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver.
2023-10-14 14:53 ` [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver Yoshinori Sato
@ 2023-10-18 13:02 ` Geert Uytterhoeven
2023-10-19 7:18 ` Geert Uytterhoeven
1 sibling, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 13:02 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, mturquette, sboyd, linux-clk
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> This driver supported SH7750/7751 PLL/Divider clock and module stop.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> ---
> drivers/clk/renesas/Kconfig | 21 +-
> drivers/clk/renesas/Makefile | 1 +
> drivers/clk/renesas/clk-sh7750.c | 787 +++++++++++++++++++++++++++++++
> 3 files changed, 807 insertions(+), 2 deletions(-)
> create mode 100644 drivers/clk/renesas/clk-sh7750.c
>
> diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
> index 37632a0659d8..c52c038ce715 100644
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -1,8 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
>
> config CLK_RENESAS
> - bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
> - default y if ARCH_RENESAS
> + bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS && SUPERH
"!SUPERH", so the symbol becomes invisible but enabled on SH.
> + default y if ARCH_RENESAS || SUPERH
> select CLK_EMEV2 if ARCH_EMEV2
> select CLK_RZA1 if ARCH_R7S72100
> select CLK_R7S9210 if ARCH_R7S9210
> @@ -39,6 +39,11 @@ config CLK_RENESAS
> select CLK_R9A07G054 if ARCH_R9A07G054
> select CLK_R9A09G011 if ARCH_R9A09G011
> select CLK_SH73A0 if ARCH_SH73A0
> + select CLK_SH7750 if CPU_SUBTYPE_SH7750
> + select CLK_SH7750 if CPU_SUBTYPE_SH7750S
> + select CLK_SH7750 if CPU_SUBTYPE_SH7750R
> + select CLK_SH7750 if CPU_SUBTYPE_SH7751
> + select CLK_SH7750 if CPU_SUBTYPE_SH7751R
Please combine all of the above into a single statement using "||",
like is done for other shared drivers.
>
> if CLK_RENESAS
>
> @@ -188,6 +193,10 @@ config CLK_SH73A0
> select CLK_RENESAS_CPG_MSTP
> select CLK_RENESAS_DIV6
>
> +config CLK_SH7750
> + bool "SH7750/7751 family clock support" if COMPILE_TEST
> + help
> + This is a driver for SH7750 / SH7751 CPG.
>
> # Family
> config CLK_RCAR_CPG_LIB
> @@ -218,6 +227,14 @@ config CLK_RZG2L
> bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
> select RESET_CONTROLLER
>
> +config CLK_SH7750
> + bool "Renesas SH7750/7751 family clock support"
"if COMPILE_TEST", so the symbol becomes invisible when auto-enabled.
> + depends on CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
> + CPU_SUBTYPE_SH7750R || \
> + CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R || COMPILE_TEST
Please drop this dependency, as it is not needed.
> --- /dev/null
> +++ b/drivers/clk/renesas/clk-sh7750.c
> +static void sbcr_sw(struct clk_hw *hw, bool on)
> +{
> + struct clk_gate *gate = to_clk_gate(hw);
> + u8 msk = BIT(gate->bit_idx);
> + u8 val;
> +
> + val = readb(gate->reg);
> + if (on)
> + val &= ~msk;
> + else
> + val |= msk;
> + writeb(val, gate->reg);
RMW (Read-Modify-Write) needs locking.
> +}
> +
> +static int sbcr_enable(struct clk_hw *hw)
> +{
> + sbcr_sw(hw, true);
> + return 0;
> +}
> +
> +static void sbcr_disable(struct clk_hw *hw)
> +{
> + sbcr_sw(hw, false);
> +}
> +
> +static int sbcr_is_enabled(struct clk_hw *hw)
> +{
> + u8 val;
> + struct clk_gate *gate = to_clk_gate(hw);
> +
> + val = readb(gate->reg);
> + val &= 1 << gate->bit_idx;
> + return val != 0;
> +}
> +
> +static const struct clk_ops gate_stbcr_ops = {
> + .enable = sbcr_enable,
> + .disable = sbcr_disable,
> + .is_enabled = sbcr_is_enabled,
> +};
These are almost identical to clk_gate_ops, except that they use
8-bit instead of 32-bit register accesses.
Perhaps you can extend the standard gate clock in drivers/clk/clk-gate.c
instead, using a new CLK_GATE_* flag?
> +
> +static void clkstp00_sw(struct clk_hw *hw, bool on)
> +{
> + u32 val;
> + struct clk_gate *gate = to_clk_gate(hw);
> +
> + val = BIT(gate->bit_idx);
> + if (on)
> + writel(val, gate->reg + CLKSTPCLR00);
> + else
> + writel(val, gate->reg);
> +}
> +
> +static int clkstp00_enable(struct clk_hw *hw)
> +{
> + clkstp00_sw(hw, true);
> + return 0;
> +}
> +
> +static void clkstp00_disable(struct clk_hw *hw)
> +{
> + clkstp00_sw(hw, false);
> +}
> +
> +static int clkstp00_is_enabled(struct clk_hw *hw)
> +{
> + u8 val;
> + struct clk_gate *gate = to_clk_gate(hw);
> +
> + val = readb(gate->reg);
readl()?
> + val &= 1 << gate->bit_idx;
> + return val == 0;
> +}
> +
> +static const struct clk_ops gate_clkstp00_ops = {
> + .enable = clkstp00_enable,
> + .disable = clkstp00_disable,
> + .is_enabled = clkstp00_is_enabled,
> +};
These look identical to clk_gate_ops, so you can just use
clk_register_gate() instead?
> +static int register_div(struct device_node *node, struct cpg_priv *cpg)
> +{
> + static const char * const divout[] = {
> + "fck", "bck", "ick",
> + };
> + static const char * const mstpout[] = {
> + "sci_clk", "rtc_clk", "tmu012_clk", /* STBCR */
> + "scif_clk", "dmac_clk", /* STBCR */
> + "ubc_clk", "sq_clk", /* STBCR2 */
FTR, qemu does not support STBCR and STBCR2 yet, causing
"qemu-system-sh4 -M r2d" to crash. I have posted a patch to fix that:
"[PATCH RFC] hw/sh4/sh7750: Add STBCR/STBCR2 register support"
https://lore.kernel.org/all/20231018124023.2927710-1-geert+renesas@glider.be
> + "intc_clk", "tmu34_clk", "pcic_clk", /* CLKSTP00 */
> + };
The order of the entries in these two arrays is tied intimately to
the values in include/dt-bindings/clock/sh7750.h. Hence I think it
would be good to reflect that in the data and code below, by using
the SH7750_CPG_* identifier.
> + struct sh_clk_reg_arg args[ARRAY_SIZE(divout) + ARRAY_SIZE(mstpout)];
> + unsigned int i, j;
> + int ret;
> +
> + for (i = 0; i < ARRAY_SIZE(divout); i++) {
> + args[i].type = CLK_DIV;
> + args[i].name = divout[i];
> + args[i].parent = PLLOUT;
> + args[i].reg = cpg->frqcr;
> + args[i].ops = &sh_clk_divider_ops;
> + args[i].div.shift = i * 3;
> + args[i].div.width = 3;
> + args[i].div.table = (i == 0) ? pdiv_table : div_table;
> + }
> + for (i = 0, j = ARRAY_SIZE(divout); j < ARRAY_SIZE(args); i++, j++) {
> + args[j].type = CLK_GATE;
> + args[j].name = mstpout[i];
> + args[j].parent = divout[0];
> + switch (i) {
> + case 0 ... 4:
> + args[j].reg = cpg->frqcr + STBCR;
> + args[j].gate.bit_idx = i;
> + args[j].ops = &gate_stbcr_ops;
> + break;
> + case 5 ... 6:
> + args[j].reg = cpg->frqcr + STBCR2;
> + args[j].gate.bit_idx = i - 5;
> + args[j].ops = &gate_stbcr_ops;
> + break;
> + case 7 ... 9:
> + args[j].reg = cpg->clkstp00;
> + args[j].gate.bit_idx = i - 7;
> + args[j].ops = &gate_clkstp00_ops;
> + break;
> + }
> + }
> +
> + ret = _clk_register(node, ARRAY_SIZE(args), args,
> + &cpg->clklock, &cpg->hw);
> + if (ret < 0)
> + pr_err("%pOF: failed to register clock (%d)\n",
> + node, ret);
> + return ret;
> +}
> +
> +static struct cpg_priv *sh7750_cpg_setup(struct device_node *node)
> +{
> + unsigned int num_parents;
> + u32 mode;
> + struct cpg_priv *cpg;
> + int ret = 0;
> +
> + num_parents = of_clk_get_parent_count(node);
> + if (num_parents < 1) {
> + pr_err("%s: no parent found", node->name);
> + return ERR_PTR(-ENODEV);
> + }
> +
> + of_property_read_u32_index(node, "renesas,mode", 0, &mode);
> + if (mode >= 7) {
> + pr_err("%s: Invalid clock mode setting (%u)\n",
> + node->name, mode);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + cpg = kzalloc(sizeof(struct cpg_priv), GFP_KERNEL);
> + if (!cpg) {
> + pr_err("%pOF: failed to alloc memory", node);
No need to print an error message on allocation failure, as the
core memory allocation code already took care of that.
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + cpg->frqcr = of_iomap(node, 0);
> + if (cpg->frqcr == NULL) {
!cpg->frqcr
> + pr_err("%pOF: failed to map divide register", node);
> + ret = -ENODEV;
> + goto cpg_free;
> + }
> +
> + cpg->clkstp00 = of_iomap(node, 1);
> + if (cpg->clkstp00 == NULL) {
!cpg->clkstp00
> + pr_err("%pOF: failed to map clkstp00 register", node);
> + ret = -ENODEV;
> + goto unmap_frqcr;
> + }
> + cpg->mode = mode;
> +
> + ret = register_pll(node, cpg);
> + if (ret < 0)
> + goto unmap_clkstp00;
> +
> + ret = register_div(node, cpg);
> + if (ret < 0)
> + goto unmap_clkstp00;
> +
> + return cpg;
> +
> +unmap_clkstp00:
> + iounmap(cpg->clkstp00);
> +unmap_frqcr:
> + iounmap(cpg->frqcr);
> +cpg_free:
> + kfree(cpg);
> + return ERR_PTR(ret);
> +}
> +
> +static void __init sh7750_cpg_init(struct device_node *node)
> +{
> + cpg_data = sh7750_cpg_setup(node);
> + if (IS_ERR(cpg_data))
> + cpg_data = NULL;
> + else
> + cpg_data->have_div1 = !of_device_is_compatible(node, "renesas,sh7750r");
Please no explicit of_device_is_compatible() checks in code that is
called through a compatible-based match.
You can differentiate using multiple CLK_OF_DECLARE_DRIVER() stances,\
each with a different init function.
> +}
> +
> +CLK_OF_DECLARE_DRIVER(sh7750_cpg, "renesas,sh7750-cpg",
> + sh7750_cpg_init);
> +
> +static int sh7750_cpg_probe(struct platform_device *pdev)
> +{
> + if (cpg_data)
> + return 0;
> + cpg_data = sh7750_cpg_setup(pdev->dev.of_node);
> + if (IS_ERR(cpg_data))
> + return PTR_ERR(cpg_data);
> + cpg_data->have_div1 = (of_device_get_match_data(&pdev->dev) != NULL);
> + return 0;
> +}
> +
> +static const struct of_device_id sh7750_cpg_of_match[] = {
> + { .compatible = "renesas,sh7750-cpg",
> + .data = (void *)1 },
> + { .compatible = "renesas,sh7750s-cpg",
> + .data = (void *)1 },
> + { .compatible = "renesas,sh7750r-cpg",
> + .data = 0 },
> + { .compatible = "renesas,sh7751-cpg",
> + .data = (void *)1 },
> + { .compatible = "renesas,sh7751r-cpg",
> + .data = 0 },
> + { }
> +};
> +
> +static struct platform_driver sh7750_cpg_driver = {
> + .probe = sh7750_cpg_probe,
> + .driver = {
> + .name = "sh7750-cpg",
> + .of_match_table = sh7750_cpg_of_match,
> + },
> +};
> +builtin_platform_driver(sh7750_cpg_driver);
As the clock driver is always probed early through
CLK_OF_DECLARE_DRIVER, what is the use of the extra platform driver?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver.
2023-10-14 14:53 ` [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver Yoshinori Sato
2023-10-18 13:02 ` Geert Uytterhoeven
@ 2023-10-19 7:18 ` Geert Uytterhoeven
1 sibling, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 7:18 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, mturquette, sboyd, linux-clk
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> This driver supported SH7750/7751 PLL/Divider clock and module stop.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/clk/renesas/clk-sh7750.c
> +static void sbcr_sw(struct clk_hw *hw, bool on)
> +{
> + struct clk_gate *gate = to_clk_gate(hw);
> + u8 msk = BIT(gate->bit_idx);
> + u8 val;
> +
> + val = readb(gate->reg);
> + if (on)
> + val &= ~msk;
> + else
> + val |= msk;
> + writeb(val, gate->reg);
> +}
> +
> +static int sbcr_enable(struct clk_hw *hw)
> +{
> + sbcr_sw(hw, true);
> + return 0;
> +}
> +
> +static void sbcr_disable(struct clk_hw *hw)
> +{
> + sbcr_sw(hw, false);
> +}
> +
> +static int sbcr_is_enabled(struct clk_hw *hw)
> +{
> + u8 val;
> + struct clk_gate *gate = to_clk_gate(hw);
> +
> + val = readb(gate->reg);
> + val &= 1 << gate->bit_idx;
> + return val != 0;
This condition is inverted: 0 is enabled, 1 is stopped.
> +}
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (11 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 13:41 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
` (22 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-clk, devicetree
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../bindings/clock/renesas,sh7750-cpg.yaml | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
diff --git a/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
new file mode 100644
index 000000000000..a640968ed005
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,sh7750-cpg # SH7750
+ - renesas,sh7750s-cpg # SH775S
+ - renesas,sh7750r-cpg # SH7750R
+ - renesas,sh7751-cpg # SH7751
+ - renesas,sh7751r-cpg # SH7751R
+ - const: renesas,sh7750-cpg
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: FRQCR
+ - const: CLKSTP00
+
+ clocks: true
+
+ clock-names: true
+
+ '#clock-cells':
+ const: 1
+
+ renesas,mode:
+ description: Board-specific settings of the MD[0-2] pins on SoC
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sh7750.h>
+ cpg: clock-controller@ffc00000 {
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ compatible = "renesas,sh7751r-cpg";
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ reg = <0xffc00000 20>, <0xfe0a0000 16>;
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document.
2023-10-14 14:53 ` [RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document Yoshinori Sato
@ 2023-10-18 13:41 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 13:41 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-clk, devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7750/7751 Clock Pulse Generator (CPG)
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +description:
> + The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
> + includes PLLs, and variable ratio dividers.
> +
> + The CPG may also provide a Clock Domain for SoC devices, in combination with
> + the CPG Module Stop (MSTP) Clocks.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,sh7750-cpg # SH7750
> + - renesas,sh7750s-cpg # SH775S
> + - renesas,sh7750r-cpg # SH7750R
> + - renesas,sh7751-cpg # SH7751
> + - renesas,sh7751r-cpg # SH7751R
> + - const: renesas,sh7750-cpg
As there are important differences between the CPG variants, I think
it makes sense to drop the "renesas,sh7750-cpg", fallback, like you
BTW already did in the example below.
Then you can drop the "items", and just keep "enum".
> +examples:
> + - |
> + #include <dt-bindings/clock/sh7750.h>
> + cpg: clock-controller@ffc00000 {
> + #clock-cells = <1>;
> + #power-domain-cells = <0>;
> + compatible = "renesas,sh7751r-cpg";
> + clocks = <&xtal>;
> + clock-names = "xtal";
> + reg = <0xffc00000 20>, <0xfe0a0000 16>;
$ make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.example.dtb:
clock-controller@ffc00000: compatible: ['renesas,sh7751r-cpg'] is too
short
from schema $id:
http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.example.dtb:
clock-controller@ffc00000: 'reg-names' is a required property
from schema $id:
http://devicetree.org/schemas/clock/renesas,sh7750-cpg.yaml#
> + };
> --
> 2.39.2
>
--
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (12 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 13/35] Documentation/devicetree/bindings/clock: Add renesas,sh7750-cpg binding document Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-17 9:27 ` Geert Uytterhoeven
2023-10-18 8:02 ` Thomas Gleixner
2023-10-14 14:53 ` [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml Yoshinori Sato
` (21 subsequent siblings)
35 siblings, 2 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, tglx, maz
SH7751 Internal interrupt controler driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/irqchip/Kconfig | 9 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-sh7751.c | 255 +++++++++++++++++++++++++++
3 files changed, 265 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f7149d0f3d45..87bd490fec21 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -679,4 +679,13 @@ config SUNPLUS_SP7021_INTC
chained controller, routing all interrupt source in P-Chip to
the primary controller on C-Chip.
+config RENESAS_SH7751_INTC
+ bool "Renesas SH7751 Interrupt Controller"
+ depends on SH_DEVICE_TREE || COMPILE_TEST
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Support for the Renesas SH7751 On-chip interrupt controller.
+ And external interrupt encoder for some targets.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ffd945fe71aa..26c91d075e25 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -120,3 +120,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
+obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
diff --git a/drivers/irqchip/irq-renesas-sh7751.c b/drivers/irqchip/irq-renesas-sh7751.c
new file mode 100644
index 000000000000..585367d9c9a4
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 interrupt controller driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of.h>
+#include <linux/bsearch.h>
+#include <linux/io.h>
+#include <linux/sort.h>
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+
+struct iprmap {
+ unsigned int irq;
+ unsigned int reg;
+ unsigned int bits;
+};
+
+struct sh7751_intc_priv {
+ void *icr;
+ void *ipr;
+ void *intpri00;
+ void *intreq00;
+ void *intmsk00;
+ void *intmskclr00;
+ struct iprmap *iprmap;
+ unsigned int num_ipr;
+ bool irlm;
+};
+
+#define ICR_IRLM BIT(7)
+
+/* Bitmap of IRQ masked */
+#define IMASK_PRIORITY 15
+
+static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
+static int interrupt_priority;
+
+static inline void set_interrupt_registers(int ip)
+{
+ unsigned long __dummy;
+
+ asm volatile(
+#ifdef CONFIG_CPU_HAS_SR_RB
+ "ldc %2, r6_bank\n\t"
+#endif
+ "stc sr, %0\n\t"
+ "and #0xf0, %0\n\t"
+ "shlr2 %0\n\t"
+ "cmp/eq #0x3c, %0\n\t"
+ "bt/s 1f ! CLI-ed\n\t"
+ " stc sr, %0\n\t"
+ "and %1, %0\n\t"
+ "or %2, %0\n\t"
+ "ldc %0, sr\n"
+ "1:"
+ : "=&z" (__dummy)
+ : "r" (~0xf0), "r" (ip << 4)
+ : "t");
+}
+static int search_ipr_comp(const void *a, const void *b)
+{
+ return (int)a - ((struct iprmap *)b)->irq;
+}
+
+static void update_ipr(struct sh7751_intc_priv *priv, int irq, int pval)
+{
+ void *prireg;
+ struct iprmap *p;
+ u16 pri;
+
+ p = bsearch((void *)irq, priv->iprmap, priv->num_ipr,
+ sizeof(struct iprmap), search_ipr_comp);
+ if (p) {
+ prireg = (p->reg < INTPRI00) ? priv->ipr : priv->intpri00;
+ prireg += p->reg & (INTPRI00 - 1);
+ pri = ~(0x000f << p->bits);
+ pri &= __raw_readw(prireg);
+ pri |= (pval & 0x0f) << p->bits;
+ __raw_writew(pri, prireg);
+ } else
+ pr_warn_once("%s: undefined IPR in irq %d\n", __FILE__, irq);
+}
+
+static void sh7751_disable_irq(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ struct sh7751_intc_priv *priv = data->chip_data;
+
+ if (irq < 16 && !priv->irlm) {
+ /* IRL encoded externel interrupt */
+ /* disable for SR.IMASK */
+ clear_bit(irq, imask_mask);
+ if (interrupt_priority < IMASK_PRIORITY - irq)
+ interrupt_priority = IMASK_PRIORITY - irq;
+ set_interrupt_registers(interrupt_priority);
+ } else
+ /* Internal periphreal interrupt */
+ /* IPR priority is 0 */
+ update_ipr(priv, irq, 0);
+}
+
+static void sh7751_enable_irq(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ struct sh7751_intc_priv *priv = data->chip_data;
+
+ if (irq < 16 && !priv->irlm) {
+ set_bit(irq, imask_mask);
+ interrupt_priority = IMASK_PRIORITY -
+ find_first_bit(imask_mask, IMASK_PRIORITY);
+ set_interrupt_registers(interrupt_priority);
+ } else
+ update_ipr(priv, irq, 1);
+}
+
+static const struct irq_chip sh7751_irq_chip = {
+ .name = "SH7751-INTC",
+ .irq_unmask = sh7751_enable_irq,
+ .irq_mask = sh7751_disable_irq,
+};
+
+static int irq_sh7751_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+static const struct irq_domain_ops irq_ops = {
+ .map = irq_sh7751_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int sort_ipr_cmp(const void *a, const void *b)
+{
+ unsigned int irq_a = ((struct iprmap *)a)->irq;
+ unsigned int irq_b = ((struct iprmap *)b)->irq;
+
+ return irq_a - irq_b;
+}
+
+static void sort_ipr_swap(void *a, void *b, int sz)
+{
+ struct iprmap tmp;
+
+ memcpy(&tmp, a, sizeof(tmp));
+ memcpy(a, b, sizeof(tmp));
+ memcpy(b, &tmp, sizeof(tmp));
+}
+
+static int __init load_ipr_map(struct device_node *intc,
+ struct sh7751_intc_priv *priv)
+{
+ int num_ipr;
+ struct iprmap *p;
+ u32 val[3];
+ unsigned int i, idx;
+
+ num_ipr = of_property_count_elems_of_size(intc, "renesas,ipr-map", sizeof(u32) * 3);
+ if (num_ipr < 0)
+ return num_ipr;
+
+ priv->iprmap = kcalloc(num_ipr, sizeof(struct iprmap), GFP_KERNEL);
+ if (priv->iprmap == NULL) {
+ pr_err("%s: Failed to alloc memory\n", intc->name);
+ return -ENOMEM;
+ }
+ priv->num_ipr = num_ipr;
+
+ for (p = priv->iprmap, idx = 0; num_ipr > 0; p++, num_ipr--) {
+ for (i = 0; i < 3; idx++, i++) {
+ if (of_property_read_u32_index(intc, "renesas,ipr-map",
+ idx, &val[i])) {
+ pr_err("%s: Failed to load ipr-map\n", intc->name);
+ kfree(priv->iprmap);
+ return -EINVAL;
+ }
+ }
+ p->irq = evt2irq(val[0]);
+ p->reg = val[1];
+ p->bits = val[2];
+ }
+ /* This table will be searched using bsearch, so sort it. */
+ sort(priv->iprmap, priv->num_ipr, sizeof(struct iprmap),
+ sort_ipr_cmp, sort_ipr_swap);
+
+ for (p = priv->iprmap, idx = 0; idx < priv->num_ipr; p++, idx++)
+ pr_debug("irq=%04x reg=%02x bits=%d\n", p->irq, p->reg, p->bits);
+ return 0;
+}
+
+static int __init sh7751_intc_of_init(struct device_node *intc,
+ struct device_node *parent)
+{
+ u16 icr;
+ struct irq_domain *domain;
+ void *intc_baseaddr;
+ void *intc_baseaddr2;
+ struct sh7751_intc_priv *priv;
+ int ret;
+
+ intc_baseaddr = of_iomap(intc, 0);
+ intc_baseaddr2 = of_iomap(intc, 1);
+ if (IS_ERR(intc_baseaddr)) {
+ pr_err("%pOFP: Invalid register definition\n", intc);
+ return -EINVAL;
+ }
+
+ priv = kzalloc(sizeof(struct sh7751_intc_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ pr_err("%pOFP: Failed to alloc memory\n", intc);
+ return -ENOMEM;
+ }
+ ret = load_ipr_map(intc, priv);
+ if (ret < 0) {
+ kfree(priv);
+ return ret;
+ }
+
+ priv->icr = intc_baseaddr;
+ priv->ipr = intc_baseaddr + 4;
+ priv->intpri00 = intc_baseaddr2;
+ priv->intreq00 = intc_baseaddr2 + 0x20;
+ priv->intmsk00 = intc_baseaddr2 + 0x40;
+ priv->intmskclr00 = intc_baseaddr2 + 0x60;
+
+ if (of_property_read_bool(intc, "renesas,irlm")) {
+ priv->irlm = true;
+ icr = __raw_readw(priv->icr);
+ icr |= ICR_IRLM;
+ __raw_writew(icr, priv->icr);
+ }
+
+ domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, priv);
+ if (domain == NULL) {
+ pr_err("%pOFP: cannot initialize irq domain\n", intc);
+ kfree(priv);
+ return -ENOMEM;
+ }
+
+ irq_set_default_host(domain);
+ pr_info("%pOFP: SH7751 Interrupt controller (%s external IRQ)",
+ intc, priv->irlm ? "4 lines" : "15 level");
+ return 0;
+}
+
+IRQCHIP_DECLARE(sh_7751_intc,
+ "renesas,sh7751-intc", sh7751_intc_of_init);
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-10-14 14:53 ` [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
@ 2023-10-17 9:27 ` Geert Uytterhoeven
2023-10-18 8:02 ` Thomas Gleixner
1 sibling, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-17 9:27 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz, tglx, maz
Hi Sato-san,
Thanks for your patch!
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> SH7751 Internal interrupt controler driver.
controller
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> --- /dev/null
> +++ b/drivers/irqchip/irq-renesas-sh7751.c
> +static int __init load_ipr_map(struct device_node *intc,
> + struct sh7751_intc_priv *priv)
> +{
> + int num_ipr;
> + struct iprmap *p;
> + u32 val[3];
> + unsigned int i, idx;
> +
> + num_ipr = of_property_count_elems_of_size(intc, "renesas,ipr-map", sizeof(u32) * 3);
> + if (num_ipr < 0)
> + return num_ipr;
> +
> + priv->iprmap = kcalloc(num_ipr, sizeof(struct iprmap), GFP_KERNEL);
> + if (priv->iprmap == NULL) {
> + pr_err("%s: Failed to alloc memory\n", intc->name);
No need to print anything, as the memory allocation core code already
takes care of that.
> + return -ENOMEM;
> + }
> + priv->num_ipr = num_ipr;
> +
> + for (p = priv->iprmap, idx = 0; num_ipr > 0; p++, num_ipr--) {
> + for (i = 0; i < 3; idx++, i++) {
> + if (of_property_read_u32_index(intc, "renesas,ipr-map",
> + idx, &val[i])) {
You can use of_find_property() once to find the property, and iterate
its values using of_prop_next_u32().
> + pr_err("%s: Failed to load ipr-map\n", intc->name);
> + kfree(priv->iprmap);
> + return -EINVAL;
> + }
> + }
> + p->irq = evt2irq(val[0]);
> + p->reg = val[1];
> + p->bits = val[2];
> + }
> + /* This table will be searched using bsearch, so sort it. */
> + sort(priv->iprmap, priv->num_ipr, sizeof(struct iprmap),
> + sort_ipr_cmp, sort_ipr_swap);
> +
> + for (p = priv->iprmap, idx = 0; idx < priv->num_ipr; p++, idx++)
> + pr_debug("irq=%04x reg=%02x bits=%d\n", p->irq, p->reg, p->bits);
> + return 0;
> +}
> +
> +static int __init sh7751_intc_of_init(struct device_node *intc,
> + struct device_node *parent)
> +{
> + u16 icr;
> + struct irq_domain *domain;
> + void *intc_baseaddr;
> + void *intc_baseaddr2;
> + struct sh7751_intc_priv *priv;
> + int ret;
> +
> + intc_baseaddr = of_iomap(intc, 0);
> + intc_baseaddr2 = of_iomap(intc, 1);
> + if (IS_ERR(intc_baseaddr)) {
of_iomap() returns NULL on failure.
Missing check for intc_baseaddr2.
> + pr_err("%pOFP: Invalid register definition\n", intc);
> + return -EINVAL;
> + }
> +
> + priv = kzalloc(sizeof(struct sh7751_intc_priv), GFP_KERNEL);
> + if (priv == NULL) {
> + pr_err("%pOFP: Failed to alloc memory\n", intc);
No need to print anything, as the memory allocation core code already
takes care of that.
> + return -ENOMEM;
> + }
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-10-14 14:53 ` [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
2023-10-17 9:27 ` Geert Uytterhoeven
@ 2023-10-18 8:02 ` Thomas Gleixner
2023-10-18 8:18 ` Geert Uytterhoeven
1 sibling, 1 reply; 88+ messages in thread
From: Thomas Gleixner @ 2023-10-18 8:02 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: Yoshinori Sato, glaubitz, maz
On Sat, Oct 14 2023 at 23:53, Yoshinori Sato wrote:
> +config RENESAS_SH7751_INTC
> + bool "Renesas SH7751 Interrupt Controller"
> + depends on SH_DEVICE_TREE || COMPILE_TEST
> + select IRQ_DOMAIN
> + select IRQ_DOMAIN_HIERARCHY
IRQ_DOMAIN_HIERARCHY selects IRQ_DOMAIN already
> +struct sh7751_intc_priv {
> + void *icr;
> + void *ipr;
> + void *intpri00;
> + void *intreq00;
> + void *intmsk00;
> + void *intmskclr00;
> + struct iprmap *iprmap;
> + unsigned int num_ipr;
> + bool irlm;
> +};
See the other mail vs. formatting
> +#define ICR_IRLM BIT(7)
> +
> +/* Bitmap of IRQ masked */
> +#define IMASK_PRIORITY 15
> +
> +static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
> +static int interrupt_priority;
> +
> +static inline void set_interrupt_registers(int ip)
> +{
> + unsigned long __dummy;
> +
> + asm volatile(
> +#ifdef CONFIG_CPU_HAS_SR_RB
> + "ldc %2, r6_bank\n\t"
> +#endif
> + "stc sr, %0\n\t"
> + "and #0xf0, %0\n\t"
> + "shlr2 %0\n\t"
> + "cmp/eq #0x3c, %0\n\t"
> + "bt/s 1f ! CLI-ed\n\t"
> + " stc sr, %0\n\t"
> + "and %1, %0\n\t"
> + "or %2, %0\n\t"
> + "ldc %0, sr\n"
> + "1:"
> + : "=&z" (__dummy)
> + : "r" (~0xf0), "r" (ip << 4)
> + : "t");
Why has this to be ASM and cannot be done in C with the existing
accessors? Also this really lacks a comment what this is actually doing.
> +}
Missing newline after }.
> +static int search_ipr_comp(const void *a, const void *b)
> +{
> + return (int)a - ((struct iprmap *)b)->irq;
(long)a please. It does not matter on 32-bit, but casting a pointer to
long is the correct way to do it.
> +}
> +
> +static void update_ipr(struct sh7751_intc_priv *priv, int irq, int pval)
> +{
> + void *prireg;
> + struct iprmap *p;
> + u16 pri;
See the othermail vs. variable declarations. Please fix all over the place.
> + p = bsearch((void *)irq, priv->iprmap, priv->num_ipr,
> + sizeof(struct iprmap), search_ipr_comp);
See Documentation vs. line breaks and argument alignment
> + if (p) {
> + prireg = (p->reg < INTPRI00) ? priv->ipr : priv->intpri00;
> + prireg += p->reg & (INTPRI00 - 1);
> + pri = ~(0x000f << p->bits);
No magic numbers please. Use a define.
> + pri &= __raw_readw(prireg);
> + pri |= (pval & 0x0f) << p->bits;
> + __raw_writew(pri, prireg);
> + } else
> + pr_warn_once("%s: undefined IPR in irq %d\n", __FILE__, irq);
Lacks brackets on the else clause.
> +}
> +
> +static void sh7751_disable_irq(struct irq_data *data)
> +{
> + unsigned int irq = data->irq;
> + struct sh7751_intc_priv *priv = data->chip_data;
> +
> + if (irq < 16 && !priv->irlm) {
> + /* IRL encoded externel interrupt */
external
> + /* disable for SR.IMASK */
> + clear_bit(irq, imask_mask);
> + if (interrupt_priority < IMASK_PRIORITY - irq)
> + interrupt_priority = IMASK_PRIORITY - irq;
> + set_interrupt_registers(interrupt_priority);
> + } else
> + /* Internal periphreal interrupt */
peripheral and missing brackets.
> + /* IPR priority is 0 */
> + update_ipr(priv, irq, 0);
> +}
> +
> +static void sh7751_enable_irq(struct irq_data *data)
> +{
> + unsigned int irq = data->irq;
> + struct sh7751_intc_priv *priv = data->chip_data;
> +
> + if (irq < 16 && !priv->irlm) {
> + set_bit(irq, imask_mask);
> + interrupt_priority = IMASK_PRIORITY -
> + find_first_bit(imask_mask, IMASK_PRIORITY);
> + set_interrupt_registers(interrupt_priority);
> + } else
> + update_ipr(priv, irq, 1);
This does a bsearch on every mask/unmask operation. Why can't this be
done once at setup time and cached per interrupt?
This code lacks any form of comment and explanation what all of this is
about. You are not only leaving reviewers and casual readers puzzled,
you yourself will have a hard time understanding this magic 6 month down
the road.
> +}
> +
> +static const struct irq_chip sh7751_irq_chip = {
> + .name = "SH7751-INTC",
> + .irq_unmask = sh7751_enable_irq,
> + .irq_mask = sh7751_disable_irq,
> +};
> +
> +static int irq_sh7751_map(struct irq_domain *h, unsigned int virq,
> + irq_hw_number_t hw_irq_num)
Argument alignment please.
> +{
> + irq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq);
> + irq_get_irq_data(virq)->chip_data = h->host_data;
> + irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
> + return 0;
> +}
Newline.
> +static const struct irq_domain_ops irq_ops = {
> + .map = irq_sh7751_map,
> + .xlate = irq_domain_xlate_onecell,
Struct formatting
> +};
> +
> +static int sort_ipr_cmp(const void *a, const void *b)
> +{
> + unsigned int irq_a = ((struct iprmap *)a)->irq;
> + unsigned int irq_b = ((struct iprmap *)b)->irq;
> +
> + return irq_a - irq_b;
Why are irq_a/b unsigned int? The substraction clearly hints signed, no?
> +}
> +
> +static void sort_ipr_swap(void *a, void *b, int sz)
> +{
> + struct iprmap tmp;
> +
> + memcpy(&tmp, a, sizeof(tmp));
> + memcpy(a, b, sizeof(tmp));
> + memcpy(b, &tmp, sizeof(tmp));
> +}
> +
> +static int __init load_ipr_map(struct device_node *intc,
> + struct sh7751_intc_priv *priv)
> +{
> + int num_ipr;
> + struct iprmap *p;
> + u32 val[3];
> + unsigned int i, idx;
> +
> + num_ipr = of_property_count_elems_of_size(intc, "renesas,ipr-map", sizeof(u32) * 3);
> + if (num_ipr < 0)
> + return num_ipr;
> +
> + priv->iprmap = kcalloc(num_ipr, sizeof(struct iprmap), GFP_KERNEL);
> + if (priv->iprmap == NULL) {
> + pr_err("%s: Failed to alloc memory\n", intc->name);
> + return -ENOMEM;
> + }
> + priv->num_ipr = num_ipr;
> +
> + for (p = priv->iprmap, idx = 0; num_ipr > 0; p++, num_ipr--) {
> + for (i = 0; i < 3; idx++, i++) {
> + if (of_property_read_u32_index(intc, "renesas,ipr-map",
> + idx, &val[i])) {
> + pr_err("%s: Failed to load ipr-map\n", intc->name);
> + kfree(priv->iprmap);
> + return -EINVAL;
> + }
> + }
> + p->irq = evt2irq(val[0]);
> + p->reg = val[1];
> + p->bits = val[2];
> + }
> + /* This table will be searched using bsearch, so sort it. */
So this is one of the rare comments in this code. It comments the
obvious as the other comments do too.
Thanks,
tglx
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers.
2023-10-18 8:02 ` Thomas Gleixner
@ 2023-10-18 8:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 8:18 UTC (permalink / raw)
To: Thomas Gleixner; +Cc: Yoshinori Sato, linux-sh, glaubitz, maz
On Wed, Oct 18, 2023 at 10:02 AM Thomas Gleixner <tglx@linutronix.de> wrote:
> On Sat, Oct 14 2023 at 23:53, Yoshinori Sato wrote:
> > +config RENESAS_SH7751_INTC
> > + bool "Renesas SH7751 Interrupt Controller"
> > + depends on SH_DEVICE_TREE || COMPILE_TEST
> > +static inline void set_interrupt_registers(int ip)
> > +{
> > + unsigned long __dummy;
> > +
> > + asm volatile(
> > +#ifdef CONFIG_CPU_HAS_SR_RB
> > + "ldc %2, r6_bank\n\t"
> > +#endif
> > + "stc sr, %0\n\t"
> > + "and #0xf0, %0\n\t"
> > + "shlr2 %0\n\t"
> > + "cmp/eq #0x3c, %0\n\t"
> > + "bt/s 1f ! CLI-ed\n\t"
> > + " stc sr, %0\n\t"
> > + "and %1, %0\n\t"
> > + "or %2, %0\n\t"
> > + "ldc %0, sr\n"
> > + "1:"
> > + : "=&z" (__dummy)
> > + : "r" (~0xf0), "r" (ip << 4)
> > + : "t");
>
> Why has this to be ASM and cannot be done in C with the existing
> accessors? Also this really lacks a comment what this is actually doing.
This will play not very well with the "|| COMPILE_TEST" ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (13 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 14/35] drivers/irqchip: Add SH7751 Internal INTC drivers Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-19 11:29 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
` (20 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, tglx, maz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
SH7751 interrupt controller binding definition.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../renesas,sh7751-intc.yaml | 102 ++++++++++++++++++
1 file changed, 102 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index 000000000000..02cc8e73eaf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+properties:
+ compatible:
+ items:
+ - const: renesas,sh7751-intc
+
+ '#interrupt-cells':
+ # an interrupt index and flags, as defined in interrupts.txt in
+ # this directory
+ const: 2
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: ICR
+ - const: INTPRI00
+
+ renesas,icr-irlm:
+ type: boolean
+ description: Use ICR.IRLM=1
+
+ renesas,ipr-map:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ IRQ to IPR mapping definition.
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+ - reg
+ - reg-names
+ - renesas,ipr-map
+
+additionalProperties: false
+
+examples:
+ - |
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ renesas,ipr-map = IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
+ IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
+ IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
+ IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
+ IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
+ IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
+ IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
+ IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
+ IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
+ IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
+ IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
+ IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
+ IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
+ IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
+ IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
+ IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
+ IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
+ IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
+ IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
+ IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
+ IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
+ IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
+ IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
+ IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
+ IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
+ IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
+ IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
+ IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
+ IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
+ IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
+ IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
+ IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
+ IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
+ IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
+ IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC CIDMA3 */
+ IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC CIDMA2 */
+ IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
+ IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
+ IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
+ IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
+ IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
+ IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
+ IPRDEF(0xb80, INTPRI00, IPR_B12); /* TMU4 */
+ };
+...
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml
2023-10-14 14:53 ` [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml Yoshinori Sato
@ 2023-10-19 11:29 ` Geert Uytterhoeven
2023-10-19 11:38 ` Geert Uytterhoeven
0 siblings, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 11:29 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, tglx, maz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> SH7751 interrupt controller binding definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH7751 Interrupt Controller
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> + compatible:
> + items:
> + - const: renesas,sh7751-intc
> +
> + '#interrupt-cells':
> + # an interrupt index and flags, as defined in interrupts.txt in
> + # this directory
I think you can drop this comment.
> + const: 2
> +examples:
> + - |
Missing
#include <dt-bindings/interrupt-controller/sh_intc.h>
Please run
make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
to catch such issues before posting.
> + shintc: interrupt-controller@ffd00000 {
Please align this to the "|" above, and use 4 spaces for each additional
indentation step.
> + compatible = "renesas,sh7751-intc";
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml
2023-10-19 11:29 ` Geert Uytterhoeven
@ 2023-10-19 11:38 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 11:38 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, tglx, maz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Hi Sato-san,
On Thu, Oct 19, 2023 at 1:29 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > SH7751 interrupt controller binding definition.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
> > @@ -0,0 +1,102 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SH7751 Interrupt Controller
> > +
> > +maintainers:
> > + - Yoshinori Sato <ysato@users.sourceforge.jp>
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: renesas,sh7751-intc
> > +
> > + '#interrupt-cells':
> > + # an interrupt index and flags, as defined in interrupts.txt in
> > + # this directory
>
> I think you can drop this comment.
>
> > + const: 2
And given the second cell is always zero, and the driver uses
irq_domain_xlate_onecell, I guess this should be one instead?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (14 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 15/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-intc.yaml Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-16 18:46 ` Thomas Gleixner
2023-10-14 14:53 ` [RFC PATCH v3 17/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-irl-ext.yaml Yoshinori Sato
` (19 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz, tglx, maz
SH7751 have 15 level external interrupt.
It is typically connected to the CPU through a priority encoder
that can suppress requests.
This driver provides a way to control those hardware with irqchip.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/irqchip/Kconfig | 7 +
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-renesas-sh7751irl.c | 206 ++++++++++++++++++++++++
3 files changed, 215 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-sh7751irl.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 87bd490fec21..998c99c2c8ee 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
Support for the Renesas SH7751 On-chip interrupt controller.
And external interrupt encoder for some targets.
+config RENESAS_SH7751IRL_INTC
+ bool "Renesas SH7751 based target IRL encoder support."
+ depends on RENESAS_SH7751_INTC
+ help
+ Support for External Interrupt encoder
+ on the some Renesas SH7751 based target.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 26c91d075e25..91df16726b1f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -121,3 +121,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
+obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o
+
diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c b/drivers/irqchip/irq-renesas-sh7751irl.c
new file mode 100644
index 000000000000..1520d0cfda1e
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751irl.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SH7751 based board IRL encoder driver
+ * (Renesas RTS7751R2D / IO DATA DEVICE LANDISK, USL-5P)
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define NUM_IRQ 15
+#define EXTIRQ_BASE 16
+
+struct sh7751irl_intc_priv {
+ void __iomem *base;
+ struct irq_domain *irq_domain;
+ int width;
+ int type;
+ int nr_irq;
+ u32 enable_map[NUM_IRQ];
+};
+
+enum {type_enable, type_mask};
+
+static inline u32 get_reg(void *addr, int w)
+{
+ switch (w) {
+ case 8:
+ return __raw_readb(addr);
+ case 16:
+ return __raw_readw(addr);
+ case 32:
+ return __raw_readl(addr);
+ }
+ return 0;
+}
+
+static inline void set_reg(void *addr, int w, u32 val)
+{
+ switch (w) {
+ case 8:
+ __raw_writeb(val, addr);
+ break;
+ case 16:
+ __raw_writew(val, addr);
+ break;
+ case 32:
+ __raw_writel(val, addr);
+ break;
+ }
+}
+
+static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data *data)
+{
+ return data->domain->host_data;
+}
+
+static inline u32 set_reset_bit(int val, u32 in, int bit, int type)
+{
+ val &= 1;
+ if (type == type_mask)
+ val ^= 1;
+ in &= ~(1 << bit);
+ return in | (val << bit);
+}
+
+static inline void mask_unmask(struct irq_data *data, int en)
+{
+ struct sh7751irl_intc_priv *priv = irq_data_to_priv(data);
+ int irq = data->irq - EXTIRQ_BASE;
+ u32 val;
+
+ if (priv->nr_irq > irq && priv->enable_map[irq] < priv->width) {
+ val = get_reg(priv->base, priv->width);
+ val = set_reset_bit(en, val, priv->enable_map[irq], priv->type);
+ set_reg(priv->base, priv->width, val);
+ }
+}
+
+static void sh7751irl_intc_mask_irq(struct irq_data *data)
+{
+ mask_unmask(data, 0);
+}
+
+static void sh7751irl_intc_unmask_irq(struct irq_data *data)
+{
+ mask_unmask(data, 1);
+}
+
+static struct irq_chip sh7751irl_intc_chip = {
+ .name = "SH7751IRL-INTC",
+ .irq_unmask = sh7751irl_intc_unmask_irq,
+ .irq_mask = sh7751irl_intc_mask_irq,
+};
+
+static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+
+static int sh7751irl_intc_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec, unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (fwspec->param[0] >= NUM_IRQ)
+ return -EINVAL;
+
+ switch (fwspec->param_count) {
+ case 2:
+ *type = fwspec->param[1];
+ fallthrough;
+ case 1:
+ *hwirq = fwspec->param[0] + EXTIRQ_BASE;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct irq_domain_ops sh7751irl_intc_domain_ops = {
+ .map = sh7751irl_intc_map,
+ .translate = sh7751irl_intc_translate,
+};
+
+static int sh7751irl_init(struct device_node *node, struct device_node *parent)
+{
+ struct sh7751irl_intc_priv *priv;
+ struct irq_domain *d;
+ int ret = 0;
+ int type = -1;
+ u32 *p;
+ unsigned int i, nr_input = 0;
+ const char *type_str;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = of_iomap(node, 0);
+ if (IS_ERR(priv->base)) {
+ ret = PTR_ERR(priv->base);
+ goto error;
+ }
+ of_property_read_u32(node, "renesas,width", &priv->width);
+ if (priv->width != 8 && priv->width != 16 && priv->width != 32) {
+ pr_err("%s Invalid register width.\n", node->name);
+ ret = -EINVAL;
+ goto error;
+ }
+ if (!of_property_read_string(node, "renesas,regtype", &type_str)) {
+ if (strcasecmp("enable", type_str) == 0)
+ type = type_enable;
+ else if (strcasecmp("mask", type_str) == 0)
+ type = type_mask;
+ }
+ if (type < 0) {
+ pr_err("%pOFP: renesas,regtype Invalid register type (%s).\n", node, type_str);
+ ret = -EINVAL;
+ goto error;
+ }
+ priv->type = type;
+
+ priv->nr_irq = of_property_count_u32_elems(node, "renesas,irqbit");
+ if (priv->nr_irq < NUM_IRQ) {
+ of_property_read_u32_array(node, "renesas,irqbit", priv->enable_map, priv->nr_irq);
+ for (p = priv->enable_map, i = 0; i < priv->nr_irq; p++, i++) {
+ if (*p != 0xffffffff)
+ nr_input++;
+ }
+ }
+ if (priv->nr_irq <= 0 || priv->nr_irq >= NUM_IRQ || nr_input > priv->width) {
+ pr_err("%pOFP: renesas,irqbit Invalid register definition.\n", node);
+ ret = -EINVAL;
+ goto error;
+ }
+ d = irq_domain_add_tree(node, &sh7751irl_intc_domain_ops, priv);
+ if (d == NULL) {
+ pr_err("%pOFP: cannot initialize irq domain\n", node);
+ ret = -ENOMEM;
+ goto error;
+ }
+ priv->irq_domain = d;
+ irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED);
+ pr_info("%pOFP: SH7751 External Interrupt encoder (input=%d)", node, nr_input);
+ return 0;
+error:
+ kfree(priv);
+ return ret;
+}
+
+IRQCHIP_DECLARE(renesas_sh7751_irl, "renesas,sh7751-irl-ext", sh7751irl_init);
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-10-14 14:53 ` [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
@ 2023-10-16 18:46 ` Thomas Gleixner
2023-10-16 18:50 ` John Paul Adrian Glaubitz
0 siblings, 1 reply; 88+ messages in thread
From: Thomas Gleixner @ 2023-10-16 18:46 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh; +Cc: Yoshinori Sato, glaubitz, maz
Yoshinori!
On Sat, Oct 14 2023 at 23:53, Yoshinori Sato wrote:
Please Cc LKML on irqchip patches as that's the proper list according to
MAINTAINERS. Due to that I don't have the cover letter and ...
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
> Support for the Renesas SH7751 On-chip interrupt controller.
> And external interrupt encoder for some targets.
... I have no idea against which tree this is supposed to apply. None of
the trees I usually use has the above. So I assume it's a patch in the
same series, but what do I know.
> +config RENESAS_SH7751IRL_INTC
> + bool "Renesas SH7751 based target IRL encoder support."
> + depends on RENESAS_SH7751_INTC
> + help
> + Support for External Interrupt encoder
> + on the some Renesas SH7751 based target.
> +
> endmenu
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 26c91d075e25..91df16726b1f 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -121,3 +121,5 @@ obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
> obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
> obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
> obj-$(CONFIG_RENESAS_SH7751_INTC) += irq-renesas-sh7751.o
> +obj-$(CONFIG_RENESAS_SH7751IRL_INTC) += irq-renesas-sh7751irl.o
> +
> diff --git a/drivers/irqchip/irq-renesas-sh7751irl.c b/drivers/irqchip/irq-renesas-sh7751irl.c
> new file mode 100644
> index 000000000000..1520d0cfda1e
> --- /dev/null
> +++ b/drivers/irqchip/irq-renesas-sh7751irl.c
> @@ -0,0 +1,206 @@
> +// SPDX-License-Identifier: GPL-2.0
GPL-2.0-only please
> +struct sh7751irl_intc_priv {
> + void __iomem *base;
> + struct irq_domain *irq_domain;
> + int width;
> + int type;
> + int nr_irq;
> + u32 enable_map[NUM_IRQ];
> +};
Please use proper tabular alignment for struct definitions. See:
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers
> +enum {type_enable, type_mask};
What's this? A true/false replacement? If you want you own constants,
then please make them upper case.
> +static inline u32 get_reg(void *addr, int w)
> +{
> + switch (w) {
> + case 8:
> + return __raw_readb(addr);
> + case 16:
> + return __raw_readw(addr);
> + case 32:
> + return __raw_readl(addr);
> + }
> + return 0;
Reaching this is a bug, no?
> +}
> +
> +static inline void set_reg(void *addr, int w, u32 val)
> +{
> + switch (w) {
> + case 8:
> + __raw_writeb(val, addr);
> + break;
> + case 16:
> + __raw_writew(val, addr);
> + break;
> + case 32:
> + __raw_writel(val, addr);
> + break;
> + }
> +}
> +
> +static inline struct sh7751irl_intc_priv *irq_data_to_priv(struct irq_data *data)
> +{
> + return data->domain->host_data;
So in sh7751irl_intc_map() you store host_data in chip_data and now you
retrieve it from the domain...
> +}
> +
> +static inline u32 set_reset_bit(int val, u32 in, int bit, int type)
> +{
> + val &= 1;
> + if (type == type_mask)
> + val ^= 1;
> + in &= ~(1 << bit);
> + return in | (val << bit);
This is horrible to read, really.
First of all mixing int (val) and u32 (in) for the OR operation is plain
wrong.
Here the 'type_mask' really threw me off as it's completely non-obvious
that type_mask is an enum constant, which means 'type' should be type of
the very same enum as well, but as you made the enum anonymous that does
not work.
So let me go through this in detail:
> + val &= 1;
What's this for? Making sure that the caller does not provide anything
else than 1 or 0? So any even number is equivalent to 0 and any odd
number equivalent to 1, right? How is that supposed to work correctly?
> + if (type == type_mask)
> + val ^= 1;
So 'type_mask' if set inverts 'val', right? So why is it named mask?
That's confusing at best.
> + in &= ~(1 << bit);
Again you are mixing signed and unsigned values. Also please use
BIT(bit).
> + return in | (val << bit);
This whole thing boils down to:
static inline u32 set_reset_bit(u32 regval, int bit, bool set, bool invert)
{
if (set ^ invert)
return regval | BIT(bit);
return regval & ~BIT(bit);
}
No?
> +}
> +
> +static inline void mask_unmask(struct irq_data *data, int en)
s/en/bool enable/
> +{
> + struct sh7751irl_intc_priv *priv = irq_data_to_priv(data);
> + int irq = data->irq - EXTIRQ_BASE;
What guarantees that the Linux interrupt number is exactly EXTIRQ_BASE +
offset? Linux interrupt numbers are not guaranteed to be linear or
consecutive, unless the underlying interrupt domain is declared that
way, which the tree domain is definitely not.
The proper way to map the interrupt to an hardware offset is the
hardware interrupt number, i.e. irqd_to_hwirq(data). That number is set
when the interrupt is mapped and this avoids the whole EXTIRQ_BASE magic
completely.
> + u32 val;
> +
> + if (priv->nr_irq > irq && priv->enable_map[irq] < priv->width) {
How can you end up with an invalid interrupt number or with an invalid
width here? I'm all for defensive programming, but this is just
unexplainable. The whole point of interrupt domains and their associated
interrupt chips is that irq_data contains the correct information which is
required to handle these things efficiently.
> + val = get_reg(priv->base, priv->width);
> + val = set_reset_bit(en, val, priv->enable_map[irq], priv->type);
So as this is the only place which uses this magic set_reset_bit()
inline, you can just inline it directly and make the code readable. All
of this can be condensed into:
struct sh7751irl_intc_priv *priv = irq_data_to_priv(data);
u32 msk = BIT(priv->enable_map[irqd_to_hwirq(data)]);
val = get_reg(priv->base, priv->width) & ~msk;
if (enable ^ priv->invert)
val |= msk;
set_reg(priv->base, priv->width, val);
Hmm?
> +static int sh7751irl_intc_map(struct irq_domain *h, unsigned int virq,
> + irq_hw_number_t hw_irq_num)
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#line-breaks
> +{
> + irq_set_chip_and_handler(virq, &sh7751irl_intc_chip, handle_level_irq);
> + irq_get_irq_data(virq)->chip_data = h->host_data;
irq_set_chip_data(...) if at all
> + irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
> + return 0;
> +}
> +
> +static int sh7751irl_intc_translate(struct irq_domain *domain,
> + struct irq_fwspec *fwspec, unsigned long *hwirq,
> + unsigned int *type)
Same comment vs. line breaks
> +{
> + if (fwspec->param[0] >= NUM_IRQ)
> + return -EINVAL;
> +
> + switch (fwspec->param_count) {
> + case 2:
> + *type = fwspec->param[1];
> + fallthrough;
> + case 1:
> + *hwirq = fwspec->param[0] + EXTIRQ_BASE;
So if you store fwspec->param[0] in hwirq then the above code just works
by reading hwirq, no?
> + break;
> + default:
> + return -EINVAL;
> + }
> + return 0;
> +}
> +
> +static const struct irq_domain_ops sh7751irl_intc_domain_ops = {
> + .map = sh7751irl_intc_map,
> + .translate = sh7751irl_intc_translate,
See the struct initializer documentation...
> +};
> +
> +static int sh7751irl_init(struct device_node *node, struct device_node *parent)
> +{
> + struct sh7751irl_intc_priv *priv;
> + struct irq_domain *d;
> + int ret = 0;
> + int type = -1;
> + u32 *p;
> + unsigned int i, nr_input = 0;
> + const char *type_str;
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-declarations
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->base = of_iomap(node, 0);
> + if (IS_ERR(priv->base)) {
> + ret = PTR_ERR(priv->base);
> + goto error;
> + }
Missing newline. Same on lots of places below. Please use empty newlines
to structure the code so that the individual functional blocks are easy
to identify.
> + of_property_read_u32(node, "renesas,width", &priv->width);
> + if (priv->width != 8 && priv->width != 16 && priv->width != 32) {
> + pr_err("%s Invalid register width.\n", node->name);
> + ret = -EINVAL;
> + goto error;
> + }
> + if (!of_property_read_string(node, "renesas,regtype", &type_str)) {
> + if (strcasecmp("enable", type_str) == 0)
> + type = type_enable;
> + else if (strcasecmp("mask", type_str) == 0)
> + type = type_mask;
> + }
I'm not convinced about this "enable" "mask" wording here. As I said
above this indicates whether the register bits are inverted or not.
> + if (type < 0) {
> + pr_err("%pOFP: renesas,regtype Invalid register type (%s).\n", node, type_str);
> + ret = -EINVAL;
> + goto error;
> + }
> + priv->type = type;
Please make this simply a boolean value and be done with it.
> + priv->nr_irq = of_property_count_u32_elems(node, "renesas,irqbit");
> + if (priv->nr_irq < NUM_IRQ) {
> + of_property_read_u32_array(node, "renesas,irqbit", priv->enable_map, priv->nr_irq);
> + for (p = priv->enable_map, i = 0; i < priv->nr_irq; p++, i++) {
> + if (*p != 0xffffffff)
Please use a proper define and not magic constants.
> + nr_input++;
> + }
> + }
> + if (priv->nr_irq <= 0 || priv->nr_irq >= NUM_IRQ || nr_input > priv->width) {
We usually assume that NUM_IRQ[S] is the number of interrupts which can
be handled by a domain/interrupt chip. But you require that the number
of irqbits defined in the device tree is less than NUM_IRQ which is
confusing at best. I really had to read these conditions three times to
understand the logic here.
Also nr_input > priv->width is wrong if there are enough entries with an
enable map of 0xFFFFFFFF so that nr_input is <= priv->width.
Aside of that what checks that the bit number provided in enable_map is
actually valid vs. priv->width? AFACIT, nothing. That's why you need
magic checks in your mask/unmask function. Ensure correctness at setup
time and not with magic checks at runtime.
> + pr_err("%pOFP: renesas,irqbit Invalid register definition.\n", node);
> + ret = -EINVAL;
> + goto error;
> + }
> + d = irq_domain_add_tree(node, &sh7751irl_intc_domain_ops, priv);
Why is this a tree when the number of hardware interrupts is fixed?
irq_domain_add_linear() is the right thing to use here.
> + if (d == NULL) {
if (!d) {
> + pr_err("%pOFP: cannot initialize irq domain\n", node);
> + ret = -ENOMEM;
> + goto error;
> + }
> + priv->irq_domain = d;
What's the purpose of storing the domain pointer here? Nothing,
AFAICT.
Thanks,
tglx
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-10-16 18:46 ` Thomas Gleixner
@ 2023-10-16 18:50 ` John Paul Adrian Glaubitz
2023-10-16 21:55 ` Thomas Gleixner
0 siblings, 1 reply; 88+ messages in thread
From: John Paul Adrian Glaubitz @ 2023-10-16 18:50 UTC (permalink / raw)
To: Thomas Gleixner, Yoshinori Sato, linux-sh; +Cc: maz
Hi Thomas!
Thanks for the thorough review. Just a quick comment below.
On Mon, 2023-10-16 at 20:46 +0200, Thomas Gleixner wrote:
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
> > Support for the Renesas SH7751 On-chip interrupt controller.
> > And external interrupt encoder for some targets.
>
> ... I have no idea against which tree this is supposed to apply. None of
> the trees I usually use has the above. So I assume it's a patch in the
> same series, but what do I know.
This shall eventually go through my sh-linux tree [1].
Adrian
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux.git/
--
.''`. John Paul Adrian Glaubitz
: :' : Debian Developer
`. `' Physicist
`- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-10-16 18:50 ` John Paul Adrian Glaubitz
@ 2023-10-16 21:55 ` Thomas Gleixner
2023-10-17 16:33 ` Thomas Gleixner
0 siblings, 1 reply; 88+ messages in thread
From: Thomas Gleixner @ 2023-10-16 21:55 UTC (permalink / raw)
To: John Paul Adrian Glaubitz, Yoshinori Sato, linux-sh; +Cc: maz
On Mon, Oct 16 2023 at 20:50, John Paul Adrian Glaubitz wrote:
> On Mon, 2023-10-16 at 20:46 +0200, Thomas Gleixner wrote:
>> > --- a/drivers/irqchip/Kconfig
>> > +++ b/drivers/irqchip/Kconfig
>> > @@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
>> > Support for the Renesas SH7751 On-chip interrupt controller.
>> > And external interrupt encoder for some targets.
>>
>> ... I have no idea against which tree this is supposed to apply. None of
>> the trees I usually use has the above. So I assume it's a patch in the
>> same series, but what do I know.
>
> This shall eventually go through my sh-linux tree [1].
That's an actual tree management problem, which is completely
independent of the review process.
Reviewing patches which depend on "unknown" other changes is per
definition impossible and in this case it's even worse because the
dependency affects the same subsystem, no?
Thanks,
tglx
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate.
2023-10-16 21:55 ` Thomas Gleixner
@ 2023-10-17 16:33 ` Thomas Gleixner
0 siblings, 0 replies; 88+ messages in thread
From: Thomas Gleixner @ 2023-10-17 16:33 UTC (permalink / raw)
To: John Paul Adrian Glaubitz, Yoshinori Sato, linux-sh; +Cc: maz
On Mon, Oct 16 2023 at 23:55, Thomas Gleixner wrote:
> On Mon, Oct 16 2023 at 20:50, John Paul Adrian Glaubitz wrote:
>> On Mon, 2023-10-16 at 20:46 +0200, Thomas Gleixner wrote:
>>> > --- a/drivers/irqchip/Kconfig
>>> > +++ b/drivers/irqchip/Kconfig
>>> > @@ -688,4 +688,11 @@ config RENESAS_SH7751_INTC
>>> > Support for the Renesas SH7751 On-chip interrupt controller.
>>> > And external interrupt encoder for some targets.
>>>
>>> ... I have no idea against which tree this is supposed to apply. None of
>>> the trees I usually use has the above. So I assume it's a patch in the
>>> same series, but what do I know.
>>
>> This shall eventually go through my sh-linux tree [1].
>
> That's an actual tree management problem, which is completely
> independent of the review process.
>
> Reviewing patches which depend on "unknown" other changes is per
> definition impossible and in this case it's even worse because the
> dependency affects the same subsystem, no?
Never mind. I found the other patch. For some reason that ended up with
broken threading, but I definitely do not have the cover letter.
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 17/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-irl-ext.yaml
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (15 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 16/35] drivers/irqchip: SH7751 IRL external encoder with enable gate Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 18/35] drivers/tty/serial: sh-sci.c fix SH4 OF support Yoshinori Sato
` (18 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, tglx, maz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
SH7751 external interrupt encoder binding definition.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../renesas,sh7751-irl-ext.yaml | 89 +++++++++++++++++++
1 file changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
new file mode 100644
index 000000000000..323229ccc4c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-irl-ext.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-irl-ext.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 IRL external encoder with enable regs.
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description: |
+ This is the generally used external interrupt encoder on SH7751 based boards.
+
+properties:
+ compatible:
+ items:
+ - const: renesas,sh7751-irl-ext
+
+ reg:
+ minItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ '#size-cells':
+ const: 0
+
+ renesas,width:
+ description: Enable register width
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ renesas,regtype:
+ description: Enable register type
+ $ref: /schemas/types.yaml#/definitions/string
+ oneOf:
+ - description:
+ 1 is interrupt enable / 0 is interrupt disable.
+ const: enable
+ - description:
+ 1 is interrupt mask / 0 is interrupt unmask.
+ const: mask
+
+ renesas,irqbit:
+ description: IRQ to enable register bit mapping
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+ - renesas,width
+ - renesas,regtype
+ - renesas,irqbit
+
+additionalProperties: false
+
+examples:
+ - |
+ r2dintc: sh7751irl_encoder@a4000000 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xa4000000 0x02>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ renesas,width = <16>;
+ renesas,regtype = "enable";
+ renesas,irqbit = <11>, /* PCI INTD */
+ <9>, /* CF IDE */
+ <8>, /* CF CD */
+ <12>, /* PCI INTC */
+ <10>, /* SM501 */
+ <6>, /* KEY */
+ <5>, /* RTC ALARM */
+ <4>, /* RTC T */
+ <7>, /* SDCARD */
+ <14>, /* PCI INTA */
+ <13>, /* PCI INTB */
+ <0>, /* EXT */
+ <15>; /* TP */
+ };
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 18/35] drivers/tty/serial: sh-sci.c fix SH4 OF support.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (16 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 17/35] Documentation/devicetree/bindings/interrupt-controller: Add renesas,sh7751-irl-ext.yaml Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 8:23 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 19/35] Documentation/devicetree/bindings/serial: renesas,scif.yaml Add SH Yoshinori Sato
` (17 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
- fix earlycon name.
- fix earlyprintk hung (NULL pointer reference).
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/tty/serial/sh-sci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index a560b729fa3b..faaf2bb32586 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2720,7 +2720,7 @@ static int sci_remap_port(struct uart_port *port)
if (port->membase)
return 0;
- if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
+ if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -3555,8 +3555,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r7s9210", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscifa, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 18/35] drivers/tty/serial: sh-sci.c fix SH4 OF support.
2023-10-14 14:53 ` [RFC PATCH v3 18/35] drivers/tty/serial: sh-sci.c fix SH4 OF support Yoshinori Sato
@ 2023-10-18 8:23 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 8:23 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
Thanks for your patch!
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> - fix earlycon name.
Note that to use earlycon, you currently need to enable EXPERT.
So I propose to fix that using:
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -658,7 +658,7 @@ config SERIAL_SH_SCI_EARLYCON
depends on SERIAL_SH_SCI=y
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
- default ARCH_RENESAS
+ default ARCH_RENESAS || SUPERH
config SERIAL_SH_SCI_DMA
bool "DMA support" if EXPERT
> - fix earlyprintk hung (NULL pointer reference).
How do you actually use earlyprintk, as SH lacks the EARLY_PRINTK
config symbol?
Looks like tglx missed that when creating commit d0380e6c3c0f6edb
("early_printk: consolidate random copies of identical code").
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 19/35] Documentation/devicetree/bindings/serial: renesas,scif.yaml Add SH.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (17 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 18/35] drivers/tty/serial: sh-sci.c fix SH4 OF support Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 14:04 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 20/35] drivers/mfd: sm501 add some properties Yoshinori Sato
` (16 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
Documentation/devicetree/bindings/serial/renesas,scif.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 99030fc18c45..0c938f1fb77b 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -81,6 +81,11 @@ properties:
- renesas,scif-r9a07g054 # RZ/V2L
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
+ - items:
+ - enum:
+ - renesas,scif-sh7751 # SH7751
+ - const: renesas,scif # generic SCIF compatible UART
+
reg:
maxItems: 1
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 19/35] Documentation/devicetree/bindings/serial: renesas,scif.yaml Add SH.
2023-10-14 14:53 ` [RFC PATCH v3 19/35] Documentation/devicetree/bindings/serial: renesas,scif.yaml Add SH Yoshinori Sato
@ 2023-10-18 14:04 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 14:04 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> @@ -81,6 +81,11 @@ properties:
> - renesas,scif-r9a07g054 # RZ/V2L
> - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
>
> + - items:
> + - enum:
> + - renesas,scif-sh7751 # SH7751
> + - const: renesas,scif # generic SCIF compatible UART
There is no need to add a new "items" section.
Just add "renesas,scif-sh7751" to the first "items" section at the top.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 20/35] drivers/mfd: sm501 add some properties.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (18 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 19/35] Documentation/devicetree/bindings/serial: renesas,scif.yaml Add SH Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-19 11:55 ` Lee Jones
2023-10-14 14:53 ` [RFC PATCH v3 21/35] devicetree/binding/display/sm501fb.txt: sm501fb add properies Yoshinori Sato
` (15 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, lee, deller, tzimmermann, sam, robh,
zhangxuezhi1, u.kleine-koenig
I am changing the target board of SuperH using SM501 to DeviceTree.
This target uses platform_device to configure sm501 and sm501fb.
In order to migrate to DeviceTree, it can now be set in properties.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/mfd/sm501.c | 113 ++++++++++++++++++++++++++++++++++
drivers/video/fbdev/sm501fb.c | 92 +++++++++++++++++++++++++++
2 files changed, 205 insertions(+)
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index 28027982cf69..e0fdb5237d29 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -1370,6 +1370,113 @@ static int sm501_init_dev(struct sm501_devdata *sm)
return 0;
}
+#ifdef CONFIG_OF
+static unsigned int sm501_parse_devices_str(struct device_node *np)
+{
+ unsigned int device = 0;
+ unsigned int i, j;
+ unsigned int nstr;
+ const char *devstr;
+ static const struct {
+ char *devname;
+ unsigned int devid;
+ } devlist[] = {
+ { "usb-host", SM501_USE_USB_HOST },
+ { "usb-gadget", SM501_USE_USB_SLAVE },
+ { "ssp0", SM501_USE_SSP0 },
+ { "ssp1", SM501_USE_SSP1 },
+ { "uart0", SM501_USE_UART0 },
+ { "uart1", SM501_USE_UART1 },
+ { "accel", SM501_USE_FBACCEL },
+ { "ac97", SM501_USE_AC97 },
+ { "i2s", SM501_USE_I2S },
+ { "gpio", SM501_USE_GPIO },
+ { "all", SM501_USE_ALL },
+ };
+
+ nstr = of_property_count_strings(np, "smi,devices");
+ for (i = 0; i < nstr; i++) {
+ if (of_property_read_string_index(np, "smi,devices", i, &devstr))
+ break;
+ for (j = 0; j < ARRAY_SIZE(devlist); j++) {
+ if (strcmp(devstr, devlist[j].devname) == 0) {
+ device |= devlist[j].devid;
+ goto next;
+ }
+ }
+next:
+ }
+ return device;
+}
+
+static void sm501_of_read_reg_init(struct device_node *np,
+ const char *propname, struct sm501_reg_init *val)
+{
+ u32 u32_val[2];
+
+ if (!of_property_read_u32_array(np, propname, u32_val, sizeof(u32_val))) {
+ val->set = u32_val[0];
+ val->mask = u32_val[1];
+ } else {
+ val->set = 0;
+ val->mask = 0;
+ }
+}
+
+static int sm501_parse_dt(struct sm501_devdata *sm, struct device_node *np)
+{
+ struct sm501_platdata *plat;
+ u32 u32_val;
+
+ plat = devm_kzalloc(sm->dev, sizeof(*plat), GFP_KERNEL);
+ if (!plat)
+ return -ENOMEM;
+
+ plat->init = devm_kzalloc(sm->dev, sizeof(*plat->init), GFP_KERNEL);
+ if (!plat->init)
+ return -ENOMEM;
+
+ plat->init->devices = sm501_parse_devices_str(np);
+
+ if (!of_property_read_u32_index(np, "smi,mclk", 0, &u32_val))
+ plat->init->mclk = u32_val;
+ else
+ plat->init->mclk = 0;
+
+ if (!of_property_read_u32_index(np, "smi,m1xclk", 0, &u32_val))
+ plat->init->m1xclk = u32_val;
+ else
+ plat->init->m1xclk = 0;
+
+ sm501_of_read_reg_init(np, "smi,misc-timing", &plat->init->misc_timing);
+ sm501_of_read_reg_init(np, "smi,misc-control", &plat->init->misc_control);
+ sm501_of_read_reg_init(np, "smi,gpio-low", &plat->init->gpio_low);
+ sm501_of_read_reg_init(np, "smi,gpio-high", &plat->init->gpio_high);
+
+#ifdef CONFIG_MFD_SM501_GPIO
+ if (plat->init->devices & SM501_USE_GPIO) {
+ if (!of_property_read_u32_index(np, "smi,num-i2c", 0, &u32_val))
+ plat->gpio_i2c_nr = u32_val;
+ else
+ plat->gpio_i2c_nr = 0;
+ }
+ if (plat->gpio_i2c_nr > 0) {
+ int sz_gpio;
+
+ sz_gpio = sizeof(struct sm501_platdata_gpio_i2c) * plat->gpio_i2c_nr;
+ plat->gpio_i2c = devm_kzalloc(sm->dev, sz_gpio, GFP_KERNEL);
+ if (plat->gpio_i2c == NULL)
+ return -ENOMEM;
+
+ of_property_read_variable_u32(np, "smi,gpio-i2c",
+ plat->gpio_i2c, plat->gpio_i2c_nr * 5);
+ }
+#endif /* CONFIG_MFD_SM501_GPIO */
+ sm->platdata = plat;
+ return 0;
+}
+#endif /* CONFIG_OF */
+
static int sm501_plat_probe(struct platform_device *dev)
{
struct sm501_devdata *sm;
@@ -1406,6 +1513,12 @@ static int sm501_plat_probe(struct platform_device *dev)
goto err_res;
}
+ if (IS_ENABLED(CONFIG_OF) && dev->dev.of_node) {
+ ret = sm501_parse_dt(sm, dev->dev.of_node);
+ if (ret)
+ goto err_res;
+ }
+
platform_set_drvdata(dev, sm);
sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
diff --git a/drivers/video/fbdev/sm501fb.c b/drivers/video/fbdev/sm501fb.c
index 65c799ac5604..d42f8a15e4ba 100644
--- a/drivers/video/fbdev/sm501fb.c
+++ b/drivers/video/fbdev/sm501fb.c
@@ -1928,6 +1928,82 @@ static int sm501fb_start_one(struct sm501fb_info *info,
return 0;
}
+#if defined(CONFIG_OF)
+static struct sm501_platdata_fbsub *read_fbsub(struct device_node *np, const char *ch_name)
+{
+ struct device_node *child;
+ struct sm501_platdata_fbsub *fbsub = NULL;
+ struct fb_videomode *def_mode;
+ u32 bpp;
+ u32 max_mem;
+ u32 flags = 0;
+ static const char * const flag_str[] = {
+ "use_init_mode",
+ "disable_at_exit",
+ "use_hwcursor",
+ "use_hwaccel",
+ "panel_no_fpen",
+ "panel_no_vbiasen",
+ "panel_inv_fpen",
+ "panel_inv_vbiasen",
+ };
+ const char *flag_value;
+ const char *prop;
+ int nr_flags;
+ int i, j;
+ int len;
+
+ child = of_get_child_by_name(np, ch_name);
+ if (child == NULL)
+ return NULL;
+
+ prop = of_get_property(child, "edid", &len);
+ if (prop && len == EDID_LENGTH) {
+ struct fb_monspecs *specs;
+ u8 *edid;
+
+ edid = kmemdup(prop, EDID_LENGTH, GFP_KERNEL);
+ if (edid) {
+ specs = kzalloc(sizeof(*specs), GFP_KERNEL);
+ if (specs) {
+ fb_edid_to_monspecs(edid, specs);
+ def_mode = specs->modedb;
+ }
+ kfree(specs);
+ }
+ kfree(edid);
+ }
+
+ if (of_property_read_u32(child, "bpp", &bpp))
+ bpp = 0;
+ if (of_property_read_u32(child, "max-mem", &max_mem))
+ max_mem = 0;
+
+ nr_flags = of_property_count_strings(child, "flags");
+ for (i = 0; i < nr_flags; i++) {
+ if (of_property_read_string_index(child, "flags", i, &flag_value) < 0)
+ break;
+ for (j = 0; j < ARRAY_SIZE(flag_str); j++) {
+ if (strcasecmp(flag_value, flag_str[j]) == 0) {
+ flags |= 1 << j;
+ break;
+ }
+ }
+ }
+
+ if (def_mode || bpp || max_mem || flags) {
+ fbsub = kzalloc(sizeof(*fbsub), GFP_KERNEL);
+ if (fbsub) {
+ fbsub->def_mode = def_mode;
+ fbsub->def_bpp = bpp;
+ fbsub->max_mem = max_mem;
+ fbsub->flags = flags;
+ }
+ }
+ return fbsub;
+}
+#endif
+
static int sm501fb_probe(struct platform_device *pdev)
{
struct sm501fb_info *info;
@@ -1956,6 +2032,7 @@ static int sm501fb_probe(struct platform_device *pdev)
const u8 *prop;
const char *cp;
int len;
+ struct sm501_platdata_fbsub *sub;
info->pdata = &sm501fb_def_pdata;
if (np) {
@@ -1970,6 +2047,21 @@ static int sm501fb_probe(struct platform_device *pdev)
if (info->edid_data)
found = 1;
}
+ cp = of_get_property(np, "route", &len);
+ if (cp) {
+ if (strcasecmp(cp, "own") == 0)
+ info->pdata->fb_route = SM501_FB_OWN;
+ else if (strcasecmp(cp, "crt-panel") == 0)
+ info->pdata->fb_route = SM501_FB_CRT_PANEL;
+ }
+ if (of_property_read_bool(np, "swap-fb-endian"))
+ info->pdata->flags |= SM501_FBPD_SWAP_FB_ENDIAN;
+ sub = read_fbsub(np, "crt");
+ if (sub)
+ info->pdata->fb_crt = sub;
+ sub = read_fbsub(np, "panel");
+ if (sub)
+ info->pdata->fb_pnl = sub;
}
#endif
if (!found) {
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 20/35] drivers/mfd: sm501 add some properties.
2023-10-14 14:53 ` [RFC PATCH v3 20/35] drivers/mfd: sm501 add some properties Yoshinori Sato
@ 2023-10-19 11:55 ` Lee Jones
0 siblings, 0 replies; 88+ messages in thread
From: Lee Jones @ 2023-10-19 11:55 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, deller, tzimmermann, sam, robh, zhangxuezhi1,
u.kleine-koenig
On Sat, 14 Oct 2023, Yoshinori Sato wrote:
> I am changing the target board of SuperH using SM501 to DeviceTree.
> This target uses platform_device to configure sm501 and sm501fb.
> In order to migrate to DeviceTree, it can now be set in properties.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> drivers/mfd/sm501.c | 113 ++++++++++++++++++++++++++++++++++
> drivers/video/fbdev/sm501fb.c | 92 +++++++++++++++++++++++++++
> 2 files changed, 205 insertions(+)
Wow! This is a 20 year old driver. I'm surprised to see it in use.
FYI, the driver itself seems to be in a bit of state. It would not be
accepted in its current guise if submitted in the present.
When you submit your next revision, would you please add me to the
recipients list on the *whole set* please?
Not sure I can review this until the DT guys have rubber stamped the
binding. Some of the proposed properties look like they'll need a
re-work; specifically 'smi,devices' which looks like a bitmap of the
devices to be enabled.
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 21/35] devicetree/binding/display/sm501fb.txt: sm501fb add properies.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (19 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 20/35] drivers/mfd: sm501 add some properties Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-14 14:53 ` [RFC PATCH v3 22/35] drivers/clocksource/sh_tmu: Add support CLOCKSOURCE Yoshinori Sato
` (14 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, lee, deller, tzimmermann, sam, robh,
zhangxuezhi1, u.kleine-koenig
SM501's OF support is not enough parameter in platform device.
This change adds the missing parameter.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../devicetree/bindings/display/sm501fb.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sm501fb.txt b/Documentation/devicetree/bindings/display/sm501fb.txt
index 1c79c267a57f..916b768cb340 100644
--- a/Documentation/devicetree/bindings/display/sm501fb.txt
+++ b/Documentation/devicetree/bindings/display/sm501fb.txt
@@ -20,6 +20,23 @@ Optional properties:
set different foreign endian.
- big-endian: available on little endian systems, to
set different foreign endian.
+- route: Framebuffer output route
+ "own": CRT=>CRT, Panel=>Panel
+ "crt-panel": Panel=>CRT, Panel=>Panel
+- swap-fb-endian: swap framebuffer byteorder
+- crt: CRT output control
+- panel: Panel output control
+- smi,devices: select peripheral functions.
+ available usb-host, usb-gadget, ssp0, ssp,1 uart0, uart1, accel,
+ ac97, i2s, gpio and all.
+- smi,mclk: SM501 mclk frequency.
+- smi,m1xclk: SM501 m1xclk frequency.
+- smi,misc-timing: SM501 Miscellaneous Timing reg value.
+- smi,misc-control: SM501 Miscellaneous Control reg value.
+- smi,gpio-low: SM501 GPIO31-0 Control reg value.
+- smi,gpio-high: SM501 GPIO63-32 Control reg value.
+- smi,num-i2c: I2C channel number.
+- smi,gpio-i2c: I2C assigned GPIO.
Example for MPC5200:
display@1,0 {
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 22/35] drivers/clocksource/sh_tmu: Add support CLOCKSOURCE.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (20 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 21/35] devicetree/binding/display/sm501fb.txt: sm501fb add properies Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 16:04 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 23/35] Documentation/devicetree/bindings/timer: renesas,tmu.yaml add SH Yoshinori Sato
` (13 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Enables registration as a Clocksource in the case of OF.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clocksource/sh_tmu.c | 161 +++++++++++++++++++++++------------
1 file changed, 106 insertions(+), 55 deletions(-)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index beffff81c00f..e4ae83c9f7d4 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -17,6 +17,8 @@
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
@@ -65,6 +67,7 @@ struct sh_tmu_device {
bool has_clockevent;
bool has_clocksource;
+ const char *name;
};
#define TSTR -1 /* shared register */
@@ -148,8 +151,8 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch)
/* enable clock */
ret = clk_enable(ch->tmu->clk);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
- ch->index);
+ pr_err("%s ch%u: cannot enable clock\n",
+ ch->tmu->name, ch->index);
return ret;
}
@@ -174,9 +177,10 @@ static int sh_tmu_enable(struct sh_tmu_channel *ch)
if (ch->enable_count++ > 0)
return 0;
- pm_runtime_get_sync(&ch->tmu->pdev->dev);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
-
+ if (ch->tmu->pdev) {
+ pm_runtime_get_sync(&ch->tmu->pdev->dev);
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
+ }
return __sh_tmu_enable(ch);
}
@@ -202,8 +206,10 @@ static void sh_tmu_disable(struct sh_tmu_channel *ch)
__sh_tmu_disable(ch);
- dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
- pm_runtime_put(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev) {
+ dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
+ pm_runtime_put(&ch->tmu->pdev->dev);
+ }
}
static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
@@ -245,7 +251,7 @@ static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
+static inline struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
{
return container_of(cs, struct sh_tmu_channel, cs);
}
@@ -292,7 +298,8 @@ static void sh_tmu_clocksource_suspend(struct clocksource *cs)
if (--ch->enable_count == 0) {
__sh_tmu_disable(ch);
- dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_suspend(&ch->tmu->pdev->dev);
}
}
@@ -304,7 +311,8 @@ static void sh_tmu_clocksource_resume(struct clocksource *cs)
return;
if (ch->enable_count++ == 0) {
- dev_pm_genpd_resume(&ch->tmu->pdev->dev);
+ if (ch->tmu->pdev)
+ dev_pm_genpd_resume(&ch->tmu->pdev->dev);
__sh_tmu_enable(ch);
}
}
@@ -324,14 +332,14 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
- ch->index);
+ pr_info("%s ch%u: used as clock source\n",
+ ch->tmu->name, ch->index);
clocksource_register_hz(cs, ch->tmu->rate);
return 0;
}
-static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
+static inline struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
{
return container_of(ced, struct sh_tmu_channel, ced);
}
@@ -364,8 +372,8 @@ static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,
if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
sh_tmu_disable(ch);
- dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
- ch->index, periodic ? "periodic" : "oneshot");
+ pr_info("%s ch%u: used for %s clock events\n",
+ ch->tmu->name, ch->index, periodic ? "periodic" : "oneshot");
sh_tmu_clock_event_start(ch, periodic);
return 0;
}
@@ -403,7 +411,8 @@ static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
}
static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
- const char *name)
+ const char *name,
+ struct device_node *np)
{
struct clock_event_device *ced = &ch->ced;
int ret;
@@ -417,30 +426,32 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
ced->set_state_periodic = sh_tmu_clock_event_set_periodic;
ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot;
- ced->suspend = sh_tmu_clock_event_suspend;
- ced->resume = sh_tmu_clock_event_resume;
-
- dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
- ch->index);
+ if (ch->tmu->pdev) {
+ ced->suspend = sh_tmu_clock_event_suspend;
+ ced->resume = sh_tmu_clock_event_resume;
+ }
+ pr_info("%s ch%u: used for clock events\n",
+ ch->tmu->name, ch->index);
clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);
ret = request_irq(ch->irq, sh_tmu_interrupt,
IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
- dev_name(&ch->tmu->pdev->dev), ch);
+ ch->tmu->name, ch);
if (ret) {
- dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
- ch->index, ch->irq);
+ pr_err("%s ch%u: failed to request irq %d\n",
+ ch->tmu->name, ch->index, ch->irq);
return;
}
}
static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
+ struct device_node *np,
bool clockevent, bool clocksource)
{
if (clockevent) {
ch->tmu->has_clockevent = true;
- sh_tmu_register_clockevent(ch, name);
+ sh_tmu_register_clockevent(ch, name, np);
} else if (clocksource) {
ch->tmu->has_clocksource = true;
sh_tmu_register_clocksource(ch, name);
@@ -451,7 +462,8 @@ static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
bool clockevent, bool clocksource,
- struct sh_tmu_device *tmu)
+ struct sh_tmu_device *tmu,
+ struct device_node *np)
{
/* Skip unused channels. */
if (!clockevent && !clocksource)
@@ -465,53 +477,59 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
else
ch->base = tmu->mapbase + 8 + ch->index * 12;
- ch->irq = platform_get_irq(tmu->pdev, index);
+ if (tmu->pdev)
+ ch->irq = platform_get_irq(tmu->pdev, index);
+ else
+ ch->irq = of_irq_get(np, index);
if (ch->irq < 0)
return ch->irq;
ch->cs_enabled = false;
ch->enable_count = 0;
- return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
+ return sh_tmu_register(ch, tmu->name, np,
clockevent, clocksource);
}
-static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
+static int sh_tmu_map_memory(struct sh_tmu_device *tmu, struct device_node *np)
{
struct resource *res;
- res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
- return -ENXIO;
- }
+ if (tmu->pdev) {
+ res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ pr_err("sh_tmu failed to get I/O memory\n");
+ return -ENXIO;
+ }
+
+ tmu->mapbase = ioremap(res->start, resource_size(res));
+ } else
+ tmu->mapbase = of_iomap(np, 0);
- tmu->mapbase = ioremap(res->start, resource_size(res));
if (tmu->mapbase == NULL)
return -ENXIO;
return 0;
}
-static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
+static int sh_tmu_parse_dt(struct sh_tmu_device *tmu, struct device_node *np)
{
- struct device_node *np = tmu->pdev->dev.of_node;
-
tmu->model = SH_TMU;
tmu->num_channels = 3;
of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
if (tmu->num_channels != 2 && tmu->num_channels != 3) {
- dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
- tmu->num_channels);
+ pr_err("%s: invalid number of channels %u\n",
+ tmu->name, tmu->num_channels);
return -EINVAL;
}
return 0;
}
-static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
+static int sh_tmu_setup(struct sh_tmu_device *tmu,
+ struct platform_device *pdev, struct device_node *np)
{
unsigned int i;
int ret;
@@ -520,8 +538,13 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
raw_spin_lock_init(&tmu->lock);
- if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
- ret = sh_tmu_parse_dt(tmu);
+ if (pdev)
+ tmu->name = dev_name(&pdev->dev);
+ else
+ tmu->name = of_node_full_name(np);
+
+ if (IS_ENABLED(CONFIG_OF) && np) {
+ ret = sh_tmu_parse_dt(tmu, np);
if (ret < 0)
return ret;
} else if (pdev->dev.platform_data) {
@@ -531,14 +554,17 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
tmu->model = id->driver_data;
tmu->num_channels = hweight8(cfg->channels_mask);
} else {
- dev_err(&tmu->pdev->dev, "missing platform data\n");
+ pr_err("%s missing platform data\n", tmu->name);
return -ENXIO;
}
/* Get hold of clock. */
- tmu->clk = clk_get(&tmu->pdev->dev, "fck");
+ if (pdev)
+ tmu->clk = clk_get(&tmu->pdev->dev, "fck");
+ else
+ tmu->clk = of_clk_get(np, 0);
if (IS_ERR(tmu->clk)) {
- dev_err(&tmu->pdev->dev, "cannot get clock\n");
+ pr_err("%s: cannot get clock\n", tmu->name);
return PTR_ERR(tmu->clk);
}
@@ -555,9 +581,9 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
clk_disable(tmu->clk);
/* Map the memory resource. */
- ret = sh_tmu_map_memory(tmu);
+ ret = sh_tmu_map_memory(tmu, np);
if (ret < 0) {
- dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
+ pr_err("%s: failed to remap I/O memory\n", tmu->name);
goto err_clk_unprepare;
}
@@ -575,12 +601,12 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
*/
for (i = 0; i < tmu->num_channels; ++i) {
ret = sh_tmu_channel_setup(&tmu->channels[i], i,
- i == 0, i == 1, tmu);
+ i == 0, i == 1, tmu, np);
if (ret < 0)
goto err_unmap;
}
-
- platform_set_drvdata(pdev, tmu);
+ if (pdev)
+ platform_set_drvdata(pdev, tmu);
return 0;
@@ -594,6 +620,7 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
return ret;
}
+#ifndef CONFIG_SH_DEVICE_TREE
static int sh_tmu_probe(struct platform_device *pdev)
{
struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
@@ -613,7 +640,7 @@ static int sh_tmu_probe(struct platform_device *pdev)
if (tmu == NULL)
return -ENOMEM;
- ret = sh_tmu_setup(tmu, pdev);
+ ret = sh_tmu_setup(tmu, pdev, pdev->dev.of_node);
if (ret) {
kfree(tmu);
pm_runtime_idle(&pdev->dev);
@@ -631,7 +658,26 @@ static int sh_tmu_probe(struct platform_device *pdev)
return 0;
}
+#else
+static int __init sh_tmu_of_register(struct device_node *np)
+{
+ struct sh_tmu_device *tmu;
+ int ret;
+
+ tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
+ if (tmu == NULL)
+ return -ENOMEM;
+
+ ret = sh_tmu_setup(tmu, NULL, np);
+ if (ret) {
+ kfree(tmu);
+ pr_warn("%pOF: Timer register failed (%d)", np, ret);
+ }
+ return ret;
+}
+#endif
+#ifndef CONFIG_SH_DEVICE_TREE
static const struct platform_device_id sh_tmu_id_table[] = {
{ "sh-tmu", SH_TMU },
{ "sh-tmu-sh3", SH_TMU_SH3 },
@@ -665,12 +711,17 @@ static void __exit sh_tmu_exit(void)
platform_driver_unregister(&sh_tmu_device_driver);
}
+subsys_initcall(sh_tmu_init);
+module_exit(sh_tmu_exit);
+#endif
+
#ifdef CONFIG_SUPERH
+#ifdef CONFIG_SH_DEVICE_TREE
+TIMER_OF_DECLARE(sh_tmu, "renesas,tmu", sh_tmu_of_register);
+#else
sh_early_platform_init("earlytimer", &sh_tmu_device_driver);
#endif
-
-subsys_initcall(sh_tmu_init);
-module_exit(sh_tmu_exit);
+#endif
MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH TMU Timer Driver");
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 22/35] drivers/clocksource/sh_tmu: Add support CLOCKSOURCE.
2023-10-14 14:53 ` [RFC PATCH v3 22/35] drivers/clocksource/sh_tmu: Add support CLOCKSOURCE Yoshinori Sato
@ 2023-10-18 16:04 ` Geert Uytterhoeven
2023-10-23 11:40 ` Yoshinori Sato
0 siblings, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 16:04 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
Thanks for your patch!
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Enables registration as a Clocksource in the case of OF.
I think this is not a good description.
What this patch does, is to add support for early registration using
TIMER_OF_DECLARE(), so the timer can be used as a clocksource
on SoCs that do not have any other suitable timer.
Then I wondered: do you need this? On R-Mobile A1, the TMU is also
used as a clocksource, how come it works there?
The trick is to set preset_lpj based on the CPU core clock frequency.
I see your v2 actually added that, but you dropped the code in v3.
https://lore.kernel.org/linux-sh/236185b4a47f303332aafeacadd9c9652e650062.1694596125.git.ysato@users.sourceforge.jp
Nevertheless, it doesn't work anymore, as you also removed the
clock-frequency property from cpu@0 in DT...
Adding that makes it work without this TMU patch.
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> --- a/drivers/clocksource/sh_tmu.c
> +++ b/drivers/clocksource/sh_tmu.c
> @@ -403,7 +411,8 @@ static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
> }
>
> static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
> - const char *name)
> + const char *name,
> + struct device_node *np)
"np" is unused in this function, hence this change is unneeded.
> {
> struct clock_event_device *ced = &ch->ced;
> int ret;
> static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
> + struct device_node *np,
This change is unneeded...
> bool clockevent, bool clocksource)
> {
> if (clockevent) {
> ch->tmu->has_clockevent = true;
> - sh_tmu_register_clockevent(ch, name);
> + sh_tmu_register_clockevent(ch, name, np);
... as sh_tmu_register_clockevent() doesn't use "np".
> } else if (clocksource) {
> ch->tmu->has_clocksource = true;
> sh_tmu_register_clocksource(ch, name);
> @@ -465,53 +477,59 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
> else
> ch->base = tmu->mapbase + 8 + ch->index * 12;
>
> - ch->irq = platform_get_irq(tmu->pdev, index);
> + if (tmu->pdev)
> + ch->irq = platform_get_irq(tmu->pdev, index);
> + else
> + ch->irq = of_irq_get(np, index);
You can use of_irq_get() uncondtionally.
> if (ch->irq < 0)
> return ch->irq;
>
> ch->cs_enabled = false;
> ch->enable_count = 0;
>
> - return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
> + return sh_tmu_register(ch, tmu->name, np,
No need to pass np.
> clockevent, clocksource);
> }
>
> -static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
> +static int sh_tmu_map_memory(struct sh_tmu_device *tmu, struct device_node *np)
> {
> struct resource *res;
>
> - res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
> - if (!res) {
> - dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
> - return -ENXIO;
> - }
> + if (tmu->pdev) {
> + res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + pr_err("sh_tmu failed to get I/O memory\n");
> + return -ENXIO;
> + }
> +
> + tmu->mapbase = ioremap(res->start, resource_size(res));
> + } else
> + tmu->mapbase = of_iomap(np, 0);
You can use of_iomap() unconditionally.
>
> - tmu->mapbase = ioremap(res->start, resource_size(res));
> if (tmu->mapbase == NULL)
> return -ENXIO;
>
> return 0;
> }
>
> -static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
> +static int sh_tmu_parse_dt(struct sh_tmu_device *tmu, struct device_node *np)
> {
> - struct device_node *np = tmu->pdev->dev.of_node;
> -
> tmu->model = SH_TMU;
> tmu->num_channels = 3;
>
> of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
>
> if (tmu->num_channels != 2 && tmu->num_channels != 3) {
> - dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
> - tmu->num_channels);
> + pr_err("%s: invalid number of channels %u\n",
> + tmu->name, tmu->num_channels);
> return -EINVAL;
> }
>
> return 0;
> }
>
> -static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
> +static int sh_tmu_setup(struct sh_tmu_device *tmu,
> + struct platform_device *pdev, struct device_node *np)
> {
> unsigned int i;
> int ret;
> @@ -531,14 +554,17 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
> tmu->model = id->driver_data;
> tmu->num_channels = hweight8(cfg->channels_mask);
> } else {
> - dev_err(&tmu->pdev->dev, "missing platform data\n");
> + pr_err("%s missing platform data\n", tmu->name);
> return -ENXIO;
> }
>
> /* Get hold of clock. */
> - tmu->clk = clk_get(&tmu->pdev->dev, "fck");
> + if (pdev)
> + tmu->clk = clk_get(&tmu->pdev->dev, "fck");
> + else
> + tmu->clk = of_clk_get(np, 0);
You can use of_clk_get() unconditionally.
> if (IS_ERR(tmu->clk)) {
> - dev_err(&tmu->pdev->dev, "cannot get clock\n");
> + pr_err("%s: cannot get clock\n", tmu->name);
> return PTR_ERR(tmu->clk);
> }
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 22/35] drivers/clocksource/sh_tmu: Add support CLOCKSOURCE.
2023-10-18 16:04 ` Geert Uytterhoeven
@ 2023-10-23 11:40 ` Yoshinori Sato
0 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-23 11:40 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-sh, glaubitz
On Thu, 19 Oct 2023 01:04:57 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> Thanks for your patch!
>
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Enables registration as a Clocksource in the case of OF.
>
> I think this is not a good description.
> What this patch does, is to add support for early registration using
> TIMER_OF_DECLARE(), so the timer can be used as a clocksource
> on SoCs that do not have any other suitable timer.
>
> Then I wondered: do you need this? On R-Mobile A1, the TMU is also
> used as a clocksource, how come it works there?
> The trick is to set preset_lpj based on the CPU core clock frequency.
>
> I see your v2 actually added that, but you dropped the code in v3.
> https://lore.kernel.org/linux-sh/236185b4a47f303332aafeacadd9c9652e650062.1694596125.git.ysato@users.sourceforge.jp
> Nevertheless, it doesn't work anymore, as you also removed the
> clock-frequency property from cpu@0 in DT...
> Adding that makes it work without this TMU patch.
Currently sh initializes the timer with a parameter called "earlytimer",
but this does not seem to work correctly with CONFIG_OF.
It will be initialized later when of_platform_depopulate is called,
so it can be started, but I think this is incorrect initialization
of the timer.
I think it's better to follow the OF procedure rather than the old
SH-specific framework.
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > --- a/drivers/clocksource/sh_tmu.c
> > +++ b/drivers/clocksource/sh_tmu.c
>
> > @@ -403,7 +411,8 @@ static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
> > }
> >
> > static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
> > - const char *name)
> > + const char *name,
> > + struct device_node *np)
>
> "np" is unused in this function, hence this change is unneeded.
>
> > {
> > struct clock_event_device *ced = &ch->ced;
> > int ret;
>
> > static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
> > + struct device_node *np,
>
> This change is unneeded...
>
> > bool clockevent, bool clocksource)
> > {
> > if (clockevent) {
> > ch->tmu->has_clockevent = true;
> > - sh_tmu_register_clockevent(ch, name);
> > + sh_tmu_register_clockevent(ch, name, np);
>
> ... as sh_tmu_register_clockevent() doesn't use "np".
>
> > } else if (clocksource) {
> > ch->tmu->has_clocksource = true;
> > sh_tmu_register_clocksource(ch, name);
>
> > @@ -465,53 +477,59 @@ static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
> > else
> > ch->base = tmu->mapbase + 8 + ch->index * 12;
> >
> > - ch->irq = platform_get_irq(tmu->pdev, index);
> > + if (tmu->pdev)
> > + ch->irq = platform_get_irq(tmu->pdev, index);
> > + else
> > + ch->irq = of_irq_get(np, index);
>
> You can use of_irq_get() uncondtionally.
>
> > if (ch->irq < 0)
> > return ch->irq;
> >
> > ch->cs_enabled = false;
> > ch->enable_count = 0;
> >
> > - return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
> > + return sh_tmu_register(ch, tmu->name, np,
>
> No need to pass np.
>
> > clockevent, clocksource);
> > }
> >
> > -static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
> > +static int sh_tmu_map_memory(struct sh_tmu_device *tmu, struct device_node *np)
> > {
> > struct resource *res;
> >
> > - res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
> > - if (!res) {
> > - dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
> > - return -ENXIO;
> > - }
> > + if (tmu->pdev) {
> > + res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + pr_err("sh_tmu failed to get I/O memory\n");
> > + return -ENXIO;
> > + }
> > +
> > + tmu->mapbase = ioremap(res->start, resource_size(res));
> > + } else
> > + tmu->mapbase = of_iomap(np, 0);
>
> You can use of_iomap() unconditionally.
>
> >
> > - tmu->mapbase = ioremap(res->start, resource_size(res));
> > if (tmu->mapbase == NULL)
> > return -ENXIO;
> >
> > return 0;
> > }
> >
> > -static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
> > +static int sh_tmu_parse_dt(struct sh_tmu_device *tmu, struct device_node *np)
> > {
> > - struct device_node *np = tmu->pdev->dev.of_node;
> > -
> > tmu->model = SH_TMU;
> > tmu->num_channels = 3;
> >
> > of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
> >
> > if (tmu->num_channels != 2 && tmu->num_channels != 3) {
> > - dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
> > - tmu->num_channels);
> > + pr_err("%s: invalid number of channels %u\n",
> > + tmu->name, tmu->num_channels);
> > return -EINVAL;
> > }
> >
> > return 0;
> > }
> >
> > -static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
> > +static int sh_tmu_setup(struct sh_tmu_device *tmu,
> > + struct platform_device *pdev, struct device_node *np)
> > {
> > unsigned int i;
> > int ret;
>
> > @@ -531,14 +554,17 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
> > tmu->model = id->driver_data;
> > tmu->num_channels = hweight8(cfg->channels_mask);
> > } else {
> > - dev_err(&tmu->pdev->dev, "missing platform data\n");
> > + pr_err("%s missing platform data\n", tmu->name);
> > return -ENXIO;
> > }
> >
> > /* Get hold of clock. */
> > - tmu->clk = clk_get(&tmu->pdev->dev, "fck");
> > + if (pdev)
> > + tmu->clk = clk_get(&tmu->pdev->dev, "fck");
> > + else
> > + tmu->clk = of_clk_get(np, 0);
>
> You can use of_clk_get() unconditionally.
>
> > if (IS_ERR(tmu->clk)) {
> > - dev_err(&tmu->pdev->dev, "cannot get clock\n");
> > + pr_err("%s: cannot get clock\n", tmu->name);
> > return PTR_ERR(tmu->clk);
> > }
> >
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 23/35] Documentation/devicetree/bindings/timer: renesas,tmu.yaml add SH.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (21 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 22/35] drivers/clocksource/sh_tmu: Add support CLOCKSOURCE Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 19:40 ` Geert Uytterhoeven
2023-10-14 14:53 ` [RFC PATCH v3 24/35] include/dt-binding/interrupt-controller/sh_intc.h: renesas,sh7751-intc.h helper Yoshinori Sato
` (12 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../devicetree/bindings/timer/renesas,tmu.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
index a67e427a9e7e..0c609d54ff10 100644
--- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
@@ -21,6 +21,7 @@ properties:
compatible:
items:
- enum:
+ - renesas,tmu-sh # SH
- renesas,tmu-r8a7740 # R-Mobile A1
- renesas,tmu-r8a774a1 # RZ/G2M
- renesas,tmu-r8a774b1 # RZ/G2N
@@ -46,7 +47,14 @@ properties:
interrupts:
minItems: 2
- maxItems: 3
+ maxItems: 4
+
+ interrupt-names:
+ items:
+ - const: tuni0
+ - const: tuni1
+ - const: tuni2
+ - const: ticpi2
clocks:
maxItems: 1
@@ -84,6 +92,7 @@ if:
- renesas,tmu-r8a7740
- renesas,tmu-r8a7778
- renesas,tmu-r8a7779
+ - renesas,tmu-sh
then:
required:
- resets
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 23/35] Documentation/devicetree/bindings/timer: renesas,tmu.yaml add SH.
2023-10-14 14:53 ` [RFC PATCH v3 23/35] Documentation/devicetree/bindings/timer: renesas,tmu.yaml add SH Yoshinori Sato
@ 2023-10-18 19:40 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 19:40 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
> +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
> @@ -21,6 +21,7 @@ properties:
> compatible:
> items:
> - enum:
> + - renesas,tmu-sh # SH
Please use an SoC-specific compatible value: renesas,tmu-sh7750
> - renesas,tmu-r8a7740 # R-Mobile A1
> - renesas,tmu-r8a774a1 # RZ/G2M
> - renesas,tmu-r8a774b1 # RZ/G2N
> @@ -46,7 +47,14 @@ properties:
>
> interrupts:
> minItems: 2
> - maxItems: 3
> + maxItems: 4
> +
> + interrupt-names:
> + items:
> + - const: tuni0
> + - const: tuni1
> + - const: tuni2
> + - const: ticpi2
I'm delighted to see support for the 4th interrupt, finally!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 24/35] include/dt-binding/interrupt-controller/sh_intc.h: renesas,sh7751-intc.h helper
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (22 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 23/35] Documentation/devicetree/bindings/timer: renesas,tmu.yaml add SH Yoshinori Sato
@ 2023-10-14 14:53 ` Yoshinori Sato
2023-10-18 13:39 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU Yoshinori Sato
` (11 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:53 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt
SH7751 Interrupt controller binding helper.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../dt-bindings/interrupt-controller/sh_intc.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
create mode 100644 include/dt-bindings/interrupt-controller/sh_intc.h
diff --git a/include/dt-bindings/interrupt-controller/sh_intc.h b/include/dt-bindings/interrupt-controller/sh_intc.h
new file mode 100644
index 000000000000..956259e985ea
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/sh_intc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * SH3/4 INTC EVT - IRQ conversion
+ */
+
+#define evt2irq(evt) ((evt) >> 5)
+#define irq2evt(irq) ((irq) << 5)
+
+#define IPRDEF(e, o, b) < e o b >
+#define IPRA 0
+#define IPRB 4
+#define IPRC 8
+#define IPRD 12
+#define INTPRI00 256
+#define IPR_B12 12
+#define IPR_B8 8
+#define IPR_B4 4
+#define IPR_B0 0
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 24/35] include/dt-binding/interrupt-controller/sh_intc.h: renesas,sh7751-intc.h helper
2023-10-14 14:53 ` [RFC PATCH v3 24/35] include/dt-binding/interrupt-controller/sh_intc.h: renesas,sh7751-intc.h helper Yoshinori Sato
@ 2023-10-18 13:39 ` Geert Uytterhoeven
2023-10-18 14:03 ` Krzysztof Kozlowski
0 siblings, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 13:39 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> SH7751 Interrupt controller binding helper.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * SH3/4 INTC EVT - IRQ conversion
> + */
> +
> +#define evt2irq(evt) ((evt) >> 5)
> +#define irq2evt(irq) ((irq) << 5)
Please drop irq2evt() as it is not used, and not needed, in DTS files.
> +
> +#define IPRDEF(e, o, b) < e o b >
Please drop this macro, it doesn't add any value.
> +#define IPRA 0
> +#define IPRB 4
> +#define IPRC 8
> +#define IPRD 12
> +#define INTPRI00 256
> +#define IPR_B12 12
> +#define IPR_B8 8
> +#define IPR_B4 4
> +#define IPR_B0 0
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 24/35] include/dt-binding/interrupt-controller/sh_intc.h: renesas,sh7751-intc.h helper
2023-10-18 13:39 ` Geert Uytterhoeven
@ 2023-10-18 14:03 ` Krzysztof Kozlowski
0 siblings, 0 replies; 88+ messages in thread
From: Krzysztof Kozlowski @ 2023-10-18 14:03 UTC (permalink / raw)
To: Geert Uytterhoeven, Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt
On 18/10/2023 15:39, Geert Uytterhoeven wrote:
> Hi Sato-san,
>
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
>> SH7751 Interrupt controller binding helper.
>>
>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> Thanks for your patch!
>
>> --- /dev/null
>> +++ b/include/dt-bindings/interrupt-controller/sh_intc.h
>> @@ -0,0 +1,18 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> + *
>> + * SH3/4 INTC EVT - IRQ conversion
>> + */
>> +
>> +#define evt2irq(evt) ((evt) >> 5)
>> +#define irq2evt(irq) ((irq) << 5)
>
> Please drop irq2evt() as it is not used, and not needed, in DTS files.
And we talked about this already... just like about few other things
which did not improve. This patchset is repeating the same issues over
and over again.
Please call it not RFC, but "DO NOT MERGE" or something like this.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (23 preceding siblings ...)
2023-10-14 14:53 ` [RFC PATCH v3 24/35] include/dt-binding/interrupt-controller/sh_intc.h: renesas,sh7751-intc.h helper Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-18 14:27 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi Yoshinori Sato
` (10 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Renesas SuperH binding definition.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../devicetree/bindings/sh/cpus.yaml | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml
diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml
new file mode 100644
index 000000000000..273df4dfb74e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sh/cpus.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sh/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH CPUs
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description: |+
+ The device tree allows to describe the layout of CPUs in a system through
+ the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+ defining properties for every cpu.
+
+ Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+ https://www.devicetree.org/specifications/
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,sh4
+ - const: renesas,sh
+
+ clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ CPU core clock freqency.
+
+required:
+ - compatible
+
+additionalProperties: true
+
+examples:
+ - |
+ cpus {
+ cpu: cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ };
+ };
+...
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-14 14:54 ` [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU Yoshinori Sato
@ 2023-10-18 14:27 ` Geert Uytterhoeven
2023-10-25 11:14 ` Yoshinori Sato
0 siblings, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 14:27 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas SuperH binding definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SuperH CPUs
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +description: |+
> + The device tree allows to describe the layout of CPUs in a system through
> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> + defining properties for every cpu.
> +
> + Bindings for CPU nodes follow the Devicetree Specification, available from:
> +
> + https://www.devicetree.org/specifications/
> +
> +properties:
> + compatible:
> + items:
> + - enum:
Missing
- jcore,j2
> + - renesas,sh4
> + - const: renesas,sh
I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
"renesas,sh", though.
Is there a common base of instructions that are available on all SH cores?
Missing reg property.
Missing "device_type: true".
> +
> + clock-frequency:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + CPU core clock freqency.
Perhaps a "clocks" property instead, or as an alternative?
On sh7750, you do have
clocks = <&cpg SH7750_CPG_ICK>;
> +
> +required:
> + - compatible
> +
> +additionalProperties: true
> +
> +examples:
> + - |
> + cpus {
make dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
'#address-cells' is a required property
from schema $id: http://devicetree.org/schemas/cpus.yaml#
Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
'#size-cells' is a required property
from schema $id: http://devicetree.org/schemas/cpus.yaml#
> + cpu: cpu@0 {
> + compatible = "renesas,sh4", "renesas,sh";
Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
name, but no reg or ranges property
Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
'cache-level' is a required property
from schema $id: http://devicetree.org/schemas/cpus.yaml#
> + };
> + };
> +...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-18 14:27 ` Geert Uytterhoeven
@ 2023-10-25 11:14 ` Yoshinori Sato
2023-10-25 11:33 ` D. Jeff Dionne
2023-10-25 12:01 ` Geert Uytterhoeven
0 siblings, 2 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-25 11:14 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
On Wed, 18 Oct 2023 23:27:43 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Renesas SuperH binding definition.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> > @@ -0,0 +1,45 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SuperH CPUs
> > +
> > +maintainers:
> > + - Yoshinori Sato <ysato@users.sourceforge.jp>
> > +
> > +description: |+
> > + The device tree allows to describe the layout of CPUs in a system through
> > + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > + defining properties for every cpu.
> > +
> > + Bindings for CPU nodes follow the Devicetree Specification, available from:
> > +
> > + https://www.devicetree.org/specifications/
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
>
> Missing
>
> - jcore,j2
>
> > + - renesas,sh4
>
>
> > + - const: renesas,sh
>
> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> "renesas,sh", though.
> Is there a common base of instructions that are available on all SH cores?
The base instruction set is sh2.
Before that, there is sh1, but this is not compatible with Linux.
I think it would be a good idea to change this to "renesas,sh2",
but the SH7619 (SH2 CPU) would look like the following.
cpus {
cpu: cpu@0 {
compatible = "renesas,sh2", "renesas,sh2";
};
};
> Missing reg property.
> Missing "device_type: true".
>
> > +
> > + clock-frequency:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + CPU core clock freqency.
>
> Perhaps a "clocks" property instead, or as an alternative?
>
> On sh7750, you do have
>
> clocks = <&cpg SH7750_CPG_ICK>;
>
> > +
> > +required:
> > + - compatible
> > +
> > +additionalProperties: true
> > +
> > +examples:
> > + - |
> > + cpus {
>
> make dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
>
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> '#address-cells' is a required property
> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> '#size-cells' is a required property
> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>
> > + cpu: cpu@0 {
> > + compatible = "renesas,sh4", "renesas,sh";
>
> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
> name, but no reg or ranges property
> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
> 'cache-level' is a required property
> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>
> > + };
> > + };
> > +...
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 11:14 ` Yoshinori Sato
@ 2023-10-25 11:33 ` D. Jeff Dionne
2023-10-25 12:04 ` Geert Uytterhoeven
2023-10-25 12:07 ` Yoshinori Sato
2023-10-25 12:01 ` Geert Uytterhoeven
1 sibling, 2 replies; 88+ messages in thread
From: D. Jeff Dionne @ 2023-10-25 11:33 UTC (permalink / raw)
To: Yoshinori Sato
Cc: Geert Uytterhoeven, linux-sh, glaubitz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
Hi Sato-san,
We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
J-Core has the responsibility for maintenance of those SH ISA compatible cores.
J.
> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
>
> On Wed, 18 Oct 2023 23:27:43 +0900,
> Geert Uytterhoeven wrote:
>>
>> Hi Sato-san,
>>
>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>> <ysato@users.sourceforge.jp> wrote:
>>> Renesas SuperH binding definition.
>>>
>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>>
>> Thanks for your patch!
>>
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>>> @@ -0,0 +1,45 @@
>>> +# SPDX-License-Identifier: GPL-2.0
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Renesas SuperH CPUs
>>> +
>>> +maintainers:
>>> + - Yoshinori Sato <ysato@users.sourceforge.jp>
>>> +
>>> +description: |+
>>> + The device tree allows to describe the layout of CPUs in a system through
>>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>> + defining properties for every cpu.
>>> +
>>> + Bindings for CPU nodes follow the Devicetree Specification, available from:
>>> +
>>> + https://www.devicetree.org/specifications/
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>
>> Missing
>>
>> - jcore,j2
>>
>>> + - renesas,sh4
>>
>>
>>> + - const: renesas,sh
>>
>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
>> "renesas,sh", though.
>> Is there a common base of instructions that are available on all SH cores?
>
> The base instruction set is sh2.
> Before that, there is sh1, but this is not compatible with Linux.
> I think it would be a good idea to change this to "renesas,sh2",
> but the SH7619 (SH2 CPU) would look like the following.
> cpus {
> cpu: cpu@0 {
> compatible = "renesas,sh2", "renesas,sh2";
> };
> };
>
>> Missing reg property.
>> Missing "device_type: true".
>>
>>> +
>>> + clock-frequency:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: |
>>> + CPU core clock freqency.
>>
>> Perhaps a "clocks" property instead, or as an alternative?
>>
>> On sh7750, you do have
>>
>> clocks = <&cpg SH7750_CPG_ICK>;
>>
>>> +
>>> +required:
>>> + - compatible
>>> +
>>> +additionalProperties: true
>>> +
>>> +examples:
>>> + - |
>>> + cpus {
>>
>> make dt_binding_check
>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
>>
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
>> '#address-cells' is a required property
>> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
>> '#size-cells' is a required property
>> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>>
>>> + cpu: cpu@0 {
>>> + compatible = "renesas,sh4", "renesas,sh";
>>
>> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
>> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
>> name, but no reg or ranges property
>> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
>> 'cache-level' is a required property
>> from schema $id: http://devicetree.org/schemas/cpus.yaml#
>>
>>> + };
>>> + };
>>> +...
>>
>> Gr{oetje,eeting}s,
>>
>> Geert
>>
>> --
>> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>>
>> In personal conversations with technical people, I call myself a hacker. But
>> when I'm talking to journalists I just say "programmer" or something like that.
>> -- Linus Torvalds
>
> --
> Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 11:33 ` D. Jeff Dionne
@ 2023-10-25 12:04 ` Geert Uytterhoeven
2023-10-25 12:10 ` D. Jeff Dionne
2023-10-25 12:07 ` Yoshinori Sato
1 sibling, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-25 12:04 UTC (permalink / raw)
To: D. Jeff Dionne
Cc: Yoshinori Sato, linux-sh, glaubitz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
Hi Jeff,
On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
> > On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> > On Wed, 18 Oct 2023 23:27:43 +0900,
> > Geert Uytterhoeven wrote:
> >> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >> <ysato@users.sourceforge.jp> wrote:
> >>> Renesas SuperH binding definition.
> >>>
> >>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>> @@ -0,0 +1,45 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas SuperH CPUs
> >>> +
> >>> +maintainers:
> >>> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> >>> +
> >>> +description: |+
> >>> + The device tree allows to describe the layout of CPUs in a system through
> >>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> >>> + defining properties for every cpu.
> >>> +
> >>> + Bindings for CPU nodes follow the Devicetree Specification, available from:
> >>> +
> >>> + https://www.devicetree.org/specifications/
> >>> +
> >>> +properties:
> >>> + compatible:
> >>> + items:
> >>> + - enum:
> >>
> >> Missing
> >>
> >> - jcore,j2
> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
Compatible values do not declare any such endorsement.
> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
The question is: does J2 implement the same instruction set as SH2,
i.e. can it run unmodified SH2 code?
> >>
> >>> + - renesas,sh4
> >>
> >>
> >>> + - const: renesas,sh
> >>
> >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> >> "renesas,sh", though.
> >> Is there a common base of instructions that are available on all SH cores?
> >
> > The base instruction set is sh2.
> > Before that, there is sh1, but this is not compatible with Linux.
> > I think it would be a good idea to change this to "renesas,sh2",
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 12:04 ` Geert Uytterhoeven
@ 2023-10-25 12:10 ` D. Jeff Dionne
2023-10-25 12:17 ` Geert Uytterhoeven
0 siblings, 1 reply; 88+ messages in thread
From: D. Jeff Dionne @ 2023-10-25 12:10 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yoshinori Sato, linux-sh, glaubitz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Jeff,
Hi Geert,
>
> On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
>>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
>>> On Wed, 18 Oct 2023 23:27:43 +0900,
>>> Geert Uytterhoeven wrote:
>>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>>>> <ysato@users.sourceforge.jp> wrote:
>>>>> Renesas SuperH binding definition.
>>>>>
>>>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>>>>> @@ -0,0 +1,45 @@
>>>>> +# SPDX-License-Identifier: GPL-2.0
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Renesas SuperH CPUs
>>>>> +
>>>>> +maintainers:
>>>>> + - Yoshinori Sato <ysato@users.sourceforge.jp>
>>>>> +
>>>>> +description: |+
>>>>> + The device tree allows to describe the layout of CPUs in a system through
>>>>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>>>> + defining properties for every cpu.
>>>>> +
>>>>> + Bindings for CPU nodes follow the Devicetree Specification, available from:
>>>>> +
>>>>> + https://www.devicetree.org/specifications/
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + items:
>>>>> + - enum:
>>>>
>>>> Missing
>>>>
>>>> - jcore,j2
>
>> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
>
> Compatible values do not declare any such endorsement.
>
>> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>
> The question is: does J2 implement the same instruction set as SH2,
> i.e. can it run unmodified SH2 code?
It can run all SH2 code, but an SH2 cannot run all J2 code.
The GCC compilers we use for J2 generate J2 code, not strictly SH2 code.
The main difference is SH3 dynamic shift, and (S390 derived) Compare And Swap. The new FPU is in testing now, and AFAIK there is no FPU for SH2 but I’m not sure.
Cheers,
J.
>>>>
>>>>> + - renesas,sh4
>>>>
>>>>
>>>>> + - const: renesas,sh
>>>>
>>>> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
>>>> "renesas,sh", though.
>>>> Is there a common base of instructions that are available on all SH cores?
>>>
>>> The base instruction set is sh2.
>>> Before that, there is sh1, but this is not compatible with Linux.
>>> I think it would be a good idea to change this to "renesas,sh2",
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 12:10 ` D. Jeff Dionne
@ 2023-10-25 12:17 ` Geert Uytterhoeven
2023-10-25 12:34 ` D. Jeff Dionne
0 siblings, 1 reply; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-25 12:17 UTC (permalink / raw)
To: D. Jeff Dionne
Cc: Yoshinori Sato, linux-sh, glaubitz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
Hi Jeff,
On Wed, Oct 25, 2023 at 2:10 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
> On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
> >>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> >>> On Wed, 18 Oct 2023 23:27:43 +0900,
> >>> Geert Uytterhoeven wrote:
> >>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >>>> <ysato@users.sourceforge.jp> wrote:
> >>>>> Renesas SuperH binding definition.
> >>>>>
> >>>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>>>> +properties:
> >>>>> + compatible:
> >>>>> + items:
> >>>>> + - enum:
> >>>>
> >>>> Missing
> >>>>
> >>>> - jcore,j2
> >
> >> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
> >
> > Compatible values do not declare any such endorsement.
> >
> >> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
> >
> > The question is: does J2 implement the same instruction set as SH2,
> > i.e. can it run unmodified SH2 code?
>
> It can run all SH2 code, but an SH2 cannot run all J2 code.
This is exactly what
compatible = "jcore,j2", "renesas,sh2";
represents.
Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification
https://www.devicetree.org/specifications
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 12:17 ` Geert Uytterhoeven
@ 2023-10-25 12:34 ` D. Jeff Dionne
0 siblings, 0 replies; 88+ messages in thread
From: D. Jeff Dionne @ 2023-10-25 12:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Yoshinori Sato, open list:SUPERH, John Paul Adrian Glaubitz,
robh+dt, krzysztof.kozlowski+dt, conor+dt, devicetree
> On Oct 25, 2023, at 21:17, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Jeff,
>
> On Wed, Oct 25, 2023 at 2:10 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
>> On Oct 25, 2023, at 21:04, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>>> On Wed, Oct 25, 2023 at 1:33 PM D. Jeff Dionne <djeffdionne@gmail.com> wrote:
>>>>> On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
>>>>> On Wed, 18 Oct 2023 23:27:43 +0900,
>>>>> Geert Uytterhoeven wrote:
>>>>>> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
>>>>>> <ysato@users.sourceforge.jp> wrote:
>>>>>>> Renesas SuperH binding definition.
>>>>>>>
>>>>>>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>>>
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
>
>>>>>>> +properties:
>>>>>>> + compatible:
>>>>>>> + items:
>>>>>>> + - enum:
>>>>>>
>>>>>> Missing
>>>>>>
>>>>>> - jcore,j2
>>>
>>>> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
>>>
>>> Compatible values do not declare any such endorsement.
>>>
>>>> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>>>
>>> The question is: does J2 implement the same instruction set as SH2,
>>> i.e. can it run unmodified SH2 code?
>>
>> It can run all SH2 code, but an SH2 cannot run all J2 code.
>
> This is exactly what
>
> compatible = "jcore,j2", "renesas,sh2";
Oh, yes. I agree, this is correct. Once this is settled upon, we can change new J2 cores so they will export their ROM device tree with the sh2 fallback.
Down thread, Sato-san proposes “renesas,sh4”, “renesas,sh” I’m not sure I understand what a “renesas,sh” base fallback is.
J.
> represents.
> Cfr. Section 2.3.1 ("compatible") of the Devicetree Specification
> https://www.devicetree.org/specifications
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 11:33 ` D. Jeff Dionne
2023-10-25 12:04 ` Geert Uytterhoeven
@ 2023-10-25 12:07 ` Yoshinori Sato
1 sibling, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-25 12:07 UTC (permalink / raw)
To: D. Jeff Dionne
Cc: Geert Uytterhoeven, linux-sh, glaubitz, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree
On Wed, 25 Oct 2023 20:33:07 +0900,
D. Jeff Dionne wrote:
>
> Hi Sato-san,
>
> We must not imply that Renesas is responsible for J2, or that it is a sanctioned SH core.
>
> J-Core has the responsibility for maintenance of those SH ISA compatible cores.
>
Yes. I know.
I intended to write about ISA compatibility.
> J.
>
> > On Oct 25, 2023, at 20:14, Yoshinori Sato <ysato@users.sourceforge.jp> wrote:
> >
> > On Wed, 18 Oct 2023 23:27:43 +0900,
> > Geert Uytterhoeven wrote:
> >>
> >> Hi Sato-san,
> >>
> >> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> >> <ysato@users.sourceforge.jp> wrote:
> >>> Renesas SuperH binding definition.
> >>>
> >>> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> >>
> >> Thanks for your patch!
> >>
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> >>> @@ -0,0 +1,45 @@
> >>> +# SPDX-License-Identifier: GPL-2.0
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Renesas SuperH CPUs
> >>> +
> >>> +maintainers:
> >>> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> >>> +
> >>> +description: |+
> >>> + The device tree allows to describe the layout of CPUs in a system through
> >>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> >>> + defining properties for every cpu.
> >>> +
> >>> + Bindings for CPU nodes follow the Devicetree Specification, available from:
> >>> +
> >>> + https://www.devicetree.org/specifications/
> >>> +
> >>> +properties:
> >>> + compatible:
> >>> + items:
> >>> + - enum:
> >>
> >> Missing
> >>
> >> - jcore,j2
> >>
> >>> + - renesas,sh4
> >>
> >>
> >>> + - const: renesas,sh
> >>
> >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> >> "renesas,sh", though.
> >> Is there a common base of instructions that are available on all SH cores?
> >
> > The base instruction set is sh2.
> > Before that, there is sh1, but this is not compatible with Linux.
> > I think it would be a good idea to change this to "renesas,sh2",
> > but the SH7619 (SH2 CPU) would look like the following.
> > cpus {
> > cpu: cpu@0 {
> > compatible = "renesas,sh2", "renesas,sh2";
> > };
> > };
> >
> >> Missing reg property.
> >> Missing "device_type: true".
> >>
> >>> +
> >>> + clock-frequency:
> >>> + $ref: /schemas/types.yaml#/definitions/uint32
> >>> + description: |
> >>> + CPU core clock freqency.
> >>
> >> Perhaps a "clocks" property instead, or as an alternative?
> >>
> >> On sh7750, you do have
> >>
> >> clocks = <&cpg SH7750_CPG_ICK>;
> >>
> >>> +
> >>> +required:
> >>> + - compatible
> >>> +
> >>> +additionalProperties: true
> >>> +
> >>> +examples:
> >>> + - |
> >>> + cpus {
> >>
> >> make dt_binding_check
> >> DT_SCHEMA_FILES=Documentation/devicetree/bindings/sh/cpus.yaml:
> >>
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> >> '#address-cells' is a required property
> >> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus:
> >> '#size-cells' is a required property
> >> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >>
> >>> + cpu: cpu@0 {
> >>> + compatible = "renesas,sh4", "renesas,sh";
> >>
> >> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19:
> >> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit
> >> name, but no reg or ranges property
> >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0:
> >> 'cache-level' is a required property
> >> from schema $id: http://devicetree.org/schemas/cpus.yaml#
> >>
> >>> + };
> >>> + };
> >>> +...
> >>
> >> Gr{oetje,eeting}s,
> >>
> >> Geert
> >>
> >> --
> >> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> >>
> >> In personal conversations with technical people, I call myself a hacker. But
> >> when I'm talking to journalists I just say "programmer" or something like that.
> >> -- Linus Torvalds
> >
> > --
> > Yosinori Sato
>
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU.
2023-10-25 11:14 ` Yoshinori Sato
2023-10-25 11:33 ` D. Jeff Dionne
@ 2023-10-25 12:01 ` Geert Uytterhoeven
1 sibling, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-25 12:01 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Wed, Oct 25, 2023 at 1:14 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> On Wed, 18 Oct 2023 23:27:43 +0900,
> Geert Uytterhoeven wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Renesas SuperH binding definition.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> >
> > Missing
> >
> > - jcore,j2
> >
> > > + - renesas,sh4
> >
> >
> > > + - const: renesas,sh
> >
> > I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to
> > "renesas,sh", though.
> > Is there a common base of instructions that are available on all SH cores?
>
> The base instruction set is sh2.
> Before that, there is sh1, but this is not compatible with Linux.
> I think it would be a good idea to change this to "renesas,sh2",
> but the SH7619 (SH2 CPU) would look like the following.
> cpus {
> cpu: cpu@0 {
> compatible = "renesas,sh2", "renesas,sh2";
> };
> };
SH7619 would just use a single compatible value:
compatible = "renesas,sh2".
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (24 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-19 12:18 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc Yoshinori Sato
` (9 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Renesas SuperH SH7751R common definition.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/sh7751r.dtsi | 148 ++++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 arch/sh/boot/dts/sh7751r.dtsi
diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi
new file mode 100644
index 000000000000..66f71372baad
--- /dev/null
+++ b/arch/sh/boot/dts/sh7751r.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the SH7751R SoC
+ */
+
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+#include <dt-bindings/clock/sh7750.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&cpg SH7750_CPG_ICK>;
+ clock-names = "ick";
+ icache-size = <16384>;
+ icache-line-size = <32>;
+ dcache-size = <32768>;
+ dcache-line-size = <32>;
+ };
+ };
+
+ xtal: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "xtal";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&shintc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cpg: clock-controller@ffc00000 {
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ compatible = "renesas,sh7751r-cpg", "renesas,sh7750-cpg";
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ reg = <0xffc00000 20>, <0xfe0a0000 16>;
+ reg-names = "FRQCR", "CLKSTP00";
+ };
+
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xffd00000 20>, <0xfe080000 128>;
+ reg-names = "ICR", "INTPRI00";
+ renesas,ipr-map = IPRDEF(0x240, IPRD, IPR_B12), /* IRL0 */
+ IPRDEF(0x2a0, IPRD, IPR_B8), /* IRL1 */
+ IPRDEF(0x300, IPRD, IPR_B4), /* IRL2 */
+ IPRDEF(0x360, IPRD, IPR_B0), /* IRL3 */
+ IPRDEF(0x400, IPRA, IPR_B12), /* TMU0 */
+ IPRDEF(0x420, IPRA, IPR_B8), /* TMU1 */
+ IPRDEF(0x440, IPRA, IPR_B4), /* TMU2 TNUI */
+ IPRDEF(0x460, IPRA, IPR_B4), /* TMU2 TICPI */
+ IPRDEF(0x480, IPRA, IPR_B0), /* RTC ATI */
+ IPRDEF(0x4a0, IPRA, IPR_B0), /* RTC PRI */
+ IPRDEF(0x4c0, IPRA, IPR_B0), /* RTC CUI */
+ IPRDEF(0x4e0, IPRB, IPR_B4), /* SCI ERI */
+ IPRDEF(0x500, IPRB, IPR_B4), /* SCI RXI */
+ IPRDEF(0x520, IPRB, IPR_B4), /* SCI TXI */
+ IPRDEF(0x540, IPRB, IPR_B4), /* SCI TEI */
+ IPRDEF(0x560, IPRB, IPR_B12), /* WDT */
+ IPRDEF(0x580, IPRB, IPR_B8), /* REF RCMI */
+ IPRDEF(0x5a0, IPRB, IPR_B4), /* REF ROVI */
+ IPRDEF(0x600, IPRC, IPR_B0), /* H-UDI */
+ IPRDEF(0x620, IPRC, IPR_B12), /* GPIO */
+ IPRDEF(0x640, IPRC, IPR_B8), /* DMAC DMTE0 */
+ IPRDEF(0x660, IPRC, IPR_B8), /* DMAC DMTE1 */
+ IPRDEF(0x680, IPRC, IPR_B8), /* DMAC DMTE2 */
+ IPRDEF(0x6a0, IPRC, IPR_B8), /* DMAC DMTE3 */
+ IPRDEF(0x6c0, IPRC, IPR_B8), /* DMAC DMAE */
+ IPRDEF(0x700, IPRC, IPR_B4), /* SCIF ERI */
+ IPRDEF(0x720, IPRC, IPR_B4), /* SCIF RXI */
+ IPRDEF(0x740, IPRC, IPR_B4), /* SCIF BRI */
+ IPRDEF(0x760, IPRC, IPR_B4), /* SCIF TXI */
+ IPRDEF(0x780, IPRC, IPR_B8), /* DMAC DMTE4 */
+ IPRDEF(0x7a0, IPRC, IPR_B8), /* DMAC DMTE5 */
+ IPRDEF(0x7c0, IPRC, IPR_B8), /* DMAC DMTE6 */
+ IPRDEF(0x7e0, IPRC, IPR_B8), /* DMAC DMTE7 */
+ IPRDEF(0xa00, INTPRI00, IPR_B0), /* PCIC PCISERR */
+ IPRDEF(0xa20, INTPRI00, IPR_B4), /* PCIC PCIDMA3 */
+ IPRDEF(0xa40, INTPRI00, IPR_B4), /* PCIC PCIDMA2 */
+ IPRDEF(0xa60, INTPRI00, IPR_B4), /* PCIC PCIDMA1 */
+ IPRDEF(0xa80, INTPRI00, IPR_B4), /* PCIC PCIDMA0 */
+ IPRDEF(0xaa0, INTPRI00, IPR_B4), /* PCIC PCIPWON */
+ IPRDEF(0xac0, INTPRI00, IPR_B4), /* PCIC PCIPWDWN */
+ IPRDEF(0xae0, INTPRI00, IPR_B4), /* PCIC PCIERR */
+ IPRDEF(0xb00, INTPRI00, IPR_B8), /* TMU3 */
+ IPRDEF(0xb80, INTPRI00, IPR_B12); /* TMU4 */
+ };
+
+ /* sci0 is rarely used, so it is not defined here. */
+ scif1: serial@ffe80000 {
+ compatible = "renesas,scif-sh7751", "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0>,
+ <evt2irq(0x720) 0>,
+ <evt2irq(0x760) 0>,
+ <evt2irq(0x740) 0>;
+ interrupt-names = "eri", "rxi", "txi", "bri";
+ clocks = <&cpg SH7750_CPG_SCIF_CLK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ };
+
+ /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */
+ tmu0: timer@ffd80000 {
+ compatible = "renesas,tmu-sh", "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0>,
+ <evt2irq(0x420) 0>,
+ <evt2irq(0x440) 0>,
+ <evt2irq(0x460) 0>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
+ clocks = <&cpg SH7750_CPG_TMU012_CLK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ #renesas,channels = <3>;
+ };
+
+ pcic: pci@fe200000 {
+ compatible = "renesas,pci-sh7751";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ bus-range = <0 0>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi.
2023-10-14 14:54 ` [RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi Yoshinori Sato
@ 2023-10-19 12:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 12:18 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas SuperH SH7751R common definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/sh/boot/dts/sh7751r.dtsi
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the SH7751R SoC
> + */
> +
> +#include <dt-bindings/interrupt-controller/sh_intc.h>
> +#include <dt-bindings/clock/sh7750.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "renesas,sh4", "renesas,sh";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&cpg SH7750_CPG_ICK>;
> + clock-names = "ick";
> + icache-size = <16384>;
> + icache-line-size = <32>;
> + dcache-size = <32768>;
> + dcache-line-size = <32>;
Wrong indentation (2 TABs and 6 spaces instead of 3 TABs).
> + };
> + };
> +
> + xtal: oscillator {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <0>;
> + clock-output-names = "xtal";
> + };
> +
> + soc {
> + scif1: serial@ffe80000 {
> + compatible = "renesas,scif-sh7751", "renesas,scif";
> + reg = <0xffe80000 0x100>;
> + interrupts = <evt2irq(0x700) 0>,
> + <evt2irq(0x720) 0>,
> + <evt2irq(0x760) 0>,
> + <evt2irq(0x740) 0>;
> + interrupt-names = "eri", "rxi", "txi", "bri";
> + clocks = <&cpg SH7750_CPG_SCIF_CLK>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
status = "disabled";
and add
&scif1 {
status = "okay";
};
to each board .dts file that uses scif1.
> + };
> + pcic: pci@fe200000 {
> + compatible = "renesas,pci-sh7751";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + bus-range = <0 0>;
> + ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
> + <0x01000000 0 0x00000000 0xfe240000 0 0x00040000>;
> + reg = <0xfe200000 0x0400>,
> + <0x0c000000 0x04000000>,
> + <0xff800000 0x0030>;
status = "disabled";
and add
&pcic {
status = "okay";
};
to each board .dts file that uses pcic.
> + };
> + };
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (25 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 26/35] arch/sh/boot/dts: SH7751R SoC Internal peripheral definition dtsi Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-18 18:43 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d Yoshinori Sato
` (8 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 573578db9509..2179a9d61e6a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -657,6 +657,8 @@ patternProperties:
description: Inventec
"^inversepath,.*":
description: Inverse Path
+ "^iodata,.*":
+ description: IO DATA DEVICE Inc.
"^iom,.*":
description: Iomega Corporation
"^irondevice,.*":
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc.
2023-10-14 14:54 ` [RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc Yoshinori Sato
@ 2023-10-18 18:43 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 18:43 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
Please use a one-line prefix that matches the history of the file:
dt-bindings: vendor-prefixes: Add IO DATA DEVICE Inc.
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -657,6 +657,8 @@ patternProperties:
> description: Inventec
> "^inversepath,.*":
> description: Inverse Path
> + "^iodata,.*":
> + description: IO DATA DEVICE Inc.
> "^iom,.*":
> description: Iomega Corporation
> "^irondevice,.*":
For the actual change:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (26 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 27/35] Documentation/devicetree/bindings: vendor-prefix add IO DATA DEVICE Inc Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-15 22:25 ` Damien Le Moal
2023-10-14 14:54 ` [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target Yoshinori Sato
` (7 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, dlemoal, robh+dt,
krzysztof.kozlowski+dt, conor+dt, linux-ide, devicetree
usl-5p and rts7751r2d using ata-generic driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml
index 0697927f3d7e..1025b3b351d0 100644
--- a/Documentation/devicetree/bindings/ata/ata-generic.yaml
+++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml
@@ -18,6 +18,8 @@ properties:
- enum:
- arm,vexpress-cf
- fsl,mpc8349emitx-pata
+ - iodata,usl-5p-ata
+ - renesas,rts7751r2d-ata
- const: ata-generic
reg:
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d.
2023-10-14 14:54 ` [RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d Yoshinori Sato
@ 2023-10-15 22:25 ` Damien Le Moal
0 siblings, 0 replies; 88+ messages in thread
From: Damien Le Moal @ 2023-10-15 22:25 UTC (permalink / raw)
To: Yoshinori Sato, linux-sh
Cc: glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt, linux-ide,
devicetree
The patch title should be something like:
dt-bindings: ata: ata-generic: add usl-5p and rts7751r2d
without a period at the end.
On 10/14/23 23:54, Yoshinori Sato wrote:
> usl-5p and rts7751r2d using ata-generic driver.
Please use a full sentence. There is no verb here.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> Documentation/devicetree/bindings/ata/ata-generic.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ata/ata-generic.yaml b/Documentation/devicetree/bindings/ata/ata-generic.yaml
> index 0697927f3d7e..1025b3b351d0 100644
> --- a/Documentation/devicetree/bindings/ata/ata-generic.yaml
> +++ b/Documentation/devicetree/bindings/ata/ata-generic.yaml
> @@ -18,6 +18,8 @@ properties:
> - enum:
> - arm,vexpress-cf
> - fsl,mpc8349emitx-pata
> + - iodata,usl-5p-ata
> + - renesas,rts7751r2d-ata
> - const: ata-generic
>
> reg:
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (27 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 28/35] Documentation/devicetree/bindings/ata: ata-generic.yaml add usl-5p and rts7751r2d Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-18 18:48 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree Yoshinori Sato
` (6 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Renesas SuperH based target definition.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../devicetree/bindings/soc/renesas/sh.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/sh.yaml
diff --git a/Documentation/devicetree/bindings/soc/renesas/sh.yaml b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
new file mode 100644
index 000000000000..3fbff2532ad3
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SuperH Platform
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: RTS7751R2D Plus
+ items:
+ - enum:
+ - renesas,rts7751r2d # Renesas SH4 2D graphics board
+ - const: renesas,sh7751r
+
+ - description: Julian board
+ items:
+ - enum:
+ - iodata,landisk # LANDISK HDL-U
+ - iodata,usl-5p # USL-5P
+ - const: renesas,sh7751r
+
+additionalProperties: true
+
+...
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.
2023-10-14 14:54 ` [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target Yoshinori Sato
@ 2023-10-18 18:48 ` Geert Uytterhoeven
2023-10-18 18:49 ` Geert Uytterhoeven
2023-10-18 19:44 ` Geert Uytterhoeven
0 siblings, 2 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 18:48 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas SuperH based target definition.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
Please use a one-line prefix that matches the history of the other
files next to it:
dt-bindings: soc: renesas: Document SH7751 based targets
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> @@ -0,0 +1,32 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SuperH Platform
> +
> +maintainers:
> + - Yoshinori Sato <ysato@users.sourceforge.jp>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: RTS7751R2D Plus
> + items:
> + - enum:
> + - renesas,rts7751r2d # Renesas SH4 2D graphics board
> + - const: renesas,sh7751r
> +
> + - description: Julian board
> + items:
> + - enum:
> + - iodata,landisk # LANDISK HDL-U
> + - iodata,usl-5p # USL-5P
These depend on "[RFC PATCH v3 27/35] Documentation/devicetree/bindings:
vendor-prefix add IO DATA DEVICE Inc.", so that patch should be moved
forward in the series.
> + - const: renesas,sh7751r
Please merge both sections, as they use the same number of compatible
values and the same fallback.
> +
> +additionalProperties: true
> +
> +...
> --
> 2.39.2
>
--
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.
2023-10-18 18:48 ` Geert Uytterhoeven
@ 2023-10-18 18:49 ` Geert Uytterhoeven
2023-10-18 19:44 ` Geert Uytterhoeven
1 sibling, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 18:49 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > + - iodata,landisk # LANDISK HDL-U
> > + - iodata,usl-5p # USL-5P
>
> These depend on "[RFC PATCH v3 27/35] Documentation/devicetree/bindings:
> vendor-prefix add IO DATA DEVICE Inc.", so that patch should be moved
My apologies. Somehow the patches didn't end up in the right order
in my mailbox, so please ignore this comment.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.
2023-10-18 18:48 ` Geert Uytterhoeven
2023-10-18 18:49 ` Geert Uytterhoeven
@ 2023-10-18 19:44 ` Geert Uytterhoeven
2023-10-25 11:58 ` Yoshinori Sato
2023-10-25 12:05 ` Yoshinori Sato
1 sibling, 2 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-18 19:44 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > Renesas SuperH based target definition.
> >
> > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> > @@ -0,0 +1,32 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas SuperH Platform
> > +
> > +maintainers:
> > + - Yoshinori Sato <ysato@users.sourceforge.jp>
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > + - description: RTS7751R2D Plus
> > + items:
> > + - enum:
> > + - renesas,rts7751r2d # Renesas SH4 2D graphics board
> > + - const: renesas,sh7751r
> > +
> > + - description: Julian board
> > + items:
> > + - enum:
> > + - iodata,landisk # LANDISK HDL-U
> > + - iodata,usl-5p # USL-5P
> > + - const: renesas,sh7751r
>
> Please merge both sections, as they use the same number of compatible
> values and the same fallback.
Unless we want to add an "renesas,sh7380" intermediate, as that is
the actual SoC in the landisk? I do not know what is the difference
between SH7380 and SH7751R.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.
2023-10-18 19:44 ` Geert Uytterhoeven
@ 2023-10-25 11:58 ` Yoshinori Sato
2023-10-25 12:05 ` Yoshinori Sato
1 sibling, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-25 11:58 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
On Thu, 19 Oct 2023 04:44:12 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Renesas SuperH based target definition.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> > > @@ -0,0 +1,32 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas SuperH Platform
> > > +
> > > +maintainers:
> > > + - Yoshinori Sato <ysato@users.sourceforge.jp>
> > > +
> > > +properties:
> > > + $nodename:
> > > + const: '/'
> > > + compatible:
> > > + oneOf:
> > > + - description: RTS7751R2D Plus
> > > + items:
> > > + - enum:
> > > + - renesas,rts7751r2d # Renesas SH4 2D graphics board
> > > + - const: renesas,sh7751r
> > > +
> > > + - description: Julian board
> > > + items:
> > > + - enum:
> > > + - iodata,landisk # LANDISK HDL-U
> > > + - iodata,usl-5p # USL-5P
> > > + - const: renesas,sh7751r
> >
> > Please merge both sections, as they use the same number of compatible
> > values and the same fallback.
>
> Unless we want to add an "renesas,sh7380" intermediate, as that is
> the actual SoC in the landisk? I do not know what is the difference
> between SH7380 and SH7751R.
Everything here is SH7751R.
I didn't include J2, so I'll add it.
Other SoCs will be added after changing to DeviceTree.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target.
2023-10-18 19:44 ` Geert Uytterhoeven
2023-10-25 11:58 ` Yoshinori Sato
@ 2023-10-25 12:05 ` Yoshinori Sato
1 sibling, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-25 12:05 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
On Thu, 19 Oct 2023 04:44:12 +0900,
Geert Uytterhoeven wrote:
>
> Hi Sato-san,
>
> On Wed, Oct 18, 2023 at 8:48 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
> > <ysato@users.sourceforge.jp> wrote:
> > > Renesas SuperH based target definition.
> > >
> > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/sh.yaml
> > > @@ -0,0 +1,32 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/soc/renesas/sh.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas SuperH Platform
> > > +
> > > +maintainers:
> > > + - Yoshinori Sato <ysato@users.sourceforge.jp>
> > > +
> > > +properties:
> > > + $nodename:
> > > + const: '/'
> > > + compatible:
> > > + oneOf:
> > > + - description: RTS7751R2D Plus
> > > + items:
> > > + - enum:
> > > + - renesas,rts7751r2d # Renesas SH4 2D graphics board
> > > + - const: renesas,sh7751r
> > > +
> > > + - description: Julian board
> > > + items:
> > > + - enum:
> > > + - iodata,landisk # LANDISK HDL-U
> > > + - iodata,usl-5p # USL-5P
> > > + - const: renesas,sh7751r
> >
> > Please merge both sections, as they use the same number of compatible
> > values and the same fallback.
>
> Unless we want to add an "renesas,sh7380" intermediate, as that is
> the actual SoC in the landisk? I do not know what is the difference
> between SH7380 and SH7751R.
Details of the SH7380 have not been released,
but the hardware appears to be the same as the SH7751R.
I checked the original firmware source, and it was treated as the
same as the SH7751R.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (28 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 29/35] Documentation/devicetree/bindings/soc/renesas/sh.yaml: Add SH7751 based target Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-19 12:13 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree Yoshinori Sato
` (5 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
Renesas RTS7751R2D Plus devicetree.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/rts7751r2dplus.dts | 157 ++++++++++++++++++++++++++++
1 file changed, 157 insertions(+)
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts b/arch/sh/boot/dts/rts7751r2dplus.dts
new file mode 100644
index 000000000000..7fc9692da257
--- /dev/null
+++ b/arch/sh/boot/dts/rts7751r2dplus.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Renesas RTS7751R2D Plus
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+ model = "Renesas RTS7715R2D Plus";
+ compatible = "renesas,rts7751r2d", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+
+ oscillator {
+ clock-frequency = <22222222>;
+ };
+
+ r2dintc: sh7751irl_encoder@a4000000 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xa4000000 0x02>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ renesas,width = <16>;
+ renesas,regtype = "enable";
+ renesas,irqbit = <11>, /* PCI INTD */
+ <9>, /* CF IDE */
+ <8>, /* CF CD */
+ <12>, /* PCI INTC */
+ <10>, /* SM501 */
+ <6>, /* KEY */
+ <5>, /* RTC ALARM */
+ <4>, /* RTC T */
+ <7>, /* SDCARD */
+ <14>, /* PCI INTA */
+ <13>, /* PCI INTB */
+ <0>, /* EXT */
+ <15>; /* TP */
+ };
+
+ display@1,0 {
+ compatible = "smi,sm501";
+ reg = <0x10000000 0x03e00000
+ 0x13e00000 0x00200000>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <4>;
+ mode = "640x480-16@60";
+ little-endian;
+ smi,devices = "usb-host","uart0";
+ interrupt-name = "sm501";
+ route = "own";
+ swap-fb-endian;
+
+ crt {
+ flags = "use_init_mode",
+ "use_hwcursor",
+ "use_hwaccel",
+ "disable_at_exit";
+ };
+
+ panel {
+ bpp = <16>;
+ edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00
+ 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60
+ 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd];
+ flags = "use_init_mode",
+ "use_hwcursor",
+ "use_hwaccel",
+ "disable_at_exit";
+ };
+ };
+
+ compact-flash@b4001000 {
+ compatible = "renesas,rts7751r2d-ata", "ata-generic";
+ reg = <0xb4001000 0x0e>, <0xb400080c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <1>;
+ };
+
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x00000000 0x02000000>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x00000000 0x00040000>;
+ };
+
+ partition@1 {
+ label = "Environemt";
+ reg = <0x00040000 0x00040000>;
+ };
+
+ partition@2 {
+ label = "Kernel";
+ reg = <0x00080000 0x001c0000>;
+ };
+
+ partition@3 {
+ label = "Flash_FS";
+ reg = <0x00240000 0x00dc0000>;
+ };
+ };
+
+ soc {
+ clock-controller@ffc00000 {
+ renesas,mode = <5>;
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,pci-sh7751";
+ interrupt-parent = <&r2dintc>;
+ renesas,bcr1 = <0x40080000>;
+ renesas,intm = <0x0000c3ff>;
+ renesas,aintm = <0x0000380f>;
+ renesas,config = <1 0xfb900047>, <4 0xab000001>;
+ renesas,mcrmask = <0x40000004>;
+
+ interrupt-map = <0x0000 0 0 1 &r2dintc 9>,
+ <0x0000 0 0 2 &r2dintc 10>,
+ <0x0000 0 0 3 &r2dintc 3>,
+ <0x0000 0 0 4 &r2dintc 0>,
+ <0x0800 0 0 1 &r2dintc 10>,
+ <0x0800 0 0 2 &r2dintc 3>,
+ <0x0800 0 0 3 &r2dintc 0>,
+ <0x0800 0 0 4 &r2dintc 9>,
+ <0x1000 0 0 1 &r2dintc 3>,
+ <0x1000 0 0 2 &r2dintc 0>,
+ <0x1000 0 0 3 &r2dintc 9>,
+ <0x1000 0 0 4 &r2dintc 10>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree.
2023-10-14 14:54 ` [RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree Yoshinori Sato
@ 2023-10-19 12:13 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 12:13 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Renesas RTS7751R2D Plus devicetree.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/sh/boot/dts/rts7751r2dplus.dts
> + oscillator {
> + clock-frequency = <22222222>;
> + };
When adding or overriding properties to/in existing device nodes,
please refer to the nodes using symbolic labels. I.e. please add
&xtal {
clock-frequency = <22222222>;
};
at the bottom of this file instead.
> + display@1,0 {
> + compatible = "smi,sm501";
> + reg = <0x10000000 0x03e00000
> + 0x13e00000 0x00200000>;
> + interrupt-parent = <&r2dintc>;
> + interrupts = <4>;
> + mode = "640x480-16@60";
> + little-endian;
> + smi,devices = "usb-host","uart0";
> + interrupt-name = "sm501";
> + route = "own";
> + swap-fb-endian;
> +
> + crt {
> + flags = "use_init_mode",
> + "use_hwcursor",
> + "use_hwaccel",
> + "disable_at_exit";
"make dtbs_check" does not like flags being non-integer.
Might be an artefact of having only plain text bindings in
Documentation/devicetree/bindings/display/sm501fb.txt
> + };
> +
> + panel {
> + bpp = <16>;
> + edid = [00 ff ff ff ff ff ff 00 00 00 00 00 00 00 00 00
> + 00 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00
> + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> + 00 00 00 00 00 00 f0 0a 80 fb 20 e0 25 10 32 60
> + 02 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00
> + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bd];
> + flags = "use_init_mode",
> + "use_hwcursor",
> + "use_hwaccel",
> + "disable_at_exit";
Likewise.
> + };
> + };
> +
> + compact-flash@b4001000 {
> + compatible = "renesas,rts7751r2d-ata", "ata-generic";
> + reg = <0xb4001000 0x0e>, <0xb400080c 2>;
> + reg-shift = <1>;
> + interrupt-parent = <&r2dintc>;
> + interrupts = <1>;
> + };
> +
> + flash@0 {
> + compatible = "cfi-flash";
> + reg = <0x00000000 0x02000000>;
> + device-width = <2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "U-Boot";
> + reg = <0x00000000 0x00040000>;
> + };
> +
> + partition@1 {
> + label = "Environemt";
Environment
> + reg = <0x00040000 0x00040000>;
> + };
> +
> + partition@2 {
> + label = "Kernel";
> + reg = <0x00080000 0x001c0000>;
> + };
> +
> + partition@3 {
> + label = "Flash_FS";
> + reg = <0x00240000 0x00dc0000>;
> + };
> + };
> +
> + soc {
> + clock-controller@ffc00000 {
> + renesas,mode = <5>;
> + };
&cpg {
renesas,mode = <5>;
};
At the bottom of this file.
> +
> + pci@fe200000 {
Likewise, "&pcic { ... };" at the bottom of this file.
> + compatible = "renesas,pci-sh7751";
No need to override the compatible property, it is already set in
sh7751.dtsi.
> + interrupt-parent = <&r2dintc>;
> + renesas,bcr1 = <0x40080000>;
> + renesas,intm = <0x0000c3ff>;
> + renesas,aintm = <0x0000380f>;
> + renesas,config = <1 0xfb900047>, <4 0xab000001>;
> + renesas,mcrmask = <0x40000004>;
> +
> + interrupt-map = <0x0000 0 0 1 &r2dintc 9>,
> + <0x0000 0 0 2 &r2dintc 10>,
> + <0x0000 0 0 3 &r2dintc 3>,
> + <0x0000 0 0 4 &r2dintc 0>,
> + <0x0800 0 0 1 &r2dintc 10>,
> + <0x0800 0 0 2 &r2dintc 3>,
> + <0x0800 0 0 3 &r2dintc 0>,
> + <0x0800 0 0 4 &r2dintc 9>,
> + <0x1000 0 0 1 &r2dintc 3>,
> + <0x1000 0 0 2 &r2dintc 0>,
> + <0x1000 0 0 3 &r2dintc 9>,
> + <0x1000 0 0 4 &r2dintc 10>;
> + interrupt-map-mask = <0x1800 0 0 7>;
> + };
> + };
> +};
Some of my comments apply to landisk.dts and usl-5p.dts, too.
And please run "make dtbs_check" ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (29 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 30/35] arch/sh/boot/dts: RTS7751R2D Plus DeviceTree Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-19 12:14 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 32/35] arch/sh/boot/dts: USL-5P DeviceTree Yoshinori Sato
` (4 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
IO DATA Device LANDISK devicetree.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/landisk.dts | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 arch/sh/boot/dts/landisk.dts
diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index 000000000000..bcbaf5e4af13
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE LANDISK
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sh7750.h>
+#include "sh7751r.dtsi"
+
+/ {
+ model = "IO DATA Device LANDISK";
+ compatible = "iodata,landisk", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+
+ julianintc: sh7751irl_encoder@b0000005 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb0000005 0x01>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ renesas,width = <8>;
+ renesas,regtype = "enable";
+ renesas,irqbit = <0xffffffff>, /* Not use */
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0>, /* PCI INTA */
+ <1>, /* PCI INTB */
+ <2>, /* PCI INTC */
+ <3>, /* PCI INTD */
+ <4>, /* ATA */
+ <5>, /* CF */
+ <6>, /* Power Switch */
+ <7>; /* Button */
+ };
+
+ oscillator {
+ clock-frequency = <22222222>;
+ };
+
+ soc {
+ clock-controller@ffc00000 {
+ renesas,mode = <5>;
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,pci-sh7751";
+ renesas,bcr1 = <0x00080000>;
+ renesas,config = <6 0xd0000000>;
+ renesas,mcrmask = <0x40000004>;
+ interrupt-map = <0x0000 0 0 1 &julianintc 5>,
+ <0x0000 0 0 2 &julianintc 6>,
+ <0x0000 0 0 3 &julianintc 7>,
+ <0x0000 0 0 4 &julianintc 8>,
+ <0x0800 0 0 1 &julianintc 6>,
+ <0x0800 0 0 2 &julianintc 7>,
+ <0x0800 0 0 3 &julianintc 8>,
+ <0x0800 0 0 4 &julianintc 5>,
+ <0x1000 0 0 1 &julianintc 7>,
+ <0x1000 0 0 2 &julianintc 8>,
+ <0x1000 0 0 3 &julianintc 5>,
+ <0x1000 0 0 4 &julianintc 6>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree.
2023-10-14 14:54 ` [RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree Yoshinori Sato
@ 2023-10-19 12:14 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 12:14 UTC (permalink / raw)
To: Yoshinori Sato
Cc: linux-sh, glaubitz, robh+dt, krzysztof.kozlowski+dt, conor+dt,
devicetree
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> IO DATA Device LANDISK devicetree.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/sh/boot/dts/landisk.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the IO DATA DEVICE LANDISK
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/clock/sh7750.h>
This include can be dropped, as it is already included by sh7751r.dtsi.
> +#include "sh7751r.dtsi"
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 32/35] arch/sh/boot/dts: USL-5P DeviceTree.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (30 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 31/35] arch/sh/boot/dts: LANDISK DeviceTree Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-14 14:54 ` [RFC PATCH v3 33/35] arch/sh: Add dtbs target support Yoshinori Sato
` (3 subsequent siblings)
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh
Cc: Yoshinori Sato, glaubitz, robh+dt, krzysztof.kozlowski+dt,
conor+dt, devicetree
IO DATA Device USL-5P devicetree.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/usl-5p.dts | 88 +++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 arch/sh/boot/dts/usl-5p.dts
diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts
new file mode 100644
index 000000000000..ce5320348140
--- /dev/null
+++ b/arch/sh/boot/dts/usl-5p.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the IO DATA DEVICE USL-5P
+ */
+
+/dts-v1/;
+
+#include "sh7751r.dtsi"
+
+/ {
+ model = "IO-DATA Device USL-5P";
+ compatible = "iodata,usl-5p", "renesas,sh7751r";
+
+ aliases {
+ serial0 = &scif1;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+
+ julianintc: sh7751irl_encoder@b0000005 {
+ compatible = "renesas,sh7751-irl-ext";
+ reg = <0xb0000005 0x01>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ renesas,width = <8>;
+ renesas,regtype = "enable";
+ renesas,irqbit = <0xffffffff>, /* Not use */
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0xffffffff>,
+ <0>, /* PCI INTA */
+ <1>, /* PCI INTB */
+ <2>, /* PCI INTC */
+ <3>, /* PCI INTD */
+ <4>, /* ATA */
+ <5>, /* CF */
+ <6>, /* Power Switch */
+ <7>; /* Button */
+ };
+
+ oscillator {
+ clock-frequency = <22222222>;
+ };
+
+ compact-flash@b4001000 {
+ compatible = "iodata,usl-5p-ata", "ata-generic";
+ reg = <0xb4000040 0x0e>, <0xb400002c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&julianintc>;
+ interrupts = <10>;
+ };
+
+ soc {
+ clock-controller@ffc00000 {
+ renesas,mode = <5>;
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,pci-sh7751";
+ renesas,bcr1 = <0x00080000>;
+ renesas,config = <6 0xd0000000>;
+ renesas,mcrmask = <0x40000004>;
+ interrupt-map = <0x0000 0 0 1 &julianintc 5>,
+ <0x0000 0 0 2 &julianintc 6>,
+ <0x0000 0 0 3 &julianintc 7>,
+ <0x0000 0 0 4 &julianintc 8>,
+ <0x0800 0 0 1 &julianintc 6>,
+ <0x0800 0 0 2 &julianintc 7>,
+ <0x0800 0 0 3 &julianintc 8>,
+ <0x0800 0 0 4 &julianintc 5>,
+ <0x1000 0 0 1 &julianintc 7>,
+ <0x1000 0 0 2 &julianintc 8>,
+ <0x1000 0 0 3 &julianintc 5>,
+ <0x1000 0 0 4 &julianintc 6>;
+ interrupt-map-mask = <0x1800 0 0 7>;
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 33/35] arch/sh: Add dtbs target support.
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (31 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 32/35] arch/sh/boot/dts: USL-5P DeviceTree Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-19 11:54 ` Geert Uytterhoeven
2023-10-14 14:54 ` [RFC PATCH v3 34/35] arch/sh: RTS7751R2D Plus OF defconfig Yoshinori Sato
` (2 subsequent siblings)
35 siblings, 1 reply; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/Makefile | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile
index 4a6dec9714a9..e6b93360c213 100644
--- a/arch/sh/boot/dts/Makefile
+++ b/arch/sh/boot/dts/Makefile
@@ -1,2 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE))
+
+dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb
+dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb
+dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb
+dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 33/35] arch/sh: Add dtbs target support.
2023-10-14 14:54 ` [RFC PATCH v3 33/35] arch/sh: Add dtbs target support Yoshinori Sato
@ 2023-10-19 11:54 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2023-10-19 11:54 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh, glaubitz
Hi Sato-san,
On Sat, Oct 14, 2023 at 4:54 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> --- a/arch/sh/boot/dts/Makefile
> +++ b/arch/sh/boot/dts/Makefile
> @@ -1,2 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_USE_BUILTIN_DTB) += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_SOURCE))
> +
> +dtb-$(CONFIG_CPU_J2) += j2_mimas_v2.dtb
Please keep this a separate patch, and move it forward in the series
(or submit it independently).
> +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += landisk.dtb
This change should be moved into "[RFC PATCH v3 31/35] arch/sh/boot/dts:
LANDISK DeviceTree.".
> +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += rts7751r2dplus.dtb
This change should be moved into "[RFC PATCH v3 30/35] arch/sh/boot/dts:
RTS7751R2D Plus DeviceTree.".
> +dtb-$(CONFIG_CPU_SUBTYPE_SH7751R) += usl-5p.dtb
This change should be moved into "[RFC PATCH v3 32/35] arch/sh/boot/dts:
USL-5P DeviceTree.".
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [RFC PATCH v3 34/35] arch/sh: RTS7751R2D Plus OF defconfig
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (32 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 33/35] arch/sh: Add dtbs target support Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-10-14 14:54 ` [RFC PATCH v3 35/35] arch/sh/configs: LANDISK " Yoshinori Sato
2023-11-07 10:23 ` [RFC PATCH v3 00/35] Device Tree support for SH7751 based board John Paul Adrian Glaubitz
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/configs/rts7751r2dplus-of_defconfig | 92 +++++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
diff --git a/arch/sh/configs/rts7751r2dplus-of_defconfig b/arch/sh/configs/rts7751r2dplus-of_defconfig
new file mode 100644
index 000000000000..d62eed4cccee
--- /dev/null
+++ b/arch/sh/configs/rts7751r2dplus-of_defconfig
@@ -0,0 +1,92 @@
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_EXPERT=y
+CONFIG_PROFILING=y
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_SH_OF_BOARD=y
+CONFIG_HEARTBEAT=y
+CONFIG_MODULES=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_PCI=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_PCI_SH7751=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ATA=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_SCI=y
+CONFIG_MFD_SM501=y
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=m
+CONFIG_FB_SM501=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=m
+CONFIG_SND_YMFPCI=m
+CONFIG_HID_A4TECH=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_R9701=y
+CONFIG_RENESAS_SH7751_INTC=y
+CONFIG_RENESAS_SH7751IRL_INTC=y
+CONFIG_EXT2_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_MINIX_FS=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_CRC_T10DIF=y
+CONFIG_DEBUG_FS=y
+# CONFIG_FTRACE is not set
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* [RFC PATCH v3 35/35] arch/sh/configs: LANDISK OF defconfig
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (33 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 34/35] arch/sh: RTS7751R2D Plus OF defconfig Yoshinori Sato
@ 2023-10-14 14:54 ` Yoshinori Sato
2023-11-07 10:23 ` [RFC PATCH v3 00/35] Device Tree support for SH7751 based board John Paul Adrian Glaubitz
35 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-10-14 14:54 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato, glaubitz
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/configs/landisk-of_defconfig | 111 +++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 arch/sh/configs/landisk-of_defconfig
diff --git a/arch/sh/configs/landisk-of_defconfig b/arch/sh/configs/landisk-of_defconfig
new file mode 100644
index 000000000000..406de7d7b8a2
--- /dev/null
+++ b/arch/sh/configs/landisk-of_defconfig
@@ -0,0 +1,111 @@
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_EXPERT=y
+CONFIG_KEXEC=y
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_SH_OF_BOARD=y
+CONFIG_HEARTBEAT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_ATALK=m
+CONFIG_PCI=y
+CONFIG_PCI_SH7751=y
+CONFIG_PCCARD=y
+CONFIG_YENTA=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ATA=y
+CONFIG_PATA_ARTOP=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_ATA_GENERIC=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_NETDEVICES=y
+CONFIG_TUN=m
+CONFIG_8139CP=y
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_HW_RANDOM=y
+CONFIG_SOUND=m
+CONFIG_HID_A4TECH=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_USB_HID=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_SISUSBVGA=m
+CONFIG_RENESAS_SH7751_INTC=y
+CONFIG_RENESAS_SH7751IRL_INTC=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_REISERFS_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_UFS_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFSD=m
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_CRC_T10DIF=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_SH_STANDARD_BIOS=y
--
2.39.2
^ permalink raw reply related [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 00/35] Device Tree support for SH7751 based board
2023-10-14 14:53 [RFC PATCH v3 00/35] Device Tree support for SH7751 based board Yoshinori Sato
` (34 preceding siblings ...)
2023-10-14 14:54 ` [RFC PATCH v3 35/35] arch/sh/configs: LANDISK " Yoshinori Sato
@ 2023-11-07 10:23 ` John Paul Adrian Glaubitz
2023-11-08 7:57 ` Yoshinori Sato
35 siblings, 1 reply; 88+ messages in thread
From: John Paul Adrian Glaubitz @ 2023-11-07 10:23 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh
Hi Yoshinori!
On Sat, 2023-10-14 at 23:53 +0900, Yoshinori Sato wrote:
> This is an updated version of something I wrote about 7 years ago.
> Minimum support for R2D-plus and LANDISK.
> I think R2D-1 will work if you add AX88796 to dts.
> And board-specific functions and SCI's SPI functions are not supported.
I tried to apply this series against both 6.5 and 6.6 and it unfortunately
fails. git also claims that one of the patches is empty.
Could you rebase your series against 6.7-rc1 once it's out?
In the mean time, I will add comments to the v3 series of your patches.
Adrian
--
.''`. John Paul Adrian Glaubitz
: :' : Debian Developer
`. `' Physicist
`- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
^ permalink raw reply [flat|nested] 88+ messages in thread* Re: [RFC PATCH v3 00/35] Device Tree support for SH7751 based board
2023-11-07 10:23 ` [RFC PATCH v3 00/35] Device Tree support for SH7751 based board John Paul Adrian Glaubitz
@ 2023-11-08 7:57 ` Yoshinori Sato
0 siblings, 0 replies; 88+ messages in thread
From: Yoshinori Sato @ 2023-11-08 7:57 UTC (permalink / raw)
To: John Paul Adrian Glaubitz; +Cc: linux-sh
On Tue, 07 Nov 2023 19:23:22 +0900,
John Paul Adrian Glaubitz wrote:
>
> Hi Yoshinori!
>
> On Sat, 2023-10-14 at 23:53 +0900, Yoshinori Sato wrote:
> > This is an updated version of something I wrote about 7 years ago.
> > Minimum support for R2D-plus and LANDISK.
> > I think R2D-1 will work if you add AX88796 to dts.
> > And board-specific functions and SCI's SPI functions are not supported.
>
> I tried to apply this series against both 6.5 and 6.6 and it unfortunately
> fails. git also claims that one of the patches is empty.
>
> Could you rebase your series against 6.7-rc1 once it's out?
Yes. I know that some changes are conflicting.
I was able to fix the comments for v3, so I will send a patch for v4
after importing v6.7-rc1.
> In the mean time, I will add comments to the v3 series of your patches.
>
> Adrian
>
> --
> .''`. John Paul Adrian Glaubitz
> : :' : Debian Developer
> `. `' Physicist
> `- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
--
Yosinori Sato
^ permalink raw reply [flat|nested] 88+ messages in thread