* [PATCH 3/3] ARM: mach-shmobile: sh7372 A4R support (v4)
From: Rafael J. Wysocki @ 2011-10-19 22:15 UTC (permalink / raw)
To: Linux-sh list; +Cc: Linux PM list, Linux Kernel, Magnus Damm
In-Reply-To: <201110200012.43840.rjw@sisk.pl>
From: Magnus Damm <damm@opensource.se>
This change adds support for the sh7372 A4R power domain.
The sh7372 A4R hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.
One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
---
arch/arm/mach-shmobile/board-ap4evb.c | 1
arch/arm/mach-shmobile/board-mackerel.c | 1
arch/arm/mach-shmobile/include/mach/sh7372.h | 7 +++
arch/arm/mach-shmobile/intc-sh7372.c | 52 ++++++++++++++++++++++++++-
arch/arm/mach-shmobile/pm-sh7372.c | 29 ++++++++++++++-
arch/arm/mach-shmobile/setup-sh7372.c | 8 ++++
6 files changed, 96 insertions(+), 2 deletions(-)
Index: linux/arch/arm/mach-shmobile/board-ap4evb.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-ap4evb.c
+++ linux/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1412,6 +1412,7 @@ static void __init ap4evb_init(void)
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
hdmi_init_pm_clock();
fsi_init_pm_clock();
Index: linux/arch/arm/mach-shmobile/board-mackerel.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-mackerel.c
+++ linux/arch/arm/mach-shmobile/board-mackerel.c
@@ -1596,6 +1596,7 @@ static void __init mackerel_init(void)
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
#endif
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
hdmi_init_pm_clock();
sh7372_pm_init();
Index: linux/arch/arm/mach-shmobile/include/mach/sh7372.h
=================================--- linux.orig/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ linux/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -480,8 +480,11 @@ struct platform_device;
struct sh7372_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
+ void (*suspend)(void);
+ void (*resume)(void);
unsigned int bit_shift;
bool no_debug;
+ bool stay_on;
};
static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
@@ -493,6 +496,7 @@ static inline struct sh7372_pm_domain *t
extern struct sh7372_pm_domain sh7372_a4lc;
extern struct sh7372_pm_domain sh7372_a4mp;
extern struct sh7372_pm_domain sh7372_d4;
+extern struct sh7372_pm_domain sh7372_a4r;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
extern struct sh7372_pm_domain sh7372_a3sp;
@@ -509,4 +513,7 @@ extern void sh7372_pm_add_subdomain(stru
#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
#endif /* CONFIG_PM */
+extern void sh7372_intcs_suspend(void);
+extern void sh7372_intcs_resume(void);
+
#endif /* __ASM_SH7372_H__ */
Index: linux/arch/arm/mach-shmobile/intc-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/intc-sh7372.c
+++ linux/arch/arm/mach-shmobile/intc-sh7372.c
@@ -606,9 +606,16 @@ static void intcs_demux(unsigned int irq
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
+static void __iomem *intcs_ffd2;
+static void __iomem *intcs_ffd5;
+
void __init sh7372_init_irq(void)
{
- void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ void __iomem *intevtsa;
+
+ intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
+ intevtsa = intcs_ffd2 + 0x100;
+ intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
register_intc_controller(&intca_desc);
register_intc_controller(&intcs_desc);
@@ -617,3 +624,46 @@ void __init sh7372_init_irq(void)
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
}
+
+static unsigned short ffd2[0x200];
+static unsigned short ffd5[0x100];
+
+void sh7372_intcs_suspend(void)
+{
+ int k;
+
+ for (k = 0x00; k <= 0x30; k += 4)
+ ffd2[k] = __raw_readw(intcs_ffd2 + k);
+
+ for (k = 0x80; k <= 0xb0; k += 4)
+ ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+ for (k = 0x180; k <= 0x188; k += 4)
+ ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+ for (k = 0x00; k <= 0x3c; k += 4)
+ ffd5[k] = __raw_readw(intcs_ffd5 + k);
+
+ for (k = 0x80; k <= 0x9c; k += 4)
+ ffd5[k] = __raw_readb(intcs_ffd5 + k);
+}
+
+void sh7372_intcs_resume(void)
+{
+ int k;
+
+ for (k = 0x00; k <= 0x30; k += 4)
+ __raw_writew(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x80; k <= 0xb0; k += 4)
+ __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x180; k <= 0x188; k += 4)
+ __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x00; k <= 0x3c; k += 4)
+ __raw_writew(ffd5[k], intcs_ffd5 + k);
+
+ for (k = 0x80; k <= 0x9c; k += 4)
+ __raw_writeb(ffd5[k], intcs_ffd5 + k);
+}
Index: linux/arch/arm/mach-shmobile/pm-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/pm-sh7372.c
+++ linux/arch/arm/mach-shmobile/pm-sh7372.c
@@ -44,6 +44,7 @@
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define SBAR 0xe6180020
+#define WUPRMSK 0xe6180028
#define WUPSMSK 0xe618002c
#define WUPSMSK2 0xe6180048
#define PSTR 0xe6180080
@@ -80,6 +81,12 @@ static int pd_power_down(struct generic_
struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
unsigned int mask = 1 << sh7372_pd->bit_shift;
+ if (sh7372_pd->suspend)
+ sh7372_pd->suspend();
+
+ if (sh7372_pd->stay_on)
+ return 0;
+
if (__raw_readl(PSTR) & mask) {
unsigned int retry_count;
@@ -106,6 +113,9 @@ static int pd_power_up(struct generic_pm
unsigned int retry_count;
int ret = 0;
+ if (sh7372_pd->stay_on)
+ goto out;
+
if (__raw_readl(PSTR) & mask)
goto out;
@@ -122,14 +132,23 @@ static int pd_power_up(struct generic_pm
if (__raw_readl(SWUCR) & mask)
ret = -EIO;
- out:
if (!sh7372_pd->no_debug)
pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
mask, __raw_readl(PSTR));
+ out:
+ if (ret = 0 && sh7372_pd->resume)
+ sh7372_pd->resume();
+
return ret;
}
+static void sh7372_a4r_suspend(void)
+{
+ sh7372_intcs_suspend();
+ __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
+}
+
static bool pd_active_wakeup(struct device *dev)
{
return true;
@@ -186,6 +205,14 @@ struct sh7372_pm_domain sh7372_d4 = {
.bit_shift = 3,
};
+struct sh7372_pm_domain sh7372_a4r = {
+ .bit_shift = 5,
+ .gov = &sh7372_always_on_gov,
+ .suspend = sh7372_a4r_suspend,
+ .resume = sh7372_intcs_resume,
+ .stay_on = true,
+};
+
struct sh7372_pm_domain sh7372_a3rv = {
.bit_shift = 6,
};
Index: linux/arch/arm/mach-shmobile/setup-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/setup-sh7372.c
+++ linux/arch/arm/mach-shmobile/setup-sh7372.c
@@ -991,12 +991,14 @@ void __init sh7372_add_standard_devices(
sh7372_init_pm_domain(&sh7372_a4lc);
sh7372_init_pm_domain(&sh7372_a4mp);
sh7372_init_pm_domain(&sh7372_d4);
+ sh7372_init_pm_domain(&sh7372_a4r);
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a3sg);
sh7372_init_pm_domain(&sh7372_a3sp);
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
+ sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices));
@@ -1020,6 +1022,12 @@ void __init sh7372_add_standard_devices(
sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
}
void __init sh7372_add_early_devices(void)
^ permalink raw reply
* [PATCH 2/3] ARM: mach-shmobile: sh7372 A3SP support (v4)
From: Rafael J. Wysocki @ 2011-10-19 22:14 UTC (permalink / raw)
To: Linux-sh list; +Cc: Linux PM list, Linux Kernel, Magnus Damm
In-Reply-To: <201110200012.43840.rjw@sisk.pl>
From: Magnus Damm <damm@opensource.se>
This change adds support for the sh7372 A3SP power domain.
The sh7372 A3SP hardware power domain contains a
wide range of I/O devices. The list of I/O devices
include SCIF serial ports, DMA Engine hardware,
SD and MMC controller hardware, USB controllers
and I2C master controllers.
This patch adds the A3SP low level code which
powers the hardware power domain on and off. It
also ties in platform devices to the pm domain
support code.
It is worth noting that the serial console is
hooked up to SCIFA0 on most sh7372 boards, and
the SCIFA0 port is included in the A3SP hardware
power domain. For this reason we cannot output
debug messages from the low level power control
code in the case of A3SP.
QoS support is needed in drivers before we can
enable the A3SP power control on the fly.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
---
arch/arm/mach-shmobile/board-ap4evb.c | 4 +++
arch/arm/mach-shmobile/board-mackerel.c | 8 +++++++
arch/arm/mach-shmobile/include/mach/sh7372.h | 3 ++
arch/arm/mach-shmobile/pm-sh7372.c | 30 ++++++++++++++++++++++-----
arch/arm/mach-shmobile/setup-sh7372.c | 14 ++++++++++++
5 files changed, 54 insertions(+), 5 deletions(-)
Index: linux/arch/arm/mach-shmobile/board-ap4evb.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-ap4evb.c
+++ linux/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1409,6 +1409,10 @@ static void __init ap4evb_init(void)
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+
hdmi_init_pm_clock();
fsi_init_pm_clock();
sh7372_pm_init();
Index: linux/arch/arm/mach-shmobile/board-mackerel.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-mackerel.c
+++ linux/arch/arm/mach-shmobile/board-mackerel.c
@@ -1588,6 +1588,14 @@ static void __init mackerel_init(void)
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+#endif
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
hdmi_init_pm_clock();
sh7372_pm_init();
Index: linux/arch/arm/mach-shmobile/include/mach/sh7372.h
=================================--- linux.orig/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ linux/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -479,7 +479,9 @@ struct platform_device;
struct sh7372_pm_domain {
struct generic_pm_domain genpd;
+ struct dev_power_governor *gov;
unsigned int bit_shift;
+ bool no_debug;
};
static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
@@ -493,6 +495,7 @@ extern struct sh7372_pm_domain sh7372_a4
extern struct sh7372_pm_domain sh7372_d4;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
+extern struct sh7372_pm_domain sh7372_a3sp;
extern struct sh7372_pm_domain sh7372_a3sg;
extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
Index: linux/arch/arm/mach-shmobile/pm-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/pm-sh7372.c
+++ linux/arch/arm/mach-shmobile/pm-sh7372.c
@@ -92,8 +92,9 @@ static int pd_power_down(struct generic_
}
}
- pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+ if (!sh7372_pd->no_debug)
+ pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
+ mask, __raw_readl(PSTR));
return 0;
}
@@ -122,8 +123,9 @@ static int pd_power_up(struct generic_pm
ret = -EIO;
out:
- pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+ if (!sh7372_pd->no_debug)
+ pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
+ mask, __raw_readl(PSTR));
return ret;
}
@@ -133,11 +135,20 @@ static bool pd_active_wakeup(struct devi
return true;
}
+static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain)
+{
+ return false;
+}
+
+struct dev_power_governor sh7372_always_on_gov = {
+ .power_down_ok = sh7372_power_down_forbidden,
+};
+
void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
{
struct generic_pm_domain *genpd = &sh7372_pd->genpd;
- pm_genpd_init(genpd, NULL, false);
+ pm_genpd_init(genpd, sh7372_pd->gov, false);
genpd->stop_device = pm_clk_suspend;
genpd->start_device = pm_clk_resume;
genpd->dev_irq_safe = true;
@@ -183,6 +194,12 @@ struct sh7372_pm_domain sh7372_a3ri = {
.bit_shift = 8,
};
+struct sh7372_pm_domain sh7372_a3sp = {
+ .bit_shift = 11,
+ .gov = &sh7372_always_on_gov,
+ .no_debug = true,
+};
+
struct sh7372_pm_domain sh7372_a3sg = {
.bit_shift = 13,
};
@@ -422,6 +439,9 @@ void __init sh7372_pm_init(void)
__raw_writel(0x0000a501, DBGREG9);
__raw_writel(0x00000000, DBGREG1);
+ /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
+ __raw_writel(0, PDNSEL);
+
sh7372_suspend_init();
sh7372_cpuidle_init();
}
Index: linux/arch/arm/mach-shmobile/setup-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/setup-sh7372.c
+++ linux/arch/arm/mach-shmobile/setup-sh7372.c
@@ -994,6 +994,7 @@ void __init sh7372_add_standard_devices(
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a3sg);
+ sh7372_init_pm_domain(&sh7372_a3sp);
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
@@ -1006,6 +1007,19 @@ void __init sh7372_add_standard_devices(
sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
}
void __init sh7372_add_early_devices(void)
^ permalink raw reply
* [PATCH 1/3] PM / Sleep: Mark devices involved in wakeup signaling during suspend
From: Rafael J. Wysocki @ 2011-10-19 22:13 UTC (permalink / raw)
To: Linux-sh list; +Cc: Linux PM list, Linux Kernel, Magnus Damm
In-Reply-To: <201110200012.43840.rjw@sisk.pl>
From: Rafael J. Wysocki <rjw@sisk.pl>
The generic PM domains code in drivers/base/power/domain.c has
to avoid powering off domains that provide power to wakeup devices
during system suspend. Currently, however, this only works for
wakeup devices directly belonging to the given domain and not for
their children (or the children of their children and so on).
Thus, if there's a wakeup device whose parent belongs to a power
domain handled by the generic PM domains code, the domain will be
powered off during system suspend preventing the device from
signaling wakeup.
To address this problem introduce a device flag, power.wakeup_path,
that will be set during system suspend for all wakeup devices,
their parents, the parents of their parents and so on. This way,
all wakeup paths in the device hierarchy will be marked and the
generic PM domains code will only need to avoid powering off
domains containing devices whose power.wakeup_path is set.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
---
drivers/base/power/domain.c | 4 ++--
drivers/base/power/main.c | 8 +++++++-
include/linux/pm.h | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
Index: linux/drivers/base/power/domain.c
=================================--- linux.orig/drivers/base/power/domain.c
+++ linux/drivers/base/power/domain.c
@@ -714,7 +714,7 @@ static int pm_genpd_suspend_noirq(struct
if (ret)
return ret;
- if (device_may_wakeup(dev)
+ if (dev->power.wakeup_path
&& genpd->active_wakeup && genpd->active_wakeup(dev))
return 0;
@@ -938,7 +938,7 @@ static int pm_genpd_dev_poweroff_noirq(s
if (ret)
return ret;
- if (device_may_wakeup(dev)
+ if (dev->power.wakeup_path
&& genpd->active_wakeup && genpd->active_wakeup(dev))
return 0;
Index: linux/drivers/base/power/main.c
=================================--- linux.orig/drivers/base/power/main.c
+++ linux/drivers/base/power/main.c
@@ -917,7 +917,11 @@ static int __device_suspend(struct devic
}
End:
- dev->power.is_suspended = !error;
+ if (!error) {
+ dev->power.is_suspended = true;
+ if (dev->power.wakeup_path && dev->parent)
+ dev->parent->power.wakeup_path = true;
+ }
device_unlock(dev);
complete_all(&dev->power.completion);
@@ -1020,6 +1024,8 @@ static int device_prepare(struct device
device_lock(dev);
+ dev->power.wakeup_path = device_may_wakeup(dev);
+
if (dev->pm_domain) {
pm_dev_dbg(dev, state, "preparing power domain ");
if (dev->pm_domain->ops.prepare)
Index: linux/include/linux/pm.h
=================================--- linux.orig/include/linux/pm.h
+++ linux/include/linux/pm.h
@@ -452,6 +452,7 @@ struct dev_pm_info {
struct list_head entry;
struct completion completion;
struct wakeup_source *wakeup;
+ bool wakeup_path:1;
#else
unsigned int should_wakeup:1;
#endif
^ permalink raw reply
* [PATCH 0/3] Support for A3SP and A4R domains on SH7372
From: Rafael J. Wysocki @ 2011-10-19 22:12 UTC (permalink / raw)
To: Linux-sh list; +Cc: Linux PM list, Linux Kernel, Magnus Damm
Hi,
Patches [2/3] and [3/3] add support for the SH7372's A3SP and A4R power
domains, respectively.
Patch [1/3] is a fix that's needed for console wakeup to work with the
A3SP domain patch.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] sh: pfc: get_config_reg() shift clean up
From: Magnus Damm @ 2011-10-17 9:01 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Clean up the f_width shift code in get_config_reg().
Reported-by: Ryusuke Sakato <ryusuke.sakato.bx@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
---
drivers/sh/pfc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- 0005/drivers/sh/pfc.c
+++ work/drivers/sh/pfc.c 2011-10-14 20:11:19.000000000 +0900
@@ -217,7 +217,7 @@ static int get_config_reg(struct pinmux_
if (!r_width)
break;
- for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
+ for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) {
if (config_reg->enum_ids[n] = enum_id) {
*crp = config_reg;
*indexp = n;
^ permalink raw reply
* [PATCH] ARM: mach-shmobile: sh73a0 and AG5EVM PINT support
From: Magnus Damm @ 2011-10-17 9:00 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Support PINT on sh73a0 and AG5EVM using INTC PINT macros.
With this patch applied the AG5EVM ethernet is handled
through one of the chained sh73a0 PINT interrupt controllers.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Depends on "[PATCH] ARM: mach-shmobile: Add support for PINT though macros"
and on "[PATCH 00/07] ARM: mach-shmobile: External IRQ pin update"
arch/arm/mach-shmobile/board-ag5evm.c | 17 ------
arch/arm/mach-shmobile/include/mach/sh73a0.h | 4 +
arch/arm/mach-shmobile/intc-sh73a0.c | 65 ++++++++++++++++++++++++++
3 files changed, 71 insertions(+), 15 deletions(-)
--- 0014/arch/arm/mach-shmobile/board-ag5evm.c
+++ work/arch/arm/mach-shmobile/board-ag5evm.c 2011-10-14 18:50:07.000000000 +0900
@@ -58,7 +58,7 @@ static struct resource smsc9220_resource
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(33), /* PINT1 */
+ .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */
.flags = IORESOURCE_IRQ,
},
};
@@ -465,19 +465,6 @@ static void __init ag5evm_map_io(void)
shmobile_setup_console();
}
-#define PINTC_ADDR 0xe6900000
-#define PINTER0A (PINTC_ADDR + 0xa0)
-#define PINTCR0A (PINTC_ADDR + 0xb0)
-
-void __init ag5evm_init_irq(void)
-{
- sh73a0_init_irq();
-
- /* setup PINT: enable PINTA2 as active low */
- __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
- __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
-}
-
#define DSI0PHYCR 0xe615006c
static void __init ag5evm_init(void)
@@ -611,7 +598,7 @@ struct sys_timer ag5evm_timer = {
MACHINE_START(AG5EVM, "ag5evm")
.map_io = ag5evm_map_io,
- .init_irq = ag5evm_init_irq,
+ .init_irq = sh73a0_init_irq,
.handle_irq = shmobile_handle_irq_gic,
.init_machine = ag5evm_init,
.timer = &ag5evm_timer,
--- 0002/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ work/arch/arm/mach-shmobile/include/mach/sh73a0.h 2011-10-14 18:50:07.000000000 +0900
@@ -507,4 +507,8 @@ enum {
SHDMA_SLAVE_MMCIF_RX,
};
+/* PINT interrupts are located at Linux IRQ 768 and up */
+#define SH73A0_PINT0_IRQ(irq) ((irq) + 768)
+#define SH73A0_PINT1_IRQ(irq) ((irq) + 800)
+
#endif /* __ASM_SH73A0_H__ */
--- 0013/arch/arm/mach-shmobile/intc-sh73a0.c
+++ work/arch/arm/mach-shmobile/intc-sh73a0.c 2011-10-17 16:52:48.000000000 +0900
@@ -23,6 +23,7 @@
#include <linux/io.h>
#include <linux/sh_intc.h>
#include <mach/intc.h>
+#include <mach/sh73a0.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -363,6 +364,59 @@ static irqreturn_t sh73a0_irq_pin_demux(
static struct irqaction sh73a0_irq_pin_cascade[32];
+#define PINTER0 0xe69000a0
+#define PINTER1 0xe69000a4
+#define PINTRR0 0xe69000d0
+#define PINTRR1 0xe69000d4
+
+#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
+#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
+#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
+#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
+#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
+
+INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \
+ INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
+ INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \
+ INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \
+ INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
+ INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
+
+INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \
+ INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
+ INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \
+ INTC_PINT_V_NONE, INTC_PINT_V_NONE, \
+ INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
+ INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
+
+static struct irqaction sh73a0_pint0_cascade;
+static struct irqaction sh73a0_pint1_cascade;
+
+static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
+{
+ unsigned long value = ioread32(rr) & ioread32(er);
+ int k;
+
+ for (k = 0; k < 32; k++) {
+ if (value & (1 << (31 - k))) {
+ generic_handle_irq(base_irq + k);
+ iowrite32(~(1 << (31 - k)), rr);
+ }
+ }
+}
+
+static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
+{
+ pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
+{
+ pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
+ return IRQ_HANDLED;
+}
+
void __init sh73a0_init_irq(void)
{
void __iomem *gic_dist_base = __io(0xf0001000);
@@ -375,6 +429,8 @@ void __init sh73a0_init_irq(void)
register_intc_controller(&intcs_desc);
register_intc_controller(&intca_irq_pins_desc);
+ register_intc_controller(&intc_pint0_desc);
+ register_intc_controller(&intc_pint1_desc);
/* demux using INTEVTSA */
sh73a0_intcs_cascade.name = "INTCS cascade";
@@ -393,4 +449,13 @@ void __init sh73a0_init_irq(void)
handle_level_irq, "level");
set_irq_flags(n, IRQF_VALID); /* yuck */
}
+
+ /* PINT pins are sanely tied to the GIC as SPI */
+ sh73a0_pint0_cascade.name = "PINT0 cascade";
+ sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
+ setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
+
+ sh73a0_pint1_cascade.name = "PINT1 cascade";
+ sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
+ setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
}
^ permalink raw reply
* [PATCH] ARM: mach-shmobile: Add support for PINT though INTC macros
From: Magnus Damm @ 2011-10-17 9:00 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Add a INTC_PINT() macro with various helper bits to allow SoCs
like sh73a0 to suppor the PINT hardware using regular INTC tables.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Depends on "[PATCH 00/07] ARM: mach-shmobile: External IRQ pin update"
arch/arm/mach-shmobile/include/mach/intc.h | 51 ++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
--- 0008/arch/arm/mach-shmobile/include/mach/intc.h
+++ work/arch/arm/mach-shmobile/include/mach/intc.h 2011-10-14 18:47:45.000000000 +0900
@@ -192,4 +192,55 @@ static struct intc_desc p ## _desc __ini
p ## _sense_registers, p ## _ack_registers) \
}
+#define INTC_PINT_E_EMPTY
+#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0,
+#define INTC_PINT_E(p) \
+ PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \
+ PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7,
+
+#define INTC_PINT_V_NONE
+#define INTC_PINT_V(p, vect) \
+ vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \
+ vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \
+ vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \
+ vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7),
+
+#define INTC_PINT(p, mask_reg, sense_base, str, \
+ enums_1, enums_2, enums_3, enums_4, \
+ vect_1, vect_2, vect_3, vect_4, \
+ mask_a, mask_b, mask_c, mask_d, \
+ sense_a, sense_b, sense_c, sense_d) \
+ \
+enum { \
+ PINT ## p ## _UNUSED = 0, \
+ enums_1 enums_2 enums_3 enums_4 \
+}; \
+ \
+static struct intc_vect p ## _vectors[] __initdata = { \
+ vect_1 vect_2 vect_3 vect_4 \
+}; \
+ \
+static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
+ { mask_reg, 0, 32, /* PINTER */ \
+ { mask_a mask_b mask_c mask_d } } \
+}; \
+ \
+static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
+ { sense_base + 0x00, 16, 2, /* PINTCR */ \
+ { sense_a } }, \
+ { sense_base + 0x04, 16, 2, /* PINTCR */ \
+ { sense_b } }, \
+ { sense_base + 0x08, 16, 2, /* PINTCR */ \
+ { sense_c } }, \
+ { sense_base + 0x0c, 16, 2, /* PINTCR */ \
+ { sense_d } }, \
+}; \
+ \
+static struct intc_desc p ## _desc __initdata = { \
+ .name = str, \
+ .hw = INTC_HW_DESC(p ## _vectors, NULL, \
+ p ## _mask_registers, NULL, \
+ p ## _sense_registers, NULL), \
+}
+
#endif /* __ASM_MACH_INTC_H */
^ permalink raw reply
* [PATCH] sh: intc: Add IRQ trigger bit field check
From: Magnus Damm @ 2011-10-17 8:59 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
R-Mobile SoCs such as sh73a0 include PINT blocks in INTC
that come with 2-bit IRQ trigger support. Add code to make
sure the bit width is checked so 4-bit only modes like for
instance EDGE_BOTH will fail for PINT.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
drivers/sh/intc/chip.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
--- 0009/drivers/sh/intc/chip.c
+++ work/drivers/sh/intc/chip.c 2011-10-14 11:52:20.000000000 +0900
@@ -202,11 +202,16 @@ static int intc_set_type(struct irq_data
if (!value)
return -EINVAL;
+ value &= ~SENSE_VALID_FLAG;
+
ihp = intc_find_irq(d->sense, d->nr_sense, irq);
if (ihp) {
+ /* PINT has 2-bit sense registers, should fail on EDGE_BOTH */
+ if (value >= (1 << _INTC_WIDTH(ihp->handle)))
+ return -EINVAL;
+
addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
- intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle,
- value & ~SENSE_VALID_FLAG);
+ intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
}
return 0;
^ permalink raw reply
* Re: [PATCH 05/21] sh: drop unused Kconfig symbol
From: Nobuhiro Iwamatsu @ 2011-10-17 2:19 UTC (permalink / raw)
To: Paul Bolle; +Cc: Paul Mundt, linux-sh, linux-kernel
In-Reply-To: <1318595280.6132.61.camel@x61.thuisdomein>
Hi,
I tested with this patch. I didn't have any problem.
Tested-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2011/10/14 Paul Bolle <pebolle@tiscali.nl>:
> Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
> ---
> arch/sh/Kconfig | 4 ----
> 1 files changed, 0 insertions(+), 4 deletions(-)
>
> diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
> index ff9177c..2d39594 100644
> --- a/arch/sh/Kconfig
> +++ b/arch/sh/Kconfig
> @@ -101,10 +101,6 @@ config GENERIC_LOCKBREAK
> def_bool y
> depends on SMP && PREEMPT
>
> -config SYS_SUPPORTS_PM
> - bool
> - depends on !SMP
> -
> config ARCH_SUSPEND_POSSIBLE
> def_bool n
>
> --
> 1.7.4.4
>
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
--
Nobuhiro Iwamatsu
^ permalink raw reply
* Re: [PATCH v2] sh: Take into account the base of System RAM in virt_to_phys()
From: Nobuhiro Iwamatsu @ 2011-10-16 23:50 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <1317603918-30762-1-git-send-email-horms@verge.net.au>
Hi,
2011/10/13 Simon Horman <horms@verge.net.au>:
> On Wed, Oct 12, 2011 at 05:24:23PM +0900, Magnus Damm wrote:
>> On Mon, Oct 3, 2011 at 10:05 AM, Simon Horman <horms@verge.net.au> wrote:
>> > Previously virt_to_phys() assumed that physical memory always started
>> > at address 0. This is not always the case.
>> >
>> > Tested on an sh7757lcr (32bit system) whose only System RAM region is
>> > 40000000-4effffff and an ecovec24 (29bit system).
>> >
>> > Signed-off-by: Simon Horman <horms@verge.net.au>
>> >
>> > ---
>> > kexec/arch/sh/kexec-sh.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
>> > 1 files changed, 44 insertions(+), 1 deletions(-)
>> >
>> > v2
>> > * Only use the base of System RAM as an offset into physical memory
>> > if 32bit addressing is in use.
>>
>> This version looks much better, thanks!
>
> I thought so too. But after pushing it I realised the parsing logic in
> is_32bit() is flawed. I will send an update.
yes, line of sscan does not work.
I think that the following is good if I easily make modifications.
while(fgets(line, sizeof(line), fp) != 0) {
if (!strcmp(line, "address sizes\t: 32 bits physical\n")) {
status = 1;
break;
}
}
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
^ permalink raw reply
* Re: [PATCH] ARM: mach-shmobile: sh7372 A4R support V2
From: Rafael J. Wysocki @ 2011-10-16 21:03 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110927085408.27727.59395.sendpatchset@w520>
On Tuesday, September 27, 2011, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> This patch is V2 of sh7372 A4R power domain support.
>
> The sh7372 A4R hardware power domain contains the
> SH CPU Core and a set of I/O devices including
> multimedia accelerators and I2C controllers.
>
> One special case about A4R is the INTCS interrupt
> controller that needs to be saved and restored to
> keep working as expected. Also the LCDC hardware
> blocks are in a different hardware power domain
> but have their IRQs routed only through INTCS. So
> as long as LCDCs are active we cannot power down
> INTCS because that would risk losing interrupts.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
Unfortunately, the original patch breaks resume from system suspend,
because it causes the A4R domain be turned off during the _noirq
phase of device suspend. The domain stays off during syscore_ops
resume, so intc_resume() crashes, because it can't access the
device. To address this problem it is sufficient to prevent the
domain from being turned off, which is done in my version of the
patch below (on top of my version of the A3SP patch sent a while
ago: http://article.gmane.org/gmane.linux.ports.sh.devel/12565).
Thanks,
Rafael
---
From: Magnus Damm <damm@opensource.se>
Subject: ARM: mach-shmobile: sh7372 A4R support
This change adds support for the sh7372 A4R power domain.
The sh7372 A4R hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.
One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
---
arch/arm/mach-shmobile/board-ap4evb.c | 1
arch/arm/mach-shmobile/board-mackerel.c | 1
arch/arm/mach-shmobile/include/mach/sh7372.h | 7 +++
arch/arm/mach-shmobile/intc-sh7372.c | 52 ++++++++++++++++++++++++++-
arch/arm/mach-shmobile/pm-sh7372.c | 29 ++++++++++++++-
arch/arm/mach-shmobile/setup-sh7372.c | 8 ++++
6 files changed, 96 insertions(+), 2 deletions(-)
Index: linux/arch/arm/mach-shmobile/board-ap4evb.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-ap4evb.c
+++ linux/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1412,6 +1412,7 @@ static void __init ap4evb_init(void)
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
hdmi_init_pm_clock();
fsi_init_pm_clock();
Index: linux/arch/arm/mach-shmobile/board-mackerel.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-mackerel.c
+++ linux/arch/arm/mach-shmobile/board-mackerel.c
@@ -1596,6 +1596,7 @@ static void __init mackerel_init(void)
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
#endif
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
hdmi_init_pm_clock();
sh7372_pm_init();
Index: linux/arch/arm/mach-shmobile/include/mach/sh7372.h
=================================--- linux.orig/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ linux/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -480,8 +480,11 @@ struct platform_device;
struct sh7372_pm_domain {
struct generic_pm_domain genpd;
struct dev_power_governor *gov;
+ void (*suspend)(void);
+ void (*resume)(void);
unsigned int bit_shift;
bool no_debug;
+ bool stay_on;
};
static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
@@ -493,6 +496,7 @@ static inline struct sh7372_pm_domain *t
extern struct sh7372_pm_domain sh7372_a4lc;
extern struct sh7372_pm_domain sh7372_a4mp;
extern struct sh7372_pm_domain sh7372_d4;
+extern struct sh7372_pm_domain sh7372_a4r;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
extern struct sh7372_pm_domain sh7372_a3sp;
@@ -512,4 +516,7 @@ extern void sh7372_pm_add_subdomain(stru
#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
#endif /* CONFIG_PM */
+extern void sh7372_intcs_suspend(void);
+extern void sh7372_intcs_resume(void);
+
#endif /* __ASM_SH7372_H__ */
Index: linux/arch/arm/mach-shmobile/intc-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/intc-sh7372.c
+++ linux/arch/arm/mach-shmobile/intc-sh7372.c
@@ -606,9 +606,16 @@ static void intcs_demux(unsigned int irq
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
+static void __iomem *intcs_ffd2;
+static void __iomem *intcs_ffd5;
+
void __init sh7372_init_irq(void)
{
- void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ void __iomem *intevtsa;
+
+ intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
+ intevtsa = intcs_ffd2 + 0x100;
+ intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
register_intc_controller(&intca_desc);
register_intc_controller(&intcs_desc);
@@ -617,3 +624,46 @@ void __init sh7372_init_irq(void)
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
}
+
+static unsigned short ffd2[0x200];
+static unsigned short ffd5[0x100];
+
+void sh7372_intcs_suspend(void)
+{
+ int k;
+
+ for (k = 0x00; k <= 0x30; k += 4)
+ ffd2[k] = __raw_readw(intcs_ffd2 + k);
+
+ for (k = 0x80; k <= 0xb0; k += 4)
+ ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+ for (k = 0x180; k <= 0x188; k += 4)
+ ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+ for (k = 0x00; k <= 0x3c; k += 4)
+ ffd5[k] = __raw_readw(intcs_ffd5 + k);
+
+ for (k = 0x80; k <= 0x9c; k += 4)
+ ffd5[k] = __raw_readb(intcs_ffd5 + k);
+}
+
+void sh7372_intcs_resume(void)
+{
+ int k;
+
+ for (k = 0x00; k <= 0x30; k += 4)
+ __raw_writew(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x80; k <= 0xb0; k += 4)
+ __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x180; k <= 0x188; k += 4)
+ __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x00; k <= 0x3c; k += 4)
+ __raw_writew(ffd5[k], intcs_ffd5 + k);
+
+ for (k = 0x80; k <= 0x9c; k += 4)
+ __raw_writeb(ffd5[k], intcs_ffd5 + k);
+}
Index: linux/arch/arm/mach-shmobile/pm-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/pm-sh7372.c
+++ linux/arch/arm/mach-shmobile/pm-sh7372.c
@@ -44,6 +44,7 @@
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define SBAR 0xe6180020
+#define WUPRMSK 0xe6180028
#define WUPSMSK 0xe618002c
#define WUPSMSK2 0xe6180048
#define PSTR 0xe6180080
@@ -80,6 +81,12 @@ static int pd_power_down(struct generic_
struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
unsigned int mask = 1 << sh7372_pd->bit_shift;
+ if (sh7372_pd->suspend)
+ sh7372_pd->suspend();
+
+ if (sh7372_pd->stay_on)
+ return 0;
+
if (__raw_readl(PSTR) & mask) {
unsigned int retry_count;
@@ -106,6 +113,9 @@ static int pd_power_up(struct generic_pm
unsigned int retry_count;
int ret = 0;
+ if (sh7372_pd->stay_on)
+ goto out;
+
if (__raw_readl(PSTR) & mask)
goto out;
@@ -122,14 +132,23 @@ static int pd_power_up(struct generic_pm
if (__raw_readl(SWUCR) & mask)
ret = -EIO;
- out:
if (!sh7372_pd->no_debug)
pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
mask, __raw_readl(PSTR));
+ out:
+ if (ret = 0 && sh7372_pd->resume)
+ sh7372_pd->resume();
+
return ret;
}
+static void sh7372_a4r_suspend(void)
+{
+ sh7372_intcs_suspend();
+ __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
+}
+
static bool pd_active_wakeup(struct device *dev)
{
return true;
@@ -214,6 +233,14 @@ struct sh7372_pm_domain sh7372_d4 = {
.bit_shift = 3,
};
+struct sh7372_pm_domain sh7372_a4r = {
+ .bit_shift = 5,
+ .gov = &sh7372_always_on_gov,
+ .suspend = sh7372_a4r_suspend,
+ .resume = sh7372_intcs_resume,
+ .stay_on = true,
+};
+
struct sh7372_pm_domain sh7372_a3rv = {
.bit_shift = 6,
};
Index: linux/arch/arm/mach-shmobile/setup-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/setup-sh7372.c
+++ linux/arch/arm/mach-shmobile/setup-sh7372.c
@@ -991,12 +991,14 @@ void __init sh7372_add_standard_devices(
sh7372_init_pm_domain(&sh7372_a4lc);
sh7372_init_pm_domain(&sh7372_a4mp);
sh7372_init_pm_domain(&sh7372_d4);
+ sh7372_init_pm_domain(&sh7372_a4r);
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a3sg);
sh7372_init_pm_domain(&sh7372_a3sp);
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
+ sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices));
@@ -1020,6 +1022,12 @@ void __init sh7372_add_standard_devices(
sh7372_add_special_dev_to_domain(&sh7372_a3sp, &dma2_device);
sh7372_add_special_dev_to_domain(&sh7372_a3sp, &usb_dma0_device);
sh7372_add_special_dev_to_domain(&sh7372_a3sp, &usb_dma1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
}
void __init sh7372_add_early_devices(void)
^ permalink raw reply
* Re: [PATCH] ARM: mach-shmobile: sh7372 A3SP support V2
From: Rafael J. Wysocki @ 2011-10-16 20:05 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110712082459.18930.51005.sendpatchset@t400s>
Hi,
On Tuesday, September 27, 2011, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> This patch is V2 of sh7372 A3SP power domain support.
>
> The sh7372 A3SP hardware power domain contains a
> wide range of I/O devices. The list of I/O devices
> include SCIF serial ports, DMA Engine hardware,
> SD and MMC controller hardware, USB controllers
> and I2C master controllers.
>
> This patch adds the A3SP low level code which
> powers the hardware power domain on and off. It
> also ties in platform devices to the pm domain
> support code.
>
> It is worth noting that the serial console is
> hooked up to SCIFA0 on most sh7372 boards, and
> the SCIFA0 port is included in the A3SP hardware
> power domain. For this reason we cannot output
> debug messages from the low level power control
> code in the case of A3SP.
>
> QoS support is needed in drivers before we can
> enable the A3SP power control on the fly.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
The original patch unfortunately broke system suspend, because
attempting to turn of clocks for some devices in the A3SP domain
(DMA engines and usbh1_device) appears to lock up hard. I made
some changes to it and was able to make it work with system
suspend too. My version of the patch is appended.
Thanks,
Rafael
---
From: Magnus Damm <damm@opensource.se>
Subject: ARM: mach-shmobile: sh7372 A3SP support V2
This change adds support for the sh7372 A3SP power domain.
The sh7372 A3SP hardware power domain contains a
wide range of I/O devices. The list of I/O devices
include SCIF serial ports, DMA Engine hardware,
SD and MMC controller hardware, USB controllers
and I2C master controllers.
This patch adds the A3SP low level code which
powers the hardware power domain on and off. It
also ties in platform devices to the pm domain
support code.
It is worth noting that the serial console is
hooked up to SCIFA0 on most sh7372 boards, and
the SCIFA0 port is included in the A3SP hardware
power domain. For this reason we cannot output
debug messages from the low level power control
code in the case of A3SP.
QoS support is needed in drivers before we can
enable the A3SP power control on the fly.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
---
arch/arm/mach-shmobile/board-ap4evb.c | 4 +
arch/arm/mach-shmobile/board-mackerel.c | 8 +++
arch/arm/mach-shmobile/include/mach/sh7372.h | 6 ++
arch/arm/mach-shmobile/pm-sh7372.c | 62 +++++++++++++++++++++++----
arch/arm/mach-shmobile/setup-sh7372.c | 14 ++++++
include/linux/pm.h | 1
6 files changed, 88 insertions(+), 7 deletions(-)
Index: linux/arch/arm/mach-shmobile/board-ap4evb.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-ap4evb.c
+++ linux/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1409,6 +1409,10 @@ static void __init ap4evb_init(void)
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+
hdmi_init_pm_clock();
fsi_init_pm_clock();
sh7372_pm_init();
Index: linux/arch/arm/mach-shmobile/board-mackerel.c
=================================--- linux.orig/arch/arm/mach-shmobile/board-mackerel.c
+++ linux/arch/arm/mach-shmobile/board-mackerel.c
@@ -1588,6 +1588,14 @@ static void __init mackerel_init(void)
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
+ sh7372_add_special_dev_to_domain(&sh7372_a3sp, &usbhs1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+#endif
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
hdmi_init_pm_clock();
sh7372_pm_init();
Index: linux/arch/arm/mach-shmobile/include/mach/sh7372.h
=================================--- linux.orig/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ linux/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -479,7 +479,9 @@ struct platform_device;
struct sh7372_pm_domain {
struct generic_pm_domain genpd;
+ struct dev_power_governor *gov;
unsigned int bit_shift;
+ bool no_debug;
};
static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
@@ -493,16 +495,20 @@ extern struct sh7372_pm_domain sh7372_a4
extern struct sh7372_pm_domain sh7372_d4;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
+extern struct sh7372_pm_domain sh7372_a3sp;
extern struct sh7372_pm_domain sh7372_a3sg;
extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
struct platform_device *pdev);
+extern void sh7372_add_special_dev_to_domain(struct sh7372_pm_domain *sh7372_pd,
+ struct platform_device *pdev);
extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
struct sh7372_pm_domain *sh7372_sd);
#else
#define sh7372_init_pm_domain(pd) do { } while(0)
#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
+#define sh7372_add_special_dev_to_domain(pd, pdev) do { } while(0)
#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
#endif /* CONFIG_PM */
Index: linux/arch/arm/mach-shmobile/pm-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/pm-sh7372.c
+++ linux/arch/arm/mach-shmobile/pm-sh7372.c
@@ -92,8 +92,9 @@ static int pd_power_down(struct generic_
}
}
- pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+ if (!sh7372_pd->no_debug)
+ pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
+ mask, __raw_readl(PSTR));
return 0;
}
@@ -122,8 +123,9 @@ static int pd_power_up(struct generic_pm
ret = -EIO;
out:
- pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+ if (!sh7372_pd->no_debug)
+ pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
+ mask, __raw_readl(PSTR));
return ret;
}
@@ -133,13 +135,40 @@ static bool pd_active_wakeup(struct devi
return true;
}
+static bool sh7372_power_down_forbidden(struct dev_pm_domain *domain)
+{
+ return false;
+}
+
+struct dev_power_governor sh7372_always_on_gov = {
+ .power_down_ok = sh7372_power_down_forbidden,
+};
+
+int sh7372_stop_device(struct device *dev)
+{
+ if (dev->power.subsys_data && dev->power.subsys_data->domain_data
+ && dev->power.subsys_data->domain_data->private_data)
+ return 0;
+
+ return pm_clk_suspend(dev);
+}
+
+int sh7372_start_device(struct device *dev)
+{
+ if (dev->power.subsys_data && dev->power.subsys_data->domain_data
+ && dev->power.subsys_data->domain_data->private_data)
+ return 0;
+
+ return pm_clk_resume(dev);
+}
+
void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
{
struct generic_pm_domain *genpd = &sh7372_pd->genpd;
- pm_genpd_init(genpd, NULL, false);
- genpd->stop_device = pm_clk_suspend;
- genpd->start_device = pm_clk_resume;
+ pm_genpd_init(genpd, sh7372_pd->gov, false);
+ genpd->stop_device = sh7372_stop_device;
+ genpd->start_device = sh7372_start_device;
genpd->dev_irq_safe = true;
genpd->active_wakeup = pd_active_wakeup;
genpd->power_off = pd_power_down;
@@ -157,6 +186,16 @@ void sh7372_add_device_to_domain(struct
pm_clk_add(dev, NULL);
}
+void sh7372_add_special_dev_to_domain(struct sh7372_pm_domain *sh7372_pd,
+ struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+ sh7372_add_device_to_domain(sh7372_pd, pdev);
+ if (dev->power.subsys_data && dev->power.subsys_data->domain_data)
+ dev->power.subsys_data->domain_data->private_data = (void *)1;
+}
+
void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
struct sh7372_pm_domain *sh7372_sd)
{
@@ -183,6 +222,12 @@ struct sh7372_pm_domain sh7372_a3ri = {
.bit_shift = 8,
};
+struct sh7372_pm_domain sh7372_a3sp = {
+ .bit_shift = 11,
+ .gov = &sh7372_always_on_gov,
+ .no_debug = true,
+};
+
struct sh7372_pm_domain sh7372_a3sg = {
.bit_shift = 13,
};
@@ -422,6 +467,9 @@ void __init sh7372_pm_init(void)
__raw_writel(0x0000a501, DBGREG9);
__raw_writel(0x00000000, DBGREG1);
+ /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
+ __raw_writel(0, PDNSEL);
+
sh7372_suspend_init();
sh7372_cpuidle_init();
}
Index: linux/arch/arm/mach-shmobile/setup-sh7372.c
=================================--- linux.orig/arch/arm/mach-shmobile/setup-sh7372.c
+++ linux/arch/arm/mach-shmobile/setup-sh7372.c
@@ -994,6 +994,7 @@ void __init sh7372_add_standard_devices(
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a3sg);
+ sh7372_init_pm_domain(&sh7372_a3sp);
sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
@@ -1006,6 +1007,19 @@ void __init sh7372_add_standard_devices(
sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
+ sh7372_add_special_dev_to_domain(&sh7372_a3sp, &dma0_device);
+ sh7372_add_special_dev_to_domain(&sh7372_a3sp, &dma1_device);
+ sh7372_add_special_dev_to_domain(&sh7372_a3sp, &dma2_device);
+ sh7372_add_special_dev_to_domain(&sh7372_a3sp, &usb_dma0_device);
+ sh7372_add_special_dev_to_domain(&sh7372_a3sp, &usb_dma1_device);
}
void __init sh7372_add_early_devices(void)
Index: linux/include/linux/pm.h
=================================--- linux.orig/include/linux/pm.h
+++ linux/include/linux/pm.h
@@ -428,6 +428,7 @@ struct wakeup_source;
struct pm_domain_data {
struct list_head list_node;
struct device *dev;
+ void *private_data;
};
struct pm_subsys_data {
^ permalink raw reply
* [PATCH] PM / Sleep: Mark devices involved in wakeup signaling during suspend
From: Rafael J. Wysocki @ 2011-10-16 14:45 UTC (permalink / raw)
To: Linux PM list; +Cc: LKML, Linux-sh list, Magnus Damm
From: Rafael J. Wysocki <rjw@sisk.pl>
The generic PM domains code in drivers/base/power/domain.c has
to avoid powering off domains that provide power to wakeup devices
during system suspend. Currently, however, this only works for
wakeup devices directly belonging to the given domain and not for
their children (or the children of their children and so on).
Thus, if there's a wakeup device whose parent belongs to a power
domain handled by the generic PM domains code, the domain will be
powered off during system suspend preventing the device from
signaling wakeup.
To address this problem introduce a device flag, power.wakeup_path,
that will be set during system suspend for all wakeup devices,
their parents, the parents of their parents and so on. This way,
all wakeup paths in the device hierarchy will be marked and the
generic PM domains code will only need to avoid powering off
domains containing devices whose power.wakeup_path is set.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
---
drivers/base/power/domain.c | 4 ++--
drivers/base/power/main.c | 8 +++++++-
include/linux/pm.h | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
Index: linux/drivers/base/power/domain.c
=================================--- linux.orig/drivers/base/power/domain.c
+++ linux/drivers/base/power/domain.c
@@ -714,7 +714,7 @@ static int pm_genpd_suspend_noirq(struct
if (ret)
return ret;
- if (device_may_wakeup(dev)
+ if (dev->power.wakeup_path
&& genpd->active_wakeup && genpd->active_wakeup(dev))
return 0;
@@ -938,7 +938,7 @@ static int pm_genpd_dev_poweroff_noirq(s
if (ret)
return ret;
- if (device_may_wakeup(dev)
+ if (dev->power.wakeup_path
&& genpd->active_wakeup && genpd->active_wakeup(dev))
return 0;
Index: linux/drivers/base/power/main.c
=================================--- linux.orig/drivers/base/power/main.c
+++ linux/drivers/base/power/main.c
@@ -917,7 +917,11 @@ static int __device_suspend(struct devic
}
End:
- dev->power.is_suspended = !error;
+ if (!error) {
+ dev->power.is_suspended = true;
+ if (dev->power.wakeup_path && dev->parent)
+ dev->parent->power.wakeup_path = true;
+ }
device_unlock(dev);
complete_all(&dev->power.completion);
@@ -1020,6 +1024,8 @@ static int device_prepare(struct device
device_lock(dev);
+ dev->power.wakeup_path = device_may_wakeup(dev);
+
if (dev->pm_domain) {
pm_dev_dbg(dev, state, "preparing power domain ");
if (dev->pm_domain->ops.prepare)
Index: linux/include/linux/pm.h
=================================--- linux.orig/include/linux/pm.h
+++ linux/include/linux/pm.h
@@ -452,6 +452,7 @@ struct dev_pm_info {
struct list_head entry;
struct completion completion;
struct wakeup_source *wakeup;
+ unsigned int wakeup_path:1;
#else
unsigned int should_wakeup:1;
#endif
^ permalink raw reply
* @2011 MICROSOFT AWARD !!
From: Microsoft Office @ 2011-10-15 23:20 UTC (permalink / raw)
To: linux-sh
Message bodyA lump sum of (?1,000,000.00) have been credited to your E-mail Address.Congrats...Batch number YM 09102XN
Confirm this receipt by contacting Mr. Martin Lahm via
Email:y.msn021010121@live.com
^ permalink raw reply
* Re: [PATCH/RFC v2] sh: Use big endian ioread/write for SH2 platforms
From: Yoshinori Sato @ 2011-10-14 3:33 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <1318406604-16537-1-git-send-email-phil.edworthy@renesas.com>
At Wed, 12 Oct 2011 09:03:24 +0100,
Phil Edworthy wrote:
>
> Commit 37b7a97884ba64bf7d403351ac2a9476ab4f1bba makes all ioread/iowrite
> functions treat registers as little endian. For SH2 this is not the case,
> they are big endian.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Looks good.
Thanks.
> ---
> v2: Modified so that it's used on all SH2 devices
>
> arch/sh/include/asm/io.h | 18 ++++++++++++++++++
> 1 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
> index 28c5aa5..65f2d5a 100644
> --- a/arch/sh/include/asm/io.h
> +++ b/arch/sh/include/asm/io.h
> @@ -35,6 +35,7 @@
> #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
> #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
>
> +#ifndef CONFIG_CPU_SH2
> #define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
> #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
> __raw_readw(c)); __v; })
> @@ -50,6 +51,23 @@
> cpu_to_le32(v),c))
> #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
> cpu_to_le64(v),c))
> +#else
> +#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
> +#define readw_relaxed(c) ({ u16 __v = be16_to_cpu((__force __be16) \
> + __raw_readw(c)); __v; })
> +#define readl_relaxed(c) ({ u32 __v = be32_to_cpu((__force __be32) \
> + __raw_readl(c)); __v; })
> +#define readq_relaxed(c) ({ u64 __v = be64_to_cpu((__force __be64) \
> + __raw_readq(c)); __v; })
> +
> +#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
> +#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
> + cpu_to_be16(v),c))
> +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
> + cpu_to_be32(v),c))
> +#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
> + cpu_to_be64(v),c))
> +#endif
>
> #define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
> #define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
> --
> 1.7.0.4
>
--
Yoshinori Sato
<ysato@users.sourceforge.jp>
^ permalink raw reply
* [PATCH 2/2] sh: On 32bit segments may not be in P2
From: Simon Horman @ 2011-10-12 22:44 UTC (permalink / raw)
To: linux-sh
Cc: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Simon Horman <horms@verge.net.au>
---
kexec/arch/sh/kexec-sh.c | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/kexec/arch/sh/kexec-sh.c b/kexec/arch/sh/kexec-sh.c
index a397d08..7710fdf 100644
--- a/kexec/arch/sh/kexec-sh.c
+++ b/kexec/arch/sh/kexec-sh.c
@@ -219,13 +219,15 @@ unsigned long virt_to_phys(unsigned long addr)
{
unsigned long seg = addr & 0xe0000000;
unsigned long long start = 0;
+ int have_32bit = is_32bit();
- if (seg != 0x80000000 && seg != 0xc0000000)
- die("Virtual address %p is not in P1 or P2\n", (void *)addr);
+ if (seg != 0x80000000 && (have_32bit || seg != 0xc0000000))
+ die("Virtual address %p is not in P1%s\n", (void *)addr,
+ have_32bit ? "" : " or P2");
/* If 32bit addressing is used then the base of system RAM
* is an offset into physical memory. */
- if (is_32bit()) {
+ if (have_32bit) {
unsigned long long end;
int ret;
--
1.7.6.3
^ permalink raw reply related
* [PATCH 1/2] sh: Correct logic errors in is_32bit()
From: Simon Horman @ 2011-10-12 22:44 UTC (permalink / raw)
To: linux-sh
This corrects logic errors so that is_32bit() can actually detect that it
is running on a 32 bit system - something the original version I wrote
failed at woefully.
Signed-off-by: Simon Horman <horms@verge.net.au>
---
kexec/arch/sh/kexec-sh.c | 20 +++++++++++---------
1 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/kexec/arch/sh/kexec-sh.c b/kexec/arch/sh/kexec-sh.c
index 94ebbc7..a397d08 100644
--- a/kexec/arch/sh/kexec-sh.c
+++ b/kexec/arch/sh/kexec-sh.c
@@ -188,9 +188,8 @@ void kexec_sh_setup_zero_page(char *zero_page_buf, size_t zero_page_size,
static int is_32bit(void)
{
const char *cpuinfo = "/proc/cpuinfo";
- char line[MAX_LINE], key[MAX_LINE], value[MAX_LINE];
+ char line[MAX_LINE];
FILE *fp;
- int count;
int status = 0;
fp = fopen(cpuinfo, "r");
@@ -198,14 +197,17 @@ static int is_32bit(void)
die("Cannot open %s\n", cpuinfo);
while(fgets(line, sizeof(line), fp) != 0) {
- count = sscanf(line, "%s : %s", key, value);
- if (count != 2)
+ const char *key = "address sizes";
+ const char *value = " 32 bits physical";
+ char *p;
+ if (strncmp(line, key, strlen(key)))
continue;
- if (!strcmp(key, "address sizes")) {
- if (!strcmp(value, "32 bits physical"))
- status = 1;
- break;
- }
+ p = strchr(line + strlen(key), ':');
+ if (!p)
+ continue;
+ if (!strncmp(p + 1, value, strlen(value)))
+ status = 1;
+ break;
}
fclose(fp);
--
1.7.6.3
^ permalink raw reply related
* Re: [PATCH v2] sh: Take into account the base of System RAM in
From: Simon Horman @ 2011-10-12 22:42 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <1317603918-30762-1-git-send-email-horms@verge.net.au>
On Wed, Oct 12, 2011 at 05:24:23PM +0900, Magnus Damm wrote:
> On Mon, Oct 3, 2011 at 10:05 AM, Simon Horman <horms@verge.net.au> wrote:
> > Previously virt_to_phys() assumed that physical memory always started
> > at address 0. This is not always the case.
> >
> > Tested on an sh7757lcr (32bit system) whose only System RAM region is
> > 40000000-4effffff and an ecovec24 (29bit system).
> >
> > Signed-off-by: Simon Horman <horms@verge.net.au>
> >
> > ---
> > kexec/arch/sh/kexec-sh.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
> > 1 files changed, 44 insertions(+), 1 deletions(-)
> >
> > v2
> > * Only use the base of System RAM as an offset into physical memory
> > if 32bit addressing is in use.
>
> This version looks much better, thanks!
I thought so too. But after pushing it I realised the parsing logic in
is_32bit() is flawed. I will send an update.
^ permalink raw reply
* Re: [PATCH v2] sh: Take into account the base of System RAM in virt_to_phys()
From: Magnus Damm @ 2011-10-12 8:24 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <1317603918-30762-1-git-send-email-horms@verge.net.au>
On Mon, Oct 3, 2011 at 10:05 AM, Simon Horman <horms@verge.net.au> wrote:
> Previously virt_to_phys() assumed that physical memory always started
> at address 0. This is not always the case.
>
> Tested on an sh7757lcr (32bit system) whose only System RAM region is
> 40000000-4effffff and an ecovec24 (29bit system).
>
> Signed-off-by: Simon Horman <horms@verge.net.au>
>
> ---
> kexec/arch/sh/kexec-sh.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
> 1 files changed, 44 insertions(+), 1 deletions(-)
>
> v2
> * Only use the base of System RAM as an offset into physical memory
> if 32bit addressing is in use.
This version looks much better, thanks!
/ magnus
^ permalink raw reply
* [PATCH/RFC v2] sh: Use big endian ioread/write for SH2 platforms
From: Phil Edworthy @ 2011-10-12 8:03 UTC (permalink / raw)
To: linux-sh
Commit 37b7a97884ba64bf7d403351ac2a9476ab4f1bba makes all ioread/iowrite
functions treat registers as little endian. For SH2 this is not the case,
they are big endian.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
v2: Modified so that it's used on all SH2 devices
arch/sh/include/asm/io.h | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 28c5aa5..65f2d5a 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -35,6 +35,7 @@
#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
+#ifndef CONFIG_CPU_SH2
#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
__raw_readw(c)); __v; })
@@ -50,6 +51,23 @@
cpu_to_le32(v),c))
#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
cpu_to_le64(v),c))
+#else
+#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
+#define readw_relaxed(c) ({ u16 __v = be16_to_cpu((__force __be16) \
+ __raw_readw(c)); __v; })
+#define readl_relaxed(c) ({ u32 __v = be32_to_cpu((__force __be32) \
+ __raw_readl(c)); __v; })
+#define readq_relaxed(c) ({ u64 __v = be64_to_cpu((__force __be64) \
+ __raw_readq(c)); __v; })
+
+#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
+#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
+ cpu_to_be16(v),c))
+#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
+ cpu_to_be32(v),c))
+#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
+ cpu_to_be64(v),c))
+#endif
#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
--
1.7.0.4
^ permalink raw reply related
* [PATCH 07/07] ARM: mach-shmobile: SDHI0 GPIO hotplug for AG5EVM
From: Magnus Damm @ 2011-10-12 7:21 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Implement GPIO hotplugging via TMIO_MMC_HAS_COLD_CD for
AG5EVM SDHI0. This is possible now when INTCA is used for
IRQ triggering on sh73a0. Without INTCA IRQ support we are
left with the GIC hardware block that does not support
dealing with active low interrupt sources.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/board-ag5evm.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
--- 0003/arch/arm/mach-shmobile/board-ag5evm.c
+++ work/arch/arm/mach-shmobile/board-ag5evm.c 2011-10-12 15:14:41.000000000 +0900
@@ -338,6 +338,18 @@ static struct platform_device mipidsi0_d
},
};
+/* SDHI0 */
+static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg)
+{
+ struct device *dev = arg;
+ struct sh_mobile_sdhi_info *info = dev->platform_data;
+ struct tmio_mmc_data *pdata = info->pdata;
+
+ tmio_mmc_cd_wakeup(pdata);
+
+ return IRQ_HANDLED;
+}
+
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -561,6 +573,13 @@ static void __init ag5evm_init(void)
gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
+ if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+ "sdhi0 cd", &sdhi0_device.dev))
+ sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD;
+ else
+ pr_warn("Unable to setup SDHI0 GPIO IRQ\n");
+
/* enable SDHI1 on CN4 [WLAN I/F] */
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
^ permalink raw reply
* [PATCH 06/07] ARM: mach-shmobile: Use common INTC IRQ code on sh73a0
From: Magnus Damm @ 2011-10-12 7:21 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Improve IRQ triggering support by making use of the macro
INTC_IRQ_PINS_32() for INTCA on sh73a0. Unfortunately it
is not as easy as just using the macro as-is, we need to
do mask and unmaks in the GIC but configure other bits
and ack in INTCA. Update GPIO IRQ mappings while at it.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/intc-sh73a0.c | 122 ++++++++++++++++++++++++++++++++++
arch/arm/mach-shmobile/pfc-sh73a0.c | 68 +++++++++---------
2 files changed, 157 insertions(+), 33 deletions(-)
--- 0001/arch/arm/mach-shmobile/intc-sh73a0.c
+++ work/arch/arm/mach-shmobile/intc-sh73a0.c 2011-10-12 15:22:33.000000000 +0900
@@ -22,6 +22,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
+#include <mach/intc.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -255,20 +256,141 @@ static int sh73a0_set_wake(struct irq_da
return 0; /* always allow wakeup */
}
+#define RELOC_BASE 0x1000
+
+/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
+#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
+
+INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
+ INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
+
+static int to_gic_irq(struct irq_data *data)
+{
+ unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
+
+ if (vect >= 0x3200)
+ vect -= 0x3000;
+ else
+ vect -= 0x0200;
+
+ return gic_spi((vect >> 5) + 1);
+}
+
+static int to_intca_reloc_irq(struct irq_data *data)
+{
+ return data->irq + (RELOC_BASE >> 5);
+}
+
+#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
+#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
+
+static void intca_gic_enable(struct irq_data *data)
+{
+ irq_cb(irq_unmask, to_intca_reloc_irq(data));
+ irq_cb(irq_unmask, to_gic_irq(data));
+}
+
+static void intca_gic_disable(struct irq_data *data)
+{
+ irq_cb(irq_mask, to_gic_irq(data));
+ irq_cb(irq_mask, to_intca_reloc_irq(data));
+}
+
+static void intca_gic_mask_ack(struct irq_data *data)
+{
+ irq_cb(irq_mask, to_gic_irq(data));
+ irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
+}
+
+static void intca_gic_eoi(struct irq_data *data)
+{
+ irq_cb(irq_eoi, to_gic_irq(data));
+}
+
+static int intca_gic_set_type(struct irq_data *data, unsigned int type)
+{
+ return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
+}
+
+static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
+{
+ return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
+}
+
+#ifdef CONFIG_SMP
+static int intca_gic_set_affinity(struct irq_data *data,
+ const struct cpumask *cpumask,
+ bool force)
+{
+ return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
+}
+#endif
+
+struct irq_chip intca_gic_irq_chip = {
+ .name = "INTCA-GIC",
+ .irq_mask = intca_gic_disable,
+ .irq_unmask = intca_gic_enable,
+ .irq_mask_ack = intca_gic_mask_ack,
+ .irq_eoi = intca_gic_eoi,
+ .irq_enable = intca_gic_enable,
+ .irq_disable = intca_gic_disable,
+ .irq_shutdown = intca_gic_disable,
+ .irq_set_type = intca_gic_set_type,
+ .irq_set_wake = intca_gic_set_wake,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = intca_gic_set_affinity,
+#endif
+};
+
+static int to_intc_vect(int irq)
+{
+ unsigned int irq_pin = irq - gic_spi(1);
+ unsigned int offs;
+
+ if (irq_pin < 16)
+ offs = 0x0200;
+ else
+ offs = 0x3000;
+
+ return offs + (irq_pin << 5);
+}
+
+static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
+{
+ generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
+ return IRQ_HANDLED;
+}
+
+static struct irqaction sh73a0_irq_pin_cascade[32];
+
void __init sh73a0_init_irq(void)
{
void __iomem *gic_dist_base = __io(0xf0001000);
void __iomem *gic_cpu_base = __io(0xf0000100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ int k, n;
gic_init(0, 29, gic_dist_base, gic_cpu_base);
gic_arch_extn.irq_set_wake = sh73a0_set_wake;
register_intc_controller(&intcs_desc);
+ register_intc_controller(&intca_irq_pins_desc);
/* demux using INTEVTSA */
sh73a0_intcs_cascade.name = "INTCS cascade";
sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
sh73a0_intcs_cascade.dev_id = intevtsa;
setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
+
+ /* IRQ pins require special handling through INTCA and GIC */
+ for (k = 0; k < 32; k++) {
+ sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
+ sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
+ setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
+
+ n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
+ irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
+ handle_level_irq, "level");
+ set_irq_flags(n, IRQF_VALID); /* yuck */
+ }
}
--- 0007/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ work/arch/arm/mach-shmobile/pfc-sh73a0.c 2011-10-12 15:21:09.000000000 +0900
@@ -2766,41 +2766,43 @@ static struct pinmux_data_reg pinmux_dat
{ },
};
-#define EXT_IRQ(n) gic_spi((n) + 1) /* GIC SPI starting from 1 for IRQ0 */
+/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
+#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
+#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
static struct pinmux_irq pinmux_irqs[] = {
- PINMUX_IRQ(EXT_IRQ(19), PORT9_FN0),
- PINMUX_IRQ(EXT_IRQ(1), PORT10_FN0),
- PINMUX_IRQ(EXT_IRQ(0), PORT11_FN0),
- PINMUX_IRQ(EXT_IRQ(18), PORT13_FN0),
- PINMUX_IRQ(EXT_IRQ(20), PORT14_FN0),
- PINMUX_IRQ(EXT_IRQ(21), PORT15_FN0),
- PINMUX_IRQ(EXT_IRQ(31), PORT26_FN0),
- PINMUX_IRQ(EXT_IRQ(30), PORT27_FN0),
- PINMUX_IRQ(EXT_IRQ(29), PORT28_FN0),
- PINMUX_IRQ(EXT_IRQ(22), PORT40_FN0),
- PINMUX_IRQ(EXT_IRQ(23), PORT53_FN0),
- PINMUX_IRQ(EXT_IRQ(10), PORT54_FN0),
- PINMUX_IRQ(EXT_IRQ(9), PORT56_FN0),
- PINMUX_IRQ(EXT_IRQ(26), PORT115_FN0),
- PINMUX_IRQ(EXT_IRQ(27), PORT116_FN0),
- PINMUX_IRQ(EXT_IRQ(28), PORT117_FN0),
- PINMUX_IRQ(EXT_IRQ(24), PORT118_FN0),
- PINMUX_IRQ(EXT_IRQ(6), PORT147_FN0),
- PINMUX_IRQ(EXT_IRQ(2), PORT149_FN0),
- PINMUX_IRQ(EXT_IRQ(7), PORT150_FN0),
- PINMUX_IRQ(EXT_IRQ(12), PORT156_FN0),
- PINMUX_IRQ(EXT_IRQ(4), PORT159_FN0),
- PINMUX_IRQ(EXT_IRQ(25), PORT164_FN0),
- PINMUX_IRQ(EXT_IRQ(8), PORT223_FN0),
- PINMUX_IRQ(EXT_IRQ(3), PORT224_FN0),
- PINMUX_IRQ(EXT_IRQ(5), PORT227_FN0),
- PINMUX_IRQ(EXT_IRQ(17), PORT234_FN0),
- PINMUX_IRQ(EXT_IRQ(11), PORT238_FN0),
- PINMUX_IRQ(EXT_IRQ(13), PORT239_FN0),
- PINMUX_IRQ(EXT_IRQ(16), PORT249_FN0),
- PINMUX_IRQ(EXT_IRQ(14), PORT251_FN0),
- PINMUX_IRQ(EXT_IRQ(9), PORT308_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
+ PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
+ PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
};
static struct pinmux_info sh73a0_pinmux_info = {
^ permalink raw reply
* [PATCH 05/07] ARM: mach-shmobile: Use common INTC IRQ code on sh7372
From: Magnus Damm @ 2011-10-12 7:21 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Make use of INTC_IRQ_PINS_32() for INTCA on sh7372.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/intc-sh7372.c | 72 +++-------------------------------
1 file changed, 8 insertions(+), 64 deletions(-)
--- 0001/arch/arm/mach-shmobile/intc-sh7372.c
+++ work/arch/arm/mach-shmobile/intc-sh7372.c 2011-10-12 15:10:56.000000000 +0900
@@ -22,6 +22,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
+#include <mach/intc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -29,10 +30,6 @@ enum {
UNUSED_INTCA = 0,
/* interrupt sources INTCA */
- IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
- IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
- IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
- IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
DIRC,
CRYPT_STD,
IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
@@ -86,22 +83,6 @@ enum {
};
static struct intc_vect intca_vectors[] __initdata = {
- INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
- INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
- INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
- INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
- INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
- INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
- INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
- INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
- INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
- INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
- INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0),
- INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
- INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
- INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
- INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
- INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
INTC_VECT(DIRC, 0x0560),
INTC_VECT(CRYPT_STD, 0x0700),
INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
@@ -203,15 +184,6 @@ static struct intc_group intca_groups[]
};
static struct intc_mask_reg intca_mask_registers[] __initdata = {
- { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
@@ -282,15 +254,6 @@ static struct intc_mask_reg intca_mask_r
};
static struct intc_prio_reg intca_prio_registers[] __initdata = {
- { 0xe6900010, 0, 32, 4, /* INTPRI00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900014, 0, 32, 4, /* INTPRI10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900018, 0, 32, 4, /* INTPRI20A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690001c, 0, 32, 4, /* INTPRI30A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
@@ -336,33 +299,13 @@ static struct intc_prio_reg intca_prio_r
{ 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
};
-static struct intc_sense_reg intca_sense_registers[] __initdata = {
- { 0xe6900000, 32, 4, /* ICR1A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900004, 32, 4, /* ICR2A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900008, 32, 4, /* ICR3A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690000c, 32, 4, /* ICR4A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-};
-
-static struct intc_mask_reg intca_ack_registers[] __initdata = {
- { 0xe6900020, 0, 8, /* INTREQ00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900024, 0, 8, /* INTREQ10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900028, 0, 8, /* INTREQ20A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690002c, 0, 8, /* INTREQ30A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-};
-
-static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
- intca_vectors, intca_groups,
- intca_mask_registers, intca_prio_registers,
- intca_sense_registers, intca_ack_registers);
+static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
+ intca_vectors, intca_groups,
+ intca_mask_registers, intca_prio_registers,
+ NULL);
+INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
+ INTC_VECT, "sh7372-intca-irq-pins");
enum {
UNUSED_INTCS = 0,
ENABLED_INTCS,
@@ -611,6 +554,7 @@ void __init sh7372_init_irq(void)
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
register_intc_controller(&intca_desc);
+ register_intc_controller(&intca_irq_pins_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
^ permalink raw reply
* [PATCH 04/07] ARM: mach-shmobile: Use common INTC IRQ code on sh7377
From: Magnus Damm @ 2011-10-12 7:21 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Make use of INTC_IRQ_PINS_32() for INTCA on sh7377.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/intc-sh7377.c | 67 +++-------------------------------
1 file changed, 6 insertions(+), 61 deletions(-)
--- 0001/arch/arm/mach-shmobile/intc-sh7377.c
+++ work/arch/arm/mach-shmobile/intc-sh7377.c 2011-10-12 15:08:58.000000000 +0900
@@ -22,6 +22,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
+#include <mach/intc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -31,10 +32,6 @@ enum {
DISABLED,
/* interrupt sources INTCA */
- IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
- IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
- IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
- IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
DIRC,
_2DG,
CRYPT_STD,
@@ -91,22 +88,6 @@ enum {
};
static struct intc_vect intca_vectors[] __initdata = {
- INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
- INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
- INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
- INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
- INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
- INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
- INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
- INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
- INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
- INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
- INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
- INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
- INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
- INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
- INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
- INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
INTC_VECT(DIRC, 0x0560),
INTC_VECT(_2DG, 0x05e0),
INTC_VECT(CRYPT_STD, 0x0700),
@@ -203,15 +184,6 @@ static struct intc_group intca_groups[]
};
static struct intc_mask_reg intca_mask_registers[] __initdata = {
- { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
@@ -273,15 +245,6 @@ static struct intc_mask_reg intca_mask_r
};
static struct intc_prio_reg intca_prio_registers[] __initdata = {
- { 0xe6900010, 0, 32, 4, /* INTPRI00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900014, 0, 32, 4, /* INTPRI10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900018, 0, 32, 4, /* INTPRI10A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690001c, 0, 32, 4, /* INTPRI30A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
@@ -315,37 +278,18 @@ static struct intc_prio_reg intca_prio_r
{ 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
};
-static struct intc_sense_reg intca_sense_registers[] __initdata = {
- { 0xe6900000, 16, 2, /* ICR1A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900004, 16, 2, /* ICR2A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900008, 16, 2, /* ICR3A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690000c, 16, 2, /* ICR4A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-};
-
-static struct intc_mask_reg intca_ack_registers[] __initdata = {
- { 0xe6900020, 0, 8, /* INTREQ00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900024, 0, 8, /* INTREQ10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
- { 0xe6900028, 0, 8, /* INTREQ20A */
- { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
- { 0xe690002c, 0, 8, /* INTREQ30A */
- { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
-};
-
static struct intc_desc intca_desc __initdata = {
.name = "sh7377-intca",
.force_enable = ENABLED,
.force_disable = DISABLED,
.hw = INTC_HW_DESC(intca_vectors, intca_groups,
intca_mask_registers, intca_prio_registers,
- intca_sense_registers, intca_ack_registers),
+ NULL, NULL),
};
+INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
+ INTC_VECT, "sh7377-intca-irq-pins");
+
/* this macro ignore entry which is also in INTCA */
#define __IGNORE(a...)
#define __IGNORE0(a...) 0
@@ -638,6 +582,7 @@ void __init sh7377_init_irq(void)
void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
register_intc_controller(&intca_desc);
+ register_intc_controller(&intca_irq_pins_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
^ permalink raw reply
* [PATCH 03/07] ARM: mach-shmobile: Use common INTC IRQ code on sh7367
From: Magnus Damm @ 2011-10-12 7:21 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Make use of INTC_IRQ_PINS_16() for INTCA on sh7367.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/intc-sh7367.c | 40 +++++-----------------------------
1 file changed, 6 insertions(+), 34 deletions(-)
--- 0001/arch/arm/mach-shmobile/intc-sh7367.c
+++ work/arch/arm/mach-shmobile/intc-sh7367.c 2011-10-12 15:07:52.000000000 +0900
@@ -22,6 +22,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
+#include <mach/intc.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -31,8 +32,6 @@ enum {
DISABLED,
/* interrupt sources INTCA */
- IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
- IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
DIRC,
CRYPT1_ERR, CRYPT2_STD,
IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
@@ -76,14 +75,6 @@ enum {
};
static struct intc_vect intca_vectors[] __initdata = {
- INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
- INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
- INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
- INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
- INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
- INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
- INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
- INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
INTC_VECT(DIRC, 0x0560),
INTC_VECT(CRYPT1_ERR, 0x05e0),
INTC_VECT(CRYPT2_STD, 0x0700),
@@ -163,10 +154,6 @@ static struct intc_group intca_groups[]
};
static struct intc_mask_reg intca_mask_registers[] __initdata = {
- { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
{ 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
@@ -212,11 +199,6 @@ static struct intc_mask_reg intca_mask_r
};
static struct intc_prio_reg intca_prio_registers[] __initdata = {
- { 0xe6900010, 0, 32, 4, /* INTPRI00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900014, 0, 32, 4, /* INTPRI10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
-
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
@@ -240,29 +222,18 @@ static struct intc_prio_reg intca_prio_r
{ 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
};
-static struct intc_sense_reg intca_sense_registers[] __initdata = {
- { 0xe6900000, 16, 2, /* ICR1A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900004, 16, 2, /* ICR2A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
-};
-
-static struct intc_mask_reg intca_ack_registers[] __initdata = {
- { 0xe6900020, 0, 8, /* INTREQ00A */
- { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
- { 0xe6900024, 0, 8, /* INTREQ10A */
- { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
-};
-
static struct intc_desc intca_desc __initdata = {
.name = "sh7367-intca",
.force_enable = ENABLED,
.force_disable = DISABLED,
.hw = INTC_HW_DESC(intca_vectors, intca_groups,
intca_mask_registers, intca_prio_registers,
- intca_sense_registers, intca_ack_registers),
+ NULL, NULL),
};
+INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
+ INTC_VECT, "sh7367-intca-irq-pins");
+
enum {
UNUSED_INTCS = 0,
@@ -432,6 +403,7 @@ void __init sh7367_init_irq(void)
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
register_intc_controller(&intca_desc);
+ register_intc_controller(&intca_irq_pins_desc);
register_intc_controller(&intcs_desc);
/* demux using INTEVTSA */
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