[PATCH v8 00/05] Renesas R-Car Gen3 CPG support V8

[PATCH v8 00/05] Renesas R-Car Gen3 CPG support V8

[Magnus Damm]

Renesas R-Car Gen3 CPG support V8

[PATCH v8 01/05] clk: shmobile: Rework CONFIG_ARCH_SHMOBILE_MULTI
[PATCH v8 02/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support
[PATCH v8 03/05] clk: shmobile: Add Renesas Module Standby and Reset driver
[PATCH v8 04/05] clk: shmobile: Add r8a7795 MSSR support
[PATCH v8 05/05] drivers: sh: Handle PM_GENERIC_DOMAINS_OF=n with r8a7795 MSSR

Here's an updated R-Car Gen3 clock support patch collection through
a single "easy to use" patch series for drivers/clk and DT documentation
bits. This version of the series moves over from MSTP to MSSR so the
patches below are replaced with patch 3-5 above:

[PATCH v7 02/05] clk: shmobile: Add r8a7795 SoC to MSTP bindings
[PATCH v7 03/05] clk: shmobile: Make MSTP clock-output-names optional
[PATCH v7 05/05] clk: shmobile: rcar-gen3: Add CPG/MSTP Clock Domain support

With this V8 series the integration DT bits for MSTP need to be converted
into MSSR format, an updated integration series will be posted sometime soon.

Apart from MSSR conversion this series requires "clock-output-names" however
patch 2/5 still needs to be updated. Patch 3/5 and/or patch 4/5 also need
to be extended to include DT binding information. Apart from lacking DT
binding documentation I would say that the DT interface is becoming more
and more stable, so soon it should be possible to fix the integration bits.

For more details please see each individual patch.

Thanks to Geert for doing the heavy lifting with the MSSR driver.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Developed against 61a7cf8 in renesas-drivers:

Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt |   58 +
 drivers/clk/Makefile                                                     |    1 
 drivers/clk/shmobile/Makefile                                            |   25 
 drivers/clk/shmobile/clk-mssr.c                                          |  393 ++++++++++
 drivers/clk/shmobile/clk-rcar-gen3.c                                     |  244 ++++++
 drivers/sh/pm_runtime.c                                                  |    5 
 include/linux/clk/shmobile.h                                             |    2 
 7 files changed, 712 insertions(+), 16 deletions(-)

[PATCH v8 01/05] clk: shmobile: Rework CONFIG_ARCH_SHMOBILE_MULTI

[Magnus Damm]

From: Magnus Damm <damm+renesas@opensource.se>

Shmobile is all multiplatform these days, so in get rid of the
reference to CONFIG_ARCH_SHMOBILE_MULTI in drivers/clk/shmobile/.

Also instead of always enabling DIV6 and MSTP adjust the Makefile
to enable DIV6 and MSTP depending on if they are included in the
SoC or not.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---

 Earlier known as "clk: shmobile: Get rid of CONFIG_ARCH_SHMOBILE_MULTI"

 Changes since V7:
 - None

Changes since V6:
 - None

 Changes since V5:
 - None

 Changes since V4:
 - Added Acked-by from Laurent

 Changes since V3:
 - Got rid of hunks that modified drivers/clk/Makefile
 - This to prevent build issue with non-CCF enabled SH arch
 - A nice side effect is that this patch now can be merged any time

 Changes since V2:
 - Fixed patch subject typo CONFIG_SHMOBILE_MULTI -> CONFIG_ARCH_SHMOBILE_MULTI

 Changes since V1:
 - Added Acked-by from Geert

 drivers/clk/shmobile/Makefile |   22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

--- 0001/drivers/clk/shmobile/Makefile
+++ work/drivers/clk/shmobile/Makefile	2015-08-29 16:14:57.522366518 +0900
@@ -1,13 +1,11 @@
 obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
-obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o
-obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o
-obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o
-obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o
-obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
-obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o
-obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o
-obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o
-obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-mstp.o
+obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o clk-mstp.o
+obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o clk-mstp.o
+obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o clk-mstp.o
+obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-mstp.o clk-div6.o

[PATCH v8 02/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support

[Magnus Damm]

From: Magnus Damm <damm+renesas@opensource.se>

This V8 patch adds initial CPG support for R-Car Generation 3 and in
particular the R8A7795 SoC.

The R-Car Gen3 clock hardware has a register write protection feature that
needs to be shared between the CPG function and the MSTP hardware somehow.
So far this feature is simply ignored.

Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Changes since V7: (Magnus Damm <damm+renesas@opensource.se>)
 - Removed clk-mstp.o from r8a7795 Makefile
 - Moved to earlier in the series

 Changes since V6: (Magnus Damm <damm+renesas@opensource.se>)
 - Moved PLL1 div-by-2 unit to outside of the CPG - thanks Laurent!
 - Updated table to reflect PLL1 divider move.
 - Reworked clock registration loop to prevent re-registering clocks.

 Changes since V5: (Magnus Damm <damm+renesas@opensource.se>)
 - Removed unused spinlock, use 0x3f as mask - thanks Laurent!
 - Fixed space -> tab for DT binding documentation - thanks Geert!
 - Postponed PLL1 divide-by-2 rewrite - requires a tad more effort.
 - Updated commit log

 Changes since V4: (Magnus Damm <damm+renesas@opensource.se>)
 - Simplified clks array handling - thanks Geert!
 - Updated th DT binding documentation to reflect latest state
 - of_property_count_strings() -> of_property_count_u32_elems() fix

 Changes since V3: (Magnus Damm <damm+renesas@opensource.se>)
 - Reworked driver to incorporate most feedback from Stephen Boyd - thanks!!
 - Major things like syscon and driver model require more discussion.
 - Added hunk to build drivers/clk/shmobile if ARCH_RENESAS is set.

 Changes since V2: (Magnus Damm <damm+renesas@opensource.se>)
 - Reworked driver to rely on clock index instead of strings.
 - Dropped use of "clock-output-names".

 Earlier versions: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 Initial version: Gaku Inami <gaku.inami.xw@bp.renesas.com>

 Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt |   32 +
 drivers/clk/Makefile                                                     |    1 
 drivers/clk/shmobile/Makefile                                            |    1 
 drivers/clk/shmobile/clk-rcar-gen3.c                                     |  242 ++++++++++
 4 files changed, 276 insertions(+)

--- /dev/null
+++ work/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt	2015-10-01 18:42:49.020513000 +0900
@@ -0,0 +1,32 @@
+* Renesas R-Car Gen3 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
+and several fixed ratio dividers.
+
+Required Properties:
+
+  - compatible: Must be one of
+    - "renesas,r8a7795-cpg-clocks" for the r8a7795 CPG
+    - "renesas,rcar-gen3-cpg-clocks" for the generic R-Car Gen3 CPG
+
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: References to the parent clocks: first to the EXTAL clock
+  - #clock-cells: Must be 1
+  - clock-indices: Indices of the exported clocks
+
+Example
+-------
+
+	cpg_clocks: cpg_clocks@e6150000 {
+		compatible = "renesas,r8a7795-cpg-clocks",
+			     "renesas,rcar-gen3-cpg-clocks";
+		reg = <0 0xe6150000 0 0x1000>;
+		clocks = <&extal_clk>;
+		#clock-cells = <1>;
+		clock-indices = <
+				R8A7795_CLK_MAIN R8A7795_CLK_PLL0
+				R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
+				R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
+		>;
+	};
--- 0001/drivers/clk/Makefile
+++ work/drivers/clk/Makefile	2015-10-01 18:42:48.000513000 +0900
@@ -67,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM)		+= qcom/
 obj-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= shmobile/
+obj-$(CONFIG_ARCH_RENESAS)		+= shmobile/
 obj-$(CONFIG_ARCH_SIRF)			+= sirf/
 obj-$(CONFIG_ARCH_SOCFPGA)		+= socfpga/
 obj-$(CONFIG_PLAT_SPEAR)		+= spear/
--- 0002/drivers/clk/shmobile/Makefile
+++ work/drivers/clk/shmobile/Makefile	2015-10-01 18:42:59.670513000 +0900
@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7795)		+= clk-rcar-gen3.o clk-div6.o
 obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-mstp.o clk-div6.o
--- /dev/null
+++ work/drivers/clk/shmobile/clk-rcar-gen3.c	2015-10-01 18:42:49.020513000 +0900
@@ -0,0 +1,242 @@
+/*
+ * rcar_gen3 Core CPG Clocks
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * Based on rcar_gen2 Core CPG Clocks driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#define RCAR_GEN3_CLK_MAIN	0
+#define RCAR_GEN3_CLK_PLL0	1
+#define RCAR_GEN3_CLK_PLL1	2
+#define RCAR_GEN3_CLK_PLL2	3
+#define RCAR_GEN3_CLK_PLL3	4
+#define RCAR_GEN3_CLK_PLL4	5
+#define RCAR_GEN3_CLK_NR	6
+
+static const char * const rcar_gen3_clk_names[RCAR_GEN3_CLK_NR] = {
+	[RCAR_GEN3_CLK_MAIN] = "main",
+	[RCAR_GEN3_CLK_PLL0] = "pll0",
+	[RCAR_GEN3_CLK_PLL1] = "pll1",
+	[RCAR_GEN3_CLK_PLL2] = "pll2",
+	[RCAR_GEN3_CLK_PLL3] = "pll3",
+	[RCAR_GEN3_CLK_PLL4] = "pll4",
+};
+
+struct rcar_gen3_cpg {
+	struct clk_onecell_data data;
+	void __iomem *reg;
+	struct clk *clks[RCAR_GEN3_CLK_NR];
+};
+
+#define CPG_PLL0CR	0x00d8
+#define CPG_PLL2CR	0x002c
+
+/*
+ * common function
+ */
+#define rcar_clk_readl(cpg, _reg) readl(cpg->reg + _reg)
+
+/*
+ * Reset register definitions.
+ */
+#define MODEMR 0xe6160060
+
+static u32 rcar_gen3_read_mode_pins(void)
+{
+	static u32 mode;
+	static bool mode_valid;
+
+	if (!mode_valid) {
+		void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+
+		BUG_ON(!modemr);
+		mode = ioread32(modemr);
+		iounmap(modemr);
+		mode_valid = true;
+	}
+
+	return mode;
+}
+
+/* -----------------------------------------------------------------------------
+ * CPG Clock Data
+ */
+
+/*
+ *   MD		EXTAL		PLL0	PLL1	PLL2	PLL3	PLL4
+ * 14 13 19 17	(MHz)
+ *-------------------------------------------------------------------
+ * 0  0  0  0	16.66 x 1	x180	x192	x144	x192	x144
+ * 0  0  0  1	16.66 x 1	x180	x192	x144	x128	x144
+ * 0  0  1  0	Prohibited setting
+ * 0  0  1  1	16.66 x 1	x180	x192	x144	x192	x144
+ * 0  1  0  0	20    x 1	x150	x156	x120	x156	x120
+ * 0  1  0  1	20    x 1	x150	x156	x120	x106	x120
+ * 0  1  1  0	Prohibited setting
+ * 0  1  1  1	20    x 1	x150	x156	x120	x156	x120
+ * 1  0  0  0	25    x 1	x120	x128	x96	x128	x96
+ * 1  0  0  1	25    x 1	x120	x128	x96	x84	x96
+ * 1  0  1  0	Prohibited setting
+ * 1  0  1  1	25    x 1	x120	x128	x96	x128	x96
+ * 1  1  0  0	33.33 / 2	x180	x192	x144	x192	x144
+ * 1  1  0  1	33.33 / 2	x180	x192	x144	x128	x144
+ * 1  1  1  0	Prohibited setting
+ * 1  1  1  1	33.33 / 2	x180	x192	x144	x192	x144
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
+					 (((md) & BIT(13)) >> 11) | \
+					 (((md) & BIT(19)) >> 18) | \
+					 (((md) & BIT(17)) >> 17))
+struct cpg_pll_config {
+	unsigned int extal_div;
+	unsigned int pll1_mult;
+	unsigned int pll3_mult;
+	unsigned int pll4_mult;
+};
+
+static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
+/* EXTAL div	PLL1	PLL3	PLL4 */
+	{ 1,	192,	192,	144, },
+	{ 1,	192,	128,	144, },
+	{ 0,	0,	0,	0,   }, /* Prohibited setting */
+	{ 1,	192,	192,	144, },
+	{ 1,	156,	156,	120, },
+	{ 1,	156,	106,	120, },
+	{ 0,	0,	0,	0,   }, /* Prohibited setting */
+	{ 1,	156,	156,	120, },
+	{ 1,	128,	128,	96,  },
+	{ 1,	128,	84,	96,  },
+	{ 0,	0,	0,	0,   }, /* Prohibited setting */
+	{ 1,	128,	128,	96,  },
+	{ 2,	192,	192,	144, },
+	{ 2,	192,	128,	144, },
+	{ 0,	0,	0,	0,   }, /* Prohibited setting */
+	{ 2,	192,	192,	144, },
+};
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static struct clk * __init
+rcar_gen3_cpg_register_clk(struct device_node *np, struct rcar_gen3_cpg *cpg,
+			   const struct cpg_pll_config *config,
+			   unsigned int gen3_clk)
+{
+	const char *parent_name = rcar_gen3_clk_names[RCAR_GEN3_CLK_MAIN];
+	unsigned int mult = 1;
+	unsigned int div = 1;
+	u32 value;
+
+	switch (gen3_clk) {
+	case RCAR_GEN3_CLK_MAIN:
+		parent_name = of_clk_get_parent_name(np, 0);
+		div = config->extal_div;
+		break;
+	case RCAR_GEN3_CLK_PLL0:
+		/* PLL0 is a configurable multiplier clock. Register it as a
+		 * fixed factor clock for now as there's no generic multiplier
+		 * clock implementation and we currently have no need to change
+		 * the multiplier value.
+		 */
+		value = rcar_clk_readl(cpg, CPG_PLL0CR);
+		mult = ((value >> 24) & 0x3f) + 1;
+		break;
+	case RCAR_GEN3_CLK_PLL1:
+		mult = config->pll1_mult;
+		break;
+	case RCAR_GEN3_CLK_PLL2:
+		/* PLL2 is a configurable multiplier clock. Register it as a
+		 * fixed factor clock for now as there's no generic multiplier
+		 * clock implementation and we currently have no need to change
+		 * the multiplier value.
+		 */
+		value = rcar_clk_readl(cpg, CPG_PLL2CR);
+		mult = ((value >> 24) & 0x3f) + 1;
+		break;
+	case RCAR_GEN3_CLK_PLL3:
+		mult = config->pll3_mult;
+		break;
+	case RCAR_GEN3_CLK_PLL4:
+		mult = config->pll4_mult;
+		break;
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_register_fixed_factor(NULL, rcar_gen3_clk_names[gen3_clk],
+					 parent_name, 0, mult, div);
+}
+
+static void __init rcar_gen3_cpg_clocks_init(struct device_node *np)
+{
+	const struct cpg_pll_config *config;
+	struct rcar_gen3_cpg *cpg;
+	u32 cpg_mode;
+	unsigned int i;
+
+	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
+	if (!cpg)
+		return;
+
+	cpg->reg = of_iomap(np, 0);
+	if (WARN_ON(cpg->reg = NULL))
+		return;
+
+	cpg_mode = rcar_gen3_read_mode_pins();
+
+	config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+	if (!config->extal_div) {
+		pr_err("%s: Prohibited setting (cpg_mode=0x%x)\n",
+		       __func__, cpg_mode);
+		return;
+	}
+
+	for (i = 0; i < RCAR_GEN3_CLK_NR; ++i)
+		cpg->clks[i] = ERR_PTR(-ENOENT);
+
+	for (i = 0; i < RCAR_GEN3_CLK_NR; ++i) {
+		struct clk *clk;
+		u32 idx;
+		int ret;
+
+		ret = of_property_read_u32_index(np, "clock-indices", i, &idx);
+		if (ret < 0)
+			break;
+
+		if (idx >= RCAR_GEN3_CLK_NR) {
+			pr_err("%s: skipping unsupported %u\n", __func__, idx);
+		} else if (cpg->clks[idx] != ERR_PTR(-ENOENT)) {
+			pr_err("%s: skipping already registered %u\n",
+			       __func__, idx);
+		} else {
+			clk = rcar_gen3_cpg_register_clk(np, cpg, config, idx);
+
+			if (IS_ERR(clk))
+				pr_err("%s: unable to register %u (%ld)\n",
+				       __func__, idx, PTR_ERR(clk));
+			else
+				cpg->clks[idx] = clk;
+		}
+	}
+
+	cpg->data.clks = cpg->clks;
+	cpg->data.clk_num = i;
+
+	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+}
+CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks",
+	       rcar_gen3_cpg_clocks_init);

[PATCH v8 03/05] clk: shmobile: Add Renesas Module Standby and Reset driver

[Magnus Damm]

From: Geert Uytterhoeven <geert+renesas@glider.be>

Add a driver for the Renesas Module Standby and Software Reset module
found in several Renesas SoCs.

This driver is based on the existing R-Car MSTP driver, and is intended
to replace it.
The existing driver is limited to Module Standby, and has bindings that
are difficult to extend to more register sets for e.g. reset control.

TODO:
  - Implement module reset handling,
  - Write binding documentation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Changes since V7: (Magnus Damm <damm+renesas@opensource.se>)
 - New patch, took local v3 patch from Geert and removed r8a7791 references.

 drivers/clk/shmobile/clk-mssr.c |  392 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/shmobile.h    |    2 
 2 files changed, 394 insertions(+)

--- /dev/null
+++ work/drivers/clk/shmobile/clk-mssr.c	2015-10-01 18:38:50.320513000 +0900
@@ -0,0 +1,392 @@
+/*
+ * Renesas Module Standby and Software Reset
+ *
+ * Based on clk-mstp.c
+ *
+ * Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+/*
+ * MSTP clocks. We can't use standard gate clocks as we need to poll on the
+ * status register when enabling the clock.
+ */
+
+/*
+ * Module Standby and Software Reset register offets.
+ *
+ * If the registers exist, these are valid for SH-Mobile, R-Mobile,
+ * R-Car Gen 2, and R-Car Gen 3.
+ * These are NOT valid for R-Car Gen1 and RZ/A1!
+ */
+
+/*
+ * Module stop status register offsets
+ */
+
+static const u16 mstpsr[] = {
+	0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
+	0x9A0, 0x9A4, 0x9A8, 0x9AC,
+};
+
+#define	MSTPSR(i)	mstpsr[i]
+
+
+/*
+ * System module stop control register offsets
+ */
+
+static const u16 smstpcr[] = {
+	0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
+	0x990, 0x994, 0x998, 0x99C,
+};
+
+#define	SMSTPCR(i)	smstpcr[i]
+
+
+/*
+ * Software reset register offsets
+ */
+
+static const u16 srcr[] = {
+	0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
+	0x920, 0x924, 0x928, 0x92C,
+};
+
+#define	SRCR(i)		srcr[i]
+
+
+/* Realtime module stop control register offsets */
+#define RMSTPCR(i)	(smstpcr[i] - 0x20)
+
+/* Modem module stop control register offsets (r8a73a4) */
+#define MMSTPCR(i)	(smstpcr[i] + 0x20)
+
+/* Software reset clearing register offsets */
+#define	SRSTCLR(i)	(0x940 + (i) * 4)
+
+
+#define MSTP_MAX_REGS		ARRAY_SIZE(smstpcr)
+#define MSTP_MAX_CLOCKS		(MSTP_MAX_REGS * 32)
+
+
+/**
+ * struct mssr_group - Module standby and software reset group
+ *
+ * @data: clocks in this group
+ * @base: CPG/MSSR register block base address
+ * @lock: protects writes to SMSTPCR
+ */
+struct mssr_group {
+	struct clk_onecell_data data;
+	void __iomem *base;
+	spinlock_t lock;
+	// TODO Add reset controller data
+};
+
+/**
+ * struct mstp_clock - MSTP gating clock
+ * @hw: handle between common and hardware-specific interfaces
+ * @index: MSTP clock number
+ * @group: MSTP clocks group
+ */
+struct mstp_clock {
+	struct clk_hw hw;
+	u32 index;
+	struct mssr_group *group;
+};
+
+#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
+
+static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
+{
+	struct mstp_clock *clock = to_mstp_clock(hw);
+	struct mssr_group *group = clock->group;
+	unsigned int reg = clock->index / 32;
+	unsigned int bit = clock->index % 32;
+	u32 bitmask = BIT(bit);
+	unsigned long flags;
+	unsigned int i;
+	u32 value;
+
+	spin_lock_irqsave(&group->lock, flags);
+
+	value = clk_readl(group->base + SMSTPCR(reg));
+	if (enable)
+		value &= ~bitmask;
+	else
+		value |= bitmask;
+	clk_writel(value, group->base + SMSTPCR(reg));
+
+	spin_unlock_irqrestore(&group->lock, flags);
+
+	if (!enable)
+		return 0;
+
+	for (i = 1000; i > 0; --i) {
+		if (!(clk_readl(group->base + MSTPSR(reg)) &
+		      bitmask))
+			break;
+		cpu_relax();
+	}
+
+	if (!i) {
+		pr_err("%s: failed to enable %p[%d]\n", __func__,
+		       group->base + SMSTPCR(reg), bit);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int cpg_mstp_clock_enable(struct clk_hw *hw)
+{
+	return cpg_mstp_clock_endisable(hw, true);
+}
+
+static void cpg_mstp_clock_disable(struct clk_hw *hw)
+{
+	cpg_mstp_clock_endisable(hw, false);
+}
+
+static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
+{
+	struct mstp_clock *clock = to_mstp_clock(hw);
+	struct mssr_group *group = clock->group;
+	u32 value;
+
+	value = clk_readl(group->base + MSTPSR(clock->index / 32));
+
+	return !(value & BIT(clock->index % 32));
+}
+
+static const struct clk_ops cpg_mstp_clock_ops = {
+	.enable = cpg_mstp_clock_enable,
+	.disable = cpg_mstp_clock_disable,
+	.is_enabled = cpg_mstp_clock_is_enabled,
+};
+
+static struct clk * __init
+cpg_mstp_clock_register(const char *name, const char *parent_name,
+			unsigned int index, struct mssr_group *group)
+{
+	struct clk_init_data init;
+	struct mstp_clock *clock;
+	struct clk *clk;
+
+	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
+	if (!clock)
+		return ERR_PTR(-ENOMEM);
+
+	init.name = name;
+	init.ops = &cpg_mstp_clock_ops;
+	init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	clock->index = index;
+	clock->group = group;
+	clock->hw.init = &init;
+
+	clk = clk_register(NULL, &clock->hw);
+
+	if (IS_ERR(clk))
+		kfree(clock);
+
+	return clk;
+}
+
+static struct clk *cpg_mssr_clk_src_get(struct of_phandle_args *clkspec,
+					void *data)
+{
+	struct clk_onecell_data *clk_data = data;
+	unsigned int clkidx = clkspec->args[0];
+	unsigned int reg = clkidx / 100;
+	unsigned int bit = clkidx % 100;
+	unsigned int idx;
+
+	/* Translate from sparse base-100 to packed index space */
+	reg = clkidx / 100;
+	bit = clkidx % 100;
+	idx = reg * 32 + bit;
+	if (bit > 31 || idx >= clk_data->clk_num) {
+		pr_err("%s: invalid clock index %u\n", __func__, clkidx);
+		return ERR_PTR(-EINVAL);
+	}
+
+	return clk_data->clks[idx];
+}
+
+static void __init cpg_mssr_init(struct device_node *np)
+{
+	struct mssr_group *group;
+	struct clk **clks;
+	unsigned int i;
+
+	group = kzalloc(sizeof(*group), GFP_KERNEL);
+	clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);
+	if (group = NULL || clks = NULL) {
+		kfree(group);
+		kfree(clks);
+		return;
+	}
+
+	spin_lock_init(&group->lock);
+	group->data.clks = clks;
+
+	group->base = of_iomap(np, 0);
+
+	if (group->base = NULL) {
+		pr_err("%s: failed to remap CPG/MSSR\n", __func__);
+		kfree(group);
+		kfree(clks);
+		return;
+	}
+
+	for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
+		clks[i] = ERR_PTR(-ENOENT);
+
+	for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
+		const char *parent_name;
+		unsigned int reg, bit;
+		const char *name;
+		u32 clkidx;
+		int ret;
+
+		/* Skip clocks with no name. */
+		ret = of_property_read_string_index(np, "clock-output-names",
+						    i, &name);
+		if (ret < 0 || strlen(name) = 0)
+			continue;
+
+		parent_name = of_clk_get_parent_name(np, i);
+		ret = of_property_read_u32_index(np, "clock-indices", i,
+						 &clkidx);
+		if (parent_name = NULL || ret < 0)
+			break;
+
+		/* Translate from sparse base-100 to packed index space */
+		reg = clkidx / 100;
+		bit = clkidx % 100;
+		if (reg > MSTP_MAX_REGS || bit > 31) {
+			pr_err("%s: invalid clock %s index %u\n", __func__,
+			       name, clkidx);
+			continue;
+		}
+
+		clkidx = reg * 32 + bit;
+
+		clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
+						       clkidx, group);
+		if (!IS_ERR(clks[clkidx])) {
+			group->data.clk_num = max(group->data.clk_num,
+						  clkidx + 1);
+		} else {
+			pr_err("%s: failed to register %s %s clock (%ld)\n",
+			       __func__, np->name, name, PTR_ERR(clks[clkidx]));
+		}
+	}
+
+	of_clk_add_provider(np, cpg_mssr_clk_src_get, &group->data);
+
+	// TODO Register reset controller
+}
+
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+static int cpg_mssr_attach_dev(struct generic_pm_domain *domain,
+			       struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args clkspec;
+	struct clk *clk;
+	int i = 0;
+	int error;
+
+	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+					   &clkspec)) {
+		if (of_device_is_compatible(clkspec.np,
+					    "renesas,r8a7791-cpg-mssr"))
+			goto found;
+
+		of_node_put(clkspec.np);
+		i++;
+	}
+
+	return 0;
+
+found:
+	clk = of_clk_get_from_provider(&clkspec);
+	of_node_put(clkspec.np);
+
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	error = pm_clk_create(dev);
+	if (error) {
+		dev_err(dev, "pm_clk_create failed %d\n", error);
+		goto fail_put;
+	}
+
+	error = pm_clk_add_clk(dev, clk);
+	if (error) {
+		dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
+		goto fail_destroy;
+	}
+
+	return 0;
+
+fail_destroy:
+	pm_clk_destroy(dev);
+fail_put:
+	clk_put(clk);
+	return error;
+}
+
+static void cpg_mssr_detach_dev(struct generic_pm_domain *domain,
+				struct device *dev)
+{
+	if (!list_empty(&dev->power.subsys_data->clock_list))
+		pm_clk_destroy(dev);
+}
+
+void __init cpg_mssr_add_clk_domain(struct device_node *np)
+{
+	struct generic_pm_domain *pd;
+	u32 ncells;
+
+	if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+		pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+		return;
+	}
+
+	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return;
+
+	pd->name = np->name;
+
+	pd->flags = GENPD_FLAG_PM_CLK;
+	pm_genpd_init(pd, &simple_qos_governor, false);
+	pd->attach_dev = cpg_mssr_attach_dev;
+	pd->detach_dev = cpg_mssr_detach_dev;
+
+	of_genpd_add_provider_simple(np, pd);
+}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
--- 0001/include/linux/clk/shmobile.h
+++ work/include/linux/clk/shmobile.h	2015-10-01 18:37:56.290513000 +0900
@@ -28,8 +28,10 @@ void rcar_gen2_clocks_init(u32 mode);
 void cpg_mstp_add_clk_domain(struct device_node *np);
 int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
 void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
+void cpg_mssr_add_clk_domain(struct device_node *np);
 #else
 static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
+static inline void cpg_mssr_add_clk_domain(struct device_node *np) {}
 #endif
 
 #endif

[PATCH v8 04/05] clk: shmobile: Add r8a7795 MSSR support

[Magnus Damm]

From: Magnus Damm <damm+renesas@opensource.se>

Hook up r8a7795 support to the MSSR driver, enable build
for r8a7795, tie it into the r8a7795 CPG driver and add
DT binding documentation.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Changes since V7: (Magnus Damm <damm+renesas@opensource.se>)
 - New patch
 - DT documentation hunks nicked from patch by Geert - thanks!
  [PATCH v7 05/05] clk: shmobile: rcar-gen3: Add CPG/MSTP Clock Domain support

 Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt |   26 +++++++++-
 drivers/clk/shmobile/Makefile                                            |    2 
 drivers/clk/shmobile/clk-mssr.c                                          |    1 
 drivers/clk/shmobile/clk-rcar-gen3.c                                     |    2 
 4 files changed, 28 insertions(+), 3 deletions(-)

--- 0003/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt
+++ work/Documentation/devicetree/bindings/clock/renesas,rcar-gen3-cpg-clocks.txt	2015-10-01 23:23:59.780513000 +0900
@@ -2,6 +2,8 @@
 
 The CPG generates core clocks for the R-Car Gen3 SoCs. It includes three PLLs
 and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 
@@ -14,9 +16,17 @@ Required Properties:
   - clocks: References to the parent clocks: first to the EXTAL clock
   - #clock-cells: Must be 1
   - clock-indices: Indices of the exported clocks
+  - #power-domain-cells: Must be 0
 
-Example
--------
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
+
+Examples
+--------
+
+  - CPG device node:
 
 	cpg_clocks: cpg_clocks@e6150000 {
 		compatible = "renesas,r8a7795-cpg-clocks",
@@ -29,4 +39,16 @@ Example
 				R8A7795_CLK_PLL1 R8A7795_CLK_PLL2
 				R8A7795_CLK_PLL3 R8A7795_CLK_PLL4
 		>;
+		#power-domain-cells = <0>;
+	};
+
+  - CPG/MSTP Clock Domain member device node:
+
+	scif2: serial@e6e88000 {
+		compatible = "renesas,scif-r8a7795", "renesas,scif";
+		reg = <0 0xe6e88000 0 64>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks RCAR_R8A7795_CLK_SCIF2>;
+		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 	};
--- 0003/drivers/clk/shmobile/Makefile
+++ work/drivers/clk/shmobile/Makefile	2015-10-01 18:52:50.160513000 +0900
@@ -8,5 +8,5 @@ obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-
 obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o clk-mstp.o clk-div6.o
-obj-$(CONFIG_ARCH_R8A7795)		+= clk-rcar-gen3.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7795)		+= clk-rcar-gen3.o clk-mssr.o clk-div6.o
 obj-$(CONFIG_ARCH_SH73A0)		+= clk-sh73a0.o clk-mstp.o clk-div6.o
--- 0004/drivers/clk/shmobile/clk-mssr.c
+++ work/drivers/clk/shmobile/clk-mssr.c	2015-10-01 18:52:50.160513000 +0900
@@ -307,6 +307,7 @@ static void __init cpg_mssr_init(struct
 
 	// TODO Register reset controller
 }
+CLK_OF_DECLARE(cpg_mssr, "renesas,r8a7795-cpg-mssr", cpg_mssr_init);
 
 
 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
--- 0003/drivers/clk/shmobile/clk-rcar-gen3.c
+++ work/drivers/clk/shmobile/clk-rcar-gen3.c	2015-10-01 18:52:50.160513000 +0900
@@ -237,6 +237,8 @@ static void __init rcar_gen3_cpg_clocks_
 	cpg->data.clk_num = i;
 
 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+	cpg_mssr_add_clk_domain(np);
 }
 CLK_OF_DECLARE(rcar_gen3_cpg_clks, "renesas,rcar-gen3-cpg-clocks",
 	       rcar_gen3_cpg_clocks_init);

[PATCH v8 05/05] drivers: sh: Handle PM_GENERIC_DOMAINS_OF=n with r8a7795 MSSR

[Magnus Damm]

From: Geert Uytterhoeven <geert+renesas@glider.be>

If the new CPG/MSSR device node is present, but
CONFIG_PM_GENERIC_DOMAINS_OF=n, the legacy clock domain should be
enabled. Else the module clocks are not properly enabled when needed.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
---

 Changes since V7: (Magnus Damm <damm+renesas@opensource.se>)
 - New patch, based on local r8a7791 patch from Geert
   "drivers: sh: Handle CONFIG_PM_GENERIC_DOMAINS_OF=n with new CPG/MSSR"
 - Modified to match on r8a7795

 drivers/sh/pm_runtime.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

--- 0001/drivers/sh/pm_runtime.c
+++ work/drivers/sh/pm_runtime.c	2015-10-01 18:51:47.280513000 +0900
@@ -36,7 +36,10 @@ static int __init sh_pm_runtime_init(voi
 {
 	if (IS_ENABLED(CONFIG_ARCH_SHMOBILE)) {
 		if (!of_find_compatible_node(NULL, NULL,
-					     "renesas,cpg-mstp-clocks"))
+					     "renesas,cpg-mstp-clocks") &&
+		    (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) ||
+		     !of_find_compatible_node(NULL, NULL,
+					     "renesas,r8a7795-cpg-mssr")))
 			return 0;
 		if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) &&
 		    of_find_node_with_property(NULL, "#power-domain-cells"))

Re: [PATCH v8 03/05] clk: shmobile: Add Renesas Module Standby and Reset driver

[Geert Uytterhoeven]

Hi Magnus,

On Thu, Oct 1, 2015 at 4:37 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
> From: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Add a driver for the Renesas Module Standby and Software Reset module
> found in several Renesas SoCs.
>
> This driver is based on the existing R-Car MSTP driver, and is intended
> to replace it.
> The existing driver is limited to Module Standby, and has bindings that
> are difficult to extend to more register sets for e.g. reset control.
>
> TODO:
>   - Implement module reset handling,
>   - Write binding documentation.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>

Thanks, I'm happy you like it!

> ---
>
>  Changes since V7: (Magnus Damm <damm+renesas@opensource.se>)
>  - New patch, took local v3 patch from Geert and removed r8a7791 references.

You forgot one reference indicated below.

>  drivers/clk/shmobile/clk-mssr.c |  392 +++++++++++++++++++++++++++++++++++++++
>  include/linux/clk/shmobile.h    |    2
>  2 files changed, 394 insertions(+)
>
> --- /dev/null
> +++ work/drivers/clk/shmobile/clk-mssr.c        2015-10-01 18:38:50.320513000 +0900
> @@ -0,0 +1,392 @@

> +#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
> +static int cpg_mssr_attach_dev(struct generic_pm_domain *domain,
> +                              struct device *dev)
> +{
> +       struct device_node *np = dev->of_node;
> +       struct of_phandle_args clkspec;
> +       struct clk *clk;
> +       int i = 0;
> +       int error;
> +
> +       while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
> +                                          &clkspec)) {
> +               if (of_device_is_compatible(clkspec.np,
> +                                           "renesas,r8a7791-cpg-mssr"))

renesas,r8a7795-cpg-mssr

Else it won't manage the module clocks, and things may fail miserably.

> +                       goto found;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v8 03/05] clk: shmobile: Add Renesas Module Standby and Reset driver

[Magnus Damm]

Hi Geert,

On Fri, Oct 2, 2015 at 12:28 AM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> Hi Magnus,
>
> On Thu, Oct 1, 2015 at 4:37 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
>> From: Geert Uytterhoeven <geert+renesas@glider.be>
>>
>> Add a driver for the Renesas Module Standby and Software Reset module
>> found in several Renesas SoCs.
>>
>> This driver is based on the existing R-Car MSTP driver, and is intended
>> to replace it.
>> The existing driver is limited to Module Standby, and has bindings that
>> are difficult to extend to more register sets for e.g. reset control.
>>
>> TODO:
>>   - Implement module reset handling,
>>   - Write binding documentation.
>>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
>
> Thanks, I'm happy you like it!

Yeah, it looks good!

I'm interested in learning how to tie in the reset functionality via
DT though, do we need any integration update for that?

>> ---
>>
>>  Changes since V7: (Magnus Damm <damm+renesas@opensource.se>)
>>  - New patch, took local v3 patch from Geert and removed r8a7791 references.
>
> You forgot one reference indicated below.

Oops, thanks for pointing that out!

>>  drivers/clk/shmobile/clk-mssr.c |  392 +++++++++++++++++++++++++++++++++++++++
>>  include/linux/clk/shmobile.h    |    2
>>  2 files changed, 394 insertions(+)
>>
>> --- /dev/null
>> +++ work/drivers/clk/shmobile/clk-mssr.c        2015-10-01 18:38:50.320513000 +0900
>> @@ -0,0 +1,392 @@
>
>> +#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
>> +static int cpg_mssr_attach_dev(struct generic_pm_domain *domain,
>> +                              struct device *dev)
>> +{
>> +       struct device_node *np = dev->of_node;
>> +       struct of_phandle_args clkspec;
>> +       struct clk *clk;
>> +       int i = 0;
>> +       int error;
>> +
>> +       while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
>> +                                          &clkspec)) {
>> +               if (of_device_is_compatible(clkspec.np,
>> +                                           "renesas,r8a7791-cpg-mssr"))
>
> renesas,r8a7795-cpg-mssr
>
> Else it won't manage the module clocks, and things may fail miserably.

Thanks, I've cooked up a fix based on your information and posted it as:
[PATCH] clk: shmobile: Fix r8a7795 MSSR support

Please include the fix in the topic branch. I will fold it in when
updating the series.

Cheers,

/ magnus

Re: [PATCH v8 03/05] clk: shmobile: Add Renesas Module Standby and Reset driver

[Geert Uytterhoeven]

Hi Magnus,

On Fri, Oct 2, 2015 at 6:10 AM, Magnus Damm <magnus.damm@gmail.com> wrote:
> On Fri, Oct 2, 2015 at 12:28 AM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
>> On Thu, Oct 1, 2015 at 4:37 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
>>> From: Geert Uytterhoeven <geert+renesas@glider.be>
>>> Add a driver for the Renesas Module Standby and Software Reset module
>>> found in several Renesas SoCs.
>>>
>>> This driver is based on the existing R-Car MSTP driver, and is intended
>>> to replace it.
>>> The existing driver is limited to Module Standby, and has bindings that
>>> are difficult to extend to more register sets for e.g. reset control.
>>>
>>> TODO:
>>>   - Implement module reset handling,
>>>   - Write binding documentation.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
>>
>> Thanks, I'm happy you like it!
>
> Yeah, it looks good!
>
> I'm interested in learning how to tie in the reset functionality via
> DT though, do we need any integration update for that?

Yes, in addition to the "clocks = <&mssr R8A7795_CLK_xxx>" property, every
device node need a "resets = <&mssr R8A7795_CLK_xxx>" property (and an optional
reset-names property). In the case of e.g. DU, it needs multiple resets, just
like it needs multiple clocks.

Cfr. Documentation/devicetree/bindings/reset/reset.txt

Perhaps the R8A7795_CLK_xxx should be renamed to R8A7795_MOD_xxx?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v8 00/05] Renesas R-Car Gen3 CPG support V8

[Geert Uytterhoeven]

Hi Magnus,

On Thu, Oct 1, 2015 at 4:37 PM, Magnus Damm <magnus.damm@gmail.com> wrote:
> Renesas R-Car Gen3 CPG support V8
>
> [PATCH v8 01/05] clk: shmobile: Rework CONFIG_ARCH_SHMOBILE_MULTI
> [PATCH v8 02/05] clk: shmobile: Add Renesas R-Car Gen3 CPG support
> [PATCH v8 03/05] clk: shmobile: Add Renesas Module Standby and Reset driver
> [PATCH v8 04/05] clk: shmobile: Add r8a7795 MSSR support
> [PATCH v8 05/05] drivers: sh: Handle PM_GENERIC_DOMAINS_OF=n with r8a7795 MSSR

I have pushed this series (incl. "[PATCH] clk: shmobile: Fix r8a7795 MSSR
support") to a new topic/gen3-cpg-v8+fix branch, which is based on v4.3-rc3.

I would have preferred to base it on v4.3-rc1, but the drivers/sh patch depends
on an important change that went into v4.3-rc3. Still, it didn't apply cleanly
as we have more cleanups queued.

Hence for next submission I suggest to split it in two (clk/shmobile and
drivers/sh) parts, so the clk/shmobile part can be applied to v4.3-rc1 by
the clk maintainer.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds