[PATCH 0/6] sh73a0 common clock framework implementation

[PATCH 0/6] sh73a0 common clock framework implementation

[Ulrich Hecht]

Hi!

Here's the CCF implementation for sh73a0. This is quite similar to the
r8a7740 variety, but with more clocks.  Two of them ("dsi0pck" and "vclk3")
are currently listed as DIV6 clocks, but have custom bits and will thus be
moved into the CPG clocks driver in the next iteration.

Contained herein is an updated version of the DIV6 driver that preserves the
input clock settings properly.  This merely happened to work on the r8a7740
(where all important clock sources are set to zero, I suppose), but breaks
on the sh73a0.

This iteration does not yet reflect the change from "renesas,clock-indices"
to "clock-indices".

CU
Uli

Ulrich Hecht (6):
  ARM: shmobile: sh73a0: Common clock framework DT description
  clk: shmobile: sh73a0 common clock framework implementation
  clk: shmobile: div6: support selectable-input clocks
  ARM: shmobile: kzm9g: require ZB1 clock for Ethernet controller
  ARM: shmobile: sh73a0: common clock framework board support
  clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings

 .../bindings/clock/renesas,cpg-div6-clocks.txt     |  11 +-
 .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   2 +
 arch/arm/boot/dts/sh73a0-kzm9g-reference.dts       |   5 +
 arch/arm/boot/dts/sh73a0.dtsi                      | 407 +++++++++++++++++++++
 arch/arm/mach-shmobile/board-kzm9g-reference.c     |  25 ++
 arch/arm/mach-shmobile/setup-sh73a0.c              |   5 +-
 drivers/clk/shmobile/clk-div6.c                    |  32 +-
 drivers/clk/shmobile/clk-sh73a0.c                  | 202 ++++++++++
 include/dt-bindings/clock/sh73a0-clock.h           |  79 ++++
 9 files changed, 760 insertions(+), 8 deletions(-)
 create mode 100644 drivers/clk/shmobile/clk-sh73a0.c
 create mode 100644 include/dt-bindings/clock/sh73a0-clock.h

-- 
1.8.4.5

[PATCH 3/6] clk: shmobile: div6: support selectable-input clocks

[Ulrich Hecht]

From: Ulrich Hecht <ulrich.hecht@gmail.com>

Adds support for DIV6 clocks with selectable parents as found in the r8a7740,
sh73a0, and other SoCs.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
 .../bindings/clock/renesas,cpg-div6-clocks.txt     | 11 +++++++-
 drivers/clk/shmobile/clk-div6.c                    | 32 ++++++++++++++++++----
 2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 952e373..d8c6577 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -7,14 +7,23 @@ to 64.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7740-div6-clock" for R8A7740 DIV6 clocks
     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-MobileAG5) DIV6 clocks
     - "renesas,cpg-div6-clock" for generic DIV6 clocks
   - reg: Base address and length of the memory resource used by the DIV6 clock
-  - clocks: Reference to the parent clock
+  - clocks: Reference to the parent clock(s)
   - #clock-cells: Must be 0
   - clock-output-names: The name of the clock as a free-form string
 
+Optional Properties:
+
+  - renesas,src-shift: Bit position of the input clock selector (default:
+    fixed input clock)
+  - renesas,src-width: Bit width of the input clock selector (default: fixed
+    input clock)
+
 
 Example
 -------
diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
index f065f69..fbd1c31 100644
--- a/drivers/clk/shmobile/clk-div6.c
+++ b/drivers/clk/shmobile/clk-div6.c
@@ -38,9 +38,12 @@ struct div6_clock {
 
 static int cpg_div6_clock_enable(struct clk_hw *hw)
 {
+	unsigned int val;
 	struct div6_clock *clock = to_div6_clock(hw);
 
-	clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+	val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
+		| CPG_DIV6_DIV(clock->div - 1);
+	clk_writel(val, clock->reg);
 
 	return 0;
 }
@@ -52,8 +55,8 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
 	/* DIV6 clocks require the divisor field to be non-zero when stopping
 	 * the clock.
 	 */
-	clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
-		   clock->reg);
+	clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
+		clock->reg);
 }
 
 static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
@@ -94,12 +97,14 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 {
 	struct div6_clock *clock = to_div6_clock(hw);
 	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
+	unsigned int val;
 
 	clock->div = div;
 
+	val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
 	/* Only program the new divisor if the clock isn't stopped. */
-	if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
-		clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
+	if (!(val & CPG_DIV6_CKSTP))
+		clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
 
 	return 0;
 }
@@ -121,6 +126,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
 	const char *name;
 	struct clk *clk;
 	int ret;
+	u32 src_shift, src_width;
 
 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 	if (!clock) {
@@ -150,7 +156,21 @@ static void __init cpg_div6_clock_init(struct device_node *np)
 		goto error;
 	}
 
-	parent_name = of_clk_get_parent_name(np, 0);
+	if (!of_property_read_u32(np, "renesas,src-shift", &src_shift)) {
+		if (!of_property_read_u32(np, "renesas,src-width",
+					&src_width)) {
+			unsigned int parent_idx +				(clk_readl(clock->reg) >> src_shift) &
+				(BIT(src_width) - 1);
+			parent_name = of_clk_get_parent_name(np, parent_idx);
+		} else {
+			pr_err("%s: renesas,src-shift without renesas,"
+			       "src-width in %s\n", __func__, np->name);
+			goto error;
+		}
+	} else
+		parent_name = of_clk_get_parent_name(np, 0);
+
 	if (parent_name = NULL) {
 		pr_err("%s: failed to get %s DIV6 clock parent name\n",
 		       __func__, np->name);
-- 
1.8.4.5

Re: [PATCH 3/6] clk: shmobile: div6: support selectable-input clocks

[Geert Uytterhoeven]

Hi Ulrich,

CC devicetree@vger.kernel.org
and a few comments below

On Tue, May 6, 2014 at 4:23 PM, Ulrich Hecht <ulrich.hecht@gmail.com> wrote:
> From: Ulrich Hecht <ulrich.hecht@gmail.com>
>
> Adds support for DIV6 clocks with selectable parents as found in the r8a7740,
> sh73a0, and other SoCs.
>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> ---
>  .../bindings/clock/renesas,cpg-div6-clocks.txt     | 11 +++++++-
>  drivers/clk/shmobile/clk-div6.c                    | 32 ++++++++++++++++++----
>  2 files changed, 36 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
> index 952e373..d8c6577 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
> @@ -7,14 +7,23 @@ to 64.
>  Required Properties:
>
>    - compatible: Must be one of the following
> +    - "renesas,r8a7740-div6-clock" for R8A7740 DIV6 clocks
>      - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
>      - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
> +    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-MobileAG5) DIV6 clocks
>      - "renesas,cpg-div6-clock" for generic DIV6 clocks
>    - reg: Base address and length of the memory resource used by the DIV6 clock
> -  - clocks: Reference to the parent clock
> +  - clocks: Reference to the parent clock(s)
>    - #clock-cells: Must be 0
>    - clock-output-names: The name of the clock as a free-form string
>
> +Optional Properties:
> +
> +  - renesas,src-shift: Bit position of the input clock selector (default:
> +    fixed input clock)
> +  - renesas,src-width: Bit width of the input clock selector (default: fixed
> +    input clock)
> +
>
>  Example
>  -------
> diff --git a/drivers/clk/shmobile/clk-div6.c b/drivers/clk/shmobile/clk-div6.c
> index f065f69..fbd1c31 100644
> --- a/drivers/clk/shmobile/clk-div6.c
> +++ b/drivers/clk/shmobile/clk-div6.c
> @@ -38,9 +38,12 @@ struct div6_clock {
>
>  static int cpg_div6_clock_enable(struct clk_hw *hw)
>  {
> +       unsigned int val;

As clk_readl() returns u32, please use u32 for val, too.

>         struct div6_clock *clock = to_div6_clock(hw);
>
> -       clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
> +       val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
> +               | CPG_DIV6_DIV(clock->div - 1);
> +       clk_writel(val, clock->reg);
>
>         return 0;
>  }
> @@ -52,8 +55,8 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
>         /* DIV6 clocks require the divisor field to be non-zero when stopping
>          * the clock.
>          */
> -       clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK),
> -                  clock->reg);
> +       clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
> +               clock->reg);
>  }
>
>  static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
> @@ -94,12 +97,14 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
>  {
>         struct div6_clock *clock = to_div6_clock(hw);
>         unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
> +       unsigned int val;

u32

>
>         clock->div = div;
>
> +       val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
>         /* Only program the new divisor if the clock isn't stopped. */
> -       if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP))
> -               clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg);
> +       if (!(val & CPG_DIV6_CKSTP))
> +               clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
>
>         return 0;
>  }
> @@ -121,6 +126,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
>         const char *name;
>         struct clk *clk;
>         int ret;
> +       u32 src_shift, src_width;
>
>         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
>         if (!clock) {
> @@ -150,7 +156,21 @@ static void __init cpg_div6_clock_init(struct device_node *np)
>                 goto error;
>         }
>
> -       parent_name = of_clk_get_parent_name(np, 0);
> +       if (!of_property_read_u32(np, "renesas,src-shift", &src_shift)) {
> +               if (!of_property_read_u32(np, "renesas,src-width",
> +                                       &src_width)) {
> +                       unsigned int parent_idx > +                               (clk_readl(clock->reg) >> src_shift) &
> +                               (BIT(src_width) - 1);
> +                       parent_name = of_clk_get_parent_name(np, parent_idx);
> +               } else {
> +                       pr_err("%s: renesas,src-shift without renesas,"
> +                              "src-width in %s\n", __func__, np->name);

Please don't split the string literal, as it makes it more difficult to look
up the error message this way.

> +                       goto error;
> +               }
> +       } else
> +               parent_name = of_clk_get_parent_name(np, 0);
> +
>         if (parent_name = NULL) {
>                 pr_err("%s: failed to get %s DIV6 clock parent name\n",
>                        __func__, np->name);
> --
> 1.8.4.5

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 6/6] clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings

[Ulrich Hecht]

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 5992dce..8514088 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,8 +10,10 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7740-mstp-clocks" for R8A7740 MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+    - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
   - reg: Base address and length of the I/O mapped registers used by the MSTP
     clocks. The first register is the clock control register and is mandatory.
-- 
1.8.4.5

Re: [PATCH 6/6] clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings

[Geert Uytterhoeven]

Hi Ulrich,

Thanks for your patch!

CC devicetree + one comment below

On Tue, May 6, 2014 at 4:23 PM, Ulrich Hecht <ulrich.hecht@gmail.com> wrote:
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> index 5992dce..8514088 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
> @@ -10,8 +10,10 @@ index in the group, from 0 to 31.
>  Required Properties:
>
>    - compatible: Must be one of the following
> +    - "renesas,r8a7740-mstp-clocks" for R8A7740 MSTP gate clocks

Also known as "R-Mobile A1"

>      - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
>      - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
> +    - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
>      - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
>    - reg: Base address and length of the I/O mapped registers used by the MSTP
>      clocks. The first register is the clock control register and is mandatory.
> --
> 1.8.4.5

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds