* [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11
@ 2013-05-26 13:05 Simon Horman
2013-05-26 13:05 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock Simon Horman
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit c7788792a5e7b0d5d7f96d0766b4cb6112d47d75:
Linux 3.10-rc2 (2013-05-20 14:37:38 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc-r8a73a4-for-v3.11
for you to fetch changes up to d7f17c1c0ddbd61ad24ae93ad9ec21fc223659ba:
ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits (2013-05-26 20:17:43 +0900)
----------------------------------------------------------------
Renesas ARM based r8a73a0 SoC updates for v3.11
Clean-up from Maxime Ripard to remove unnecessary init_irq declaration in
machine description.
Clean-up from Magnus Damm to remove unused GIC CPU interface portions
of r8a73a4.dtsi
Increased clock coverage from Kuninori Morimoto.
----------------------------------------------------------------
Kuninori Morimoto (4):
ARM: shmobile: r8a73a4: add main clock
ARM: shmobile: r8a73a4: add pll clocks
ARM: shmobile: r8a73a4: add div4 clocks
ARM: shmobile: r8a73a4: add div6 clocks
Magnus Damm (1):
ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits
Maxime Ripard (1):
ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description
arch/arm/boot/dts/r8a73a4.dtsi | 6 -
arch/arm/mach-shmobile/clock-r8a73a4.c | 375 ++++++++++++++++++++++++++++++--
arch/arm/mach-shmobile/setup-r8a73a4.c | 2 -
3 files changed, 359 insertions(+), 24 deletions(-)
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman @ 2013-05-26 13:05 ` Simon Horman 2013-07-04 20:38 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it Guennadi Liakhovetski 2013-07-05 1:21 ` Magnus Damm 2013-05-26 13:05 ` [PATCH 2/6] ARM: shmobile: r8a73a4: add pll clocks Simon Horman ` (4 subsequent siblings) 5 siblings, 2 replies; 9+ messages in thread From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw) To: linux-arm-kernel From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Almost all clock needs main clock which is basis clock on r8a73a4. This patch adds it, and, set parent clock via CKSCR register. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/clock-r8a73a4.c | 53 ++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index e710c00..42942b4 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -22,6 +22,7 @@ #include <linux/kernel.h> #include <linux/sh_clk.h> #include <linux/clkdev.h> +#include <mach/clock.h> #include <mach/common.h> #define CPG_BASE 0xe6150000 @@ -31,6 +32,8 @@ #define SMSTPCR2 0xe6150138 #define SMSTPCR5 0xe6150144 +#define CKSCR 0xE61500C0 + static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, .len = CPG_LEN, @@ -51,10 +54,32 @@ static struct clk extal2_clk = { .mapping = &cpg_mapping, }; +static struct sh_clk_ops followparent_clk_ops = { + .recalc = followparent_recalc, +}; + +static struct clk main_clk = { + /* .parent will be set r8a73a4_clock_init */ + .ops = &followparent_clk_ops, +}; + +SH_CLK_RATIO(div2, 1, 2); +SH_CLK_RATIO(div4, 1, 4); + +SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2); +SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); +SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); + static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, + &extal1_div2_clk, &extal2_clk, + &extal2_div2_clk, + &extal2_div4_clk, + &main_clk, + &main_div2_clk, }; enum { @@ -74,6 +99,13 @@ static struct clk mstp_clks[MSTP_NR] = { }; static struct clk_lookup lookups[] = { + /* main clock */ + CLKDEV_CON_ID("extal1", &extal1_clk), + CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk), + CLKDEV_CON_ID("extal2", &extal2_clk), + CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), + CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), + CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), @@ -90,6 +122,7 @@ void __init r8a73a4_clock_init(void) { void __iomem *cpg_base, *reg; int k, ret = 0; + u32 ckscr; /* fix MPCLK to EXTAL2 for now. * this is needed until more detailed clock topology is supported @@ -100,6 +133,26 @@ void __init r8a73a4_clock_init(void) iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ iounmap(cpg_base); + reg = ioremap_nocache(CKSCR, PAGE_SIZE); + BUG_ON(!reg); + ckscr = ioread32(reg); + iounmap(reg); + + switch ((ckscr >> 28) & 0x3) { + case 0: + main_clk.parent = &extal1_clk; + break; + case 1: + main_clk.parent = &extal1_div2_clk; + break; + case 2: + main_clk.parent = &extal2_clk; + break; + case 3: + main_clk.parent = &extal2_div2_clk; + break; + } + for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) ret = clk_register(main_clks[k]); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/6] ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it 2013-05-26 13:05 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock Simon Horman @ 2013-07-04 20:38 ` Guennadi Liakhovetski 2013-07-05 1:21 ` Magnus Damm 1 sibling, 0 replies; 9+ messages in thread From: Guennadi Liakhovetski @ 2013-07-04 20:38 UTC (permalink / raw) To: linux-sh Add a DMAC platform device and clock definitions for it on r8a73a4. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> --- arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +- arch/arm/mach-shmobile/include/mach/r8a73a4.h | 15 +++ arch/arm/mach-shmobile/setup-r8a73a4.c | 117 +++++++++++++++++++++++++ 3 files changed, 135 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 8ea5ef6..357b9bc 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = { /* MSTP */ enum { - MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, + MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP329, MSTP323, MSTP318, MSTP317, MSTP316, MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300, MSTP411, MSTP410, MSTP409, @@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */ [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */ [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ @@ -578,6 +579,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h index 144a85e..12a4ee9 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h @@ -1,6 +1,21 @@ #ifndef __ASM_R8A73A4_H__ #define __ASM_R8A73A4_H__ +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_MMCIF0_TX, + SHDMA_SLAVE_MMCIF0_RX, + SHDMA_SLAVE_MMCIF1_TX, + SHDMA_SLAVE_MMCIF1_RX, +}; + void r8a73a4_add_standard_devices(void); void r8a73a4_clock_init(void); void r8a73a4_pinmux_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index d533bd2..6aa80645 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -22,8 +22,10 @@ #include <linux/of_platform.h> #include <linux/platform_data/irq-renesas-irqc.h> #include <linux/serial_sci.h> +#include <linux/sh_dma.h> #include <linux/sh_timer.h> #include <mach/common.h> +#include <mach/dma-register.h> #include <mach/irqs.h> #include <mach/r8a73a4.h> #include <asm/mach/arch.h> @@ -188,6 +190,118 @@ static struct resource cmt10_resources[] = { &cmt##idx##_platform_data, \ sizeof(struct sh_timer_config)) +/* DMA */ +static const struct sh_dmae_slave_config dma_slaves[] = { + { + .slave_id = SHDMA_SLAVE_SDHI0_TX, + .addr = 0xee100030, + .chcr = CHCR_TX(XMIT_SZ_16BIT), + .mid_rid = 0xc1, + }, { + .slave_id = SHDMA_SLAVE_SDHI0_RX, + .addr = 0xee100030, + .chcr = CHCR_RX(XMIT_SZ_16BIT), + .mid_rid = 0xc2, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_TX, + .addr = 0xee120030, + .chcr = CHCR_TX(XMIT_SZ_16BIT), + .mid_rid = 0xc9, + }, { + .slave_id = SHDMA_SLAVE_SDHI1_RX, + .addr = 0xee120030, + .chcr = CHCR_RX(XMIT_SZ_16BIT), + .mid_rid = 0xca, + }, { + .slave_id = SHDMA_SLAVE_SDHI2_TX, + .addr = 0xee140030, + .chcr = CHCR_TX(XMIT_SZ_16BIT), + .mid_rid = 0xcd, + }, { + .slave_id = SHDMA_SLAVE_SDHI2_RX, + .addr = 0xee140030, + .chcr = CHCR_RX(XMIT_SZ_16BIT), + .mid_rid = 0xce, + }, { + .slave_id = SHDMA_SLAVE_MMCIF0_TX, + .addr = 0xee200034, + .chcr = CHCR_TX(XMIT_SZ_32BIT), + .mid_rid = 0xd1, + }, { + .slave_id = SHDMA_SLAVE_MMCIF0_RX, + .addr = 0xee200034, + .chcr = CHCR_RX(XMIT_SZ_32BIT), + .mid_rid = 0xd2, + }, { + .slave_id = SHDMA_SLAVE_MMCIF1_TX, + .addr = 0xee220034, + .chcr = CHCR_TX(XMIT_SZ_32BIT), + .mid_rid = 0xe1, + }, { + .slave_id = SHDMA_SLAVE_MMCIF1_RX, + .addr = 0xee220034, + .chcr = CHCR_RX(XMIT_SZ_32BIT), + .mid_rid = 0xe2, + }, +}; + +#define DMAE_CHANNEL(a, b) \ + { \ + .offset = (a) - 0x20, \ + .dmars = (a) - 0x20 + 0x40, \ + .chclr_bit = (b), \ + .chclr_offset = 0x80 - 0x20, \ + } + +static const struct sh_dmae_channel dma_channels[] = { + DMAE_CHANNEL(0x8000, 0), + DMAE_CHANNEL(0x8080, 1), + DMAE_CHANNEL(0x8100, 2), + DMAE_CHANNEL(0x8180, 3), + DMAE_CHANNEL(0x8200, 4), + DMAE_CHANNEL(0x8280, 5), + DMAE_CHANNEL(0x8300, 6), + DMAE_CHANNEL(0x8380, 7), + DMAE_CHANNEL(0x8400, 8), + DMAE_CHANNEL(0x8480, 9), + DMAE_CHANNEL(0x8500, 10), + DMAE_CHANNEL(0x8580, 11), + DMAE_CHANNEL(0x8600, 12), + DMAE_CHANNEL(0x8680, 13), + DMAE_CHANNEL(0x8700, 14), + DMAE_CHANNEL(0x8780, 15), + DMAE_CHANNEL(0x8800, 16), + DMAE_CHANNEL(0x8880, 17), + DMAE_CHANNEL(0x8900, 18), + DMAE_CHANNEL(0x8980, 19), +}; + +static struct sh_dmae_pdata dma_platform_data = { + .slave = dma_slaves, + .slave_num = ARRAY_SIZE(dma_slaves), + .channel = dma_channels, + .channel_num = ARRAY_SIZE(dma_channels), + .ts_low_shift = TS_LOW_SHIFT, + .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, + .ts_high_shift = TS_HI_SHIFT, + .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, + .ts_shift = dma_ts_shift, + .ts_shift_num = ARRAY_SIZE(dma_ts_shift), + .dmaor_init = DMAOR_DME, + .chclr_present = 1, +}; + +static struct resource dma_resources[] = { + DEFINE_RES_MEM(0xe6700020, 0x89e0), + DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), + { + /* IRQ for channels 0-19 */ + .start = gic_spi(200), + .end = gic_spi(219), + .flags = IORESOURCE_IRQ, + }, +}; + void __init r8a73a4_add_standard_devices(void) { r8a73a4_register_scif(SCIFA0); @@ -200,6 +314,9 @@ void __init r8a73a4_add_standard_devices(void) r8a73a4_register_irqc(1); r8a73a4_register_thermal(); r8a7790_register_cmt(10); + platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, + dma_resources, ARRAY_SIZE(dma_resources), + &dma_platform_data, sizeof(dma_platform_data)); } void __init r8a73a4_init_delay(void) -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/6] ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it 2013-05-26 13:05 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock Simon Horman 2013-07-04 20:38 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it Guennadi Liakhovetski @ 2013-07-05 1:21 ` Magnus Damm 1 sibling, 0 replies; 9+ messages in thread From: Magnus Damm @ 2013-07-05 1:21 UTC (permalink / raw) To: linux-sh On Fri, Jul 5, 2013 at 5:38 AM, Guennadi Liakhovetski <g.liakhovetski@gmx.de> wrote: > Add a DMAC platform device and clock definitions for it on r8a73a4. > > Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> > --- > arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +- > arch/arm/mach-shmobile/include/mach/r8a73a4.h | 15 +++ > arch/arm/mach-shmobile/setup-r8a73a4.c | 117 +++++++++++++++++++++++++ > 3 files changed, 135 insertions(+), 1 deletions(-) > > @@ -200,6 +314,9 @@ void __init r8a73a4_add_standard_devices(void) > r8a73a4_register_irqc(1); > r8a73a4_register_thermal(); > r8a7790_register_cmt(10); > + platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, > + dma_resources, ARRAY_SIZE(dma_resources), > + &dma_platform_data, sizeof(dma_platform_data)); > } This goes without saying, but please follow the same style as previous commits for this file. So, in detail, instead of adding the platform_device_register_resndata() directly then add a macro that makes this more readable. Thanks, / magnus ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/6] ARM: shmobile: r8a73a4: add pll clocks 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman 2013-05-26 13:05 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock Simon Horman @ 2013-05-26 13:05 ` Simon Horman 2013-05-26 13:05 ` [PATCH 3/6] ARM: shmobile: r8a73a4: add div4 clocks Simon Horman ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw) To: linux-arm-kernel From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> PLL clocks are basis clock for other clock. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/clock-r8a73a4.c | 101 ++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 42942b4..2be592f 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -33,6 +33,14 @@ #define SMSTPCR5 0xe6150144 #define CKSCR 0xE61500C0 +#define PLLECR 0xE61500D0 +#define PLL1CR 0xE6150028 +#define PLL2CR 0xE615002C +#define PLL2SCR 0xE61501F4 +#define PLL2HCR 0xE61501E4 + + +#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) static struct clk_mapping cpg_mapping = { .phys = CPG_BASE, @@ -71,6 +79,86 @@ SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); +/* + * PLL clocks + */ +static struct clk *pll_parent_main[] = { + [0] = &main_clk, + [1] = &main_div2_clk +}; + +static struct clk *pll_parent_main_extal[8] = { + [0] = &main_div2_clk, + [1] = &extal2_div2_clk, + [3] = &extal2_div4_clk, + [4] = &main_clk, + [5] = &extal2_clk, +}; + +static unsigned long pll_recalc(struct clk *clk) +{ + unsigned long mult = 1; + + if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit)) + mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1); + + return clk->parent->rate * mult; +} + +static int pll_set_parent(struct clk *clk, struct clk *parent) +{ + u32 val; + int i, ret; + + if (!clk->parent_table || !clk->parent_num) + return -EINVAL; + + /* Search the parent */ + for (i = 0; i < clk->parent_num; i++) + if (clk->parent_table[i] = parent) + break; + + if (i = clk->parent_num) + return -ENODEV; + + ret = clk_reparent(clk, parent); + if (ret < 0) + return ret; + + val = ioread32(clk->mapped_reg) & + ~(((1 << clk->src_width) - 1) << clk->src_shift); + + iowrite32(val | i << clk->src_shift, clk->mapped_reg); + + return 0; +} + +static struct sh_clk_ops pll_clk_ops = { + .recalc = pll_recalc, + .set_parent = pll_set_parent, +}; + +#define PLL_CLOCK(name, p, pt, w, s, reg, e) \ + static struct clk name = { \ + .ops = &pll_clk_ops, \ + .flags = CLK_ENABLE_ON_INIT, \ + .parent = p, \ + .parent_table = pt, \ + .parent_num = ARRAY_SIZE(pt), \ + .src_width = w, \ + .src_shift = s, \ + .enable_reg = (void __iomem *)reg, \ + .enable_bit = e, \ + .mapping = &cpg_mapping, \ + } + +PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); +PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); +PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); +PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5); + +SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); + static struct clk *main_clks[] = { &extalr_clk, &extal1_clk, @@ -80,6 +168,11 @@ static struct clk *main_clks[] = { &extal2_div4_clk, &main_clk, &main_div2_clk, + &pll1_clk, + &pll1_div2_clk, + &pll2_clk, + &pll2s_clk, + &pll2h_clk, }; enum { @@ -106,6 +199,14 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), + /* pll clock */ + CLKDEV_CON_ID("pll1", &pll1_clk), + CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), + CLKDEV_CON_ID("pll2", &pll2_clk), + CLKDEV_CON_ID("pll2s", &pll2s_clk), + CLKDEV_CON_ID("pll2h", &pll2h_clk), + + /* MSTP */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/6] ARM: shmobile: r8a73a4: add div4 clocks 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman 2013-05-26 13:05 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock Simon Horman 2013-05-26 13:05 ` [PATCH 2/6] ARM: shmobile: r8a73a4: add pll clocks Simon Horman @ 2013-05-26 13:05 ` Simon Horman 2013-05-26 13:05 ` [PATCH 4/6] ARM: shmobile: r8a73a4: add div6 clocks Simon Horman ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw) To: linux-arm-kernel From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> DIV4 clocks control each core clocks. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/clock-r8a73a4.c | 45 ++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 2be592f..147314a 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -32,6 +32,8 @@ #define SMSTPCR2 0xe6150138 #define SMSTPCR5 0xe6150144 +#define FRQCRA 0xE6150000 +#define FRQCRB 0xE6150004 #define CKSCR 0xE61500C0 #define PLLECR 0xE61500D0 #define PLL1CR 0xE6150028 @@ -175,6 +177,46 @@ static struct clk *main_clks[] = { &pll2h_clk, }; +/* DIV4 */ +static void div4_kick(struct clk *clk) +{ + unsigned long value; + + /* set KICK bit in FRQCRB to update hardware setting */ + value = ioread32(CPG_MAP(FRQCRB)); + value |= (1 << 31); + iowrite32(value, CPG_MAP(FRQCRB)); +} + +static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; + +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = divisors, + .nr_divisors = ARRAY_SIZE(divisors), +}; + +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, + .kick = div4_kick, +}; + +enum { + DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, + DIV4_ZX, DIV4_ZS, DIV4_HP, + DIV4_NR }; + +static struct clk div4_clks[DIV4_NR] = { + [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT), + [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT), + [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0), + [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0), + [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0), + [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0), + [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), +}; + +/* MSTP */ enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP522, @@ -258,6 +300,9 @@ void __init r8a73a4_clock_init(void) ret = clk_register(main_clks[k]); if (!ret) + ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); + + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/6] ARM: shmobile: r8a73a4: add div6 clocks 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman ` (2 preceding siblings ...) 2013-05-26 13:05 ` [PATCH 3/6] ARM: shmobile: r8a73a4: add div4 clocks Simon Horman @ 2013-05-26 13:05 ` Simon Horman 2013-05-26 13:05 ` [PATCH 5/6] ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description Simon Horman 2013-05-26 13:05 ` [PATCH 6/6] ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits Simon Horman 5 siblings, 0 replies; 9+ messages in thread From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw) To: linux-arm-kernel From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> DIV6 clocks control each core clocks. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/clock-r8a73a4.c | 182 ++++++++++++++++++++++++++++---- 1 file changed, 163 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 147314a..f6227bb 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -28,19 +28,34 @@ #define CPG_BASE 0xe6150000 #define CPG_LEN 0x270 -#define MPCKCR 0xe6150080 #define SMSTPCR2 0xe6150138 #define SMSTPCR5 0xe6150144 #define FRQCRA 0xE6150000 #define FRQCRB 0xE6150004 -#define CKSCR 0xE61500C0 +#define VCLKCR1 0xE6150008 +#define VCLKCR2 0xE615000C +#define VCLKCR3 0xE615001C +#define VCLKCR4 0xE6150014 +#define VCLKCR5 0xE6150034 +#define ZBCKCR 0xE6150010 +#define SD0CKCR 0xE6150074 +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615007C +#define MMC0CKCR 0xE6150240 +#define MMC1CKCR 0xE6150244 +#define FSIACKCR 0xE6150018 +#define FSIBCKCR 0xE6150090 +#define MPCKCR 0xe6150080 +#define SPUVCKCR 0xE6150094 +#define HSICKCR 0xE615026C +#define M4CKCR 0xE6150098 #define PLLECR 0xE61500D0 #define PLL1CR 0xE6150028 #define PLL2CR 0xE615002C #define PLL2SCR 0xE61501F4 #define PLL2HCR 0xE61501E4 - +#define CKSCR 0xE61500C0 #define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base) @@ -81,6 +96,13 @@ SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2); SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2); SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4); +/* External FSIACK/FSIBCK clock */ +static struct clk fsiack_clk = { +}; + +static struct clk fsibck_clk = { +}; + /* * PLL clocks */ @@ -170,6 +192,8 @@ static struct clk *main_clks[] = { &extal2_div4_clk, &main_clk, &main_div2_clk, + &fsiack_clk, + &fsibck_clk, &pll1_clk, &pll1_div2_clk, &pll2_clk, @@ -216,6 +240,111 @@ static struct clk div4_clks[DIV4_NR] = { [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0), }; +enum { + DIV6_ZB, + DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, + DIV6_MMC0, DIV6_MMC1, + DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5, + DIV6_FSIA, DIV6_FSIB, + DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV, + DIV6_NR }; + +static struct clk *div6_parents[8] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [3] = &extal2_clk, + [4] = &main_div2_clk, + [6] = &extalr_clk, +}; + +static struct clk *fsia_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &fsiack_clk, +}; + +static struct clk *fsib_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &fsibck_clk, +}; + +static struct clk *mp_parents[4] = { + [0] = &pll1_div2_clk, + [1] = &pll2s_clk, + [2] = &extal2_clk, + [3] = &extal2_clk, +}; + +static struct clk *m4_parents[2] = { + [0] = &pll2s_clk, +}; + +static struct clk *hsi_parents[4] = { + [0] = &pll2h_clk, + [1] = &pll1_div2_clk, + [3] = &pll2s_clk, +}; + +/*** FIXME *** + * SH_CLK_DIV6_EXT() macro doesn't care .mapping + * but, it is necessary on R-Car (= ioremap() base CPG) + * The difference between + * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT() + * is only .mapping + */ +#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \ + _num_parents, _src_shift, _src_width) \ +{ \ + .enable_reg = (void __iomem *)_reg, \ + .enable_bit = 0, /* unused */ \ + .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \ + .div_mask = SH_CLK_DIV6_MSK, \ + .parent_table = _parents, \ + .parent_num = _num_parents, \ + .src_shift = _src_shift, \ + .src_width = _src_width, \ + .mapping = &cpg_mapping, \ +} + +static struct clk div6_clks[DIV6_NR] = { + [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT, + div6_parents, 2, 7, 1), + [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0, + div6_parents, 2, 6, 2), + [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */ + div6_parents, ARRAY_SIZE(div6_parents), 12, 3), + [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0, + fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2), + [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0, + fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), + [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */ + mp_parents, ARRAY_SIZE(mp_parents), 6, 2), + /* pll2s will be selected always for M4 */ + [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */ + m4_parents, ARRAY_SIZE(m4_parents), 6, 1), + [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */ + hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2), + [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0, + mp_parents, ARRAY_SIZE(mp_parents), 6, 2), +}; + /* MSTP */ enum { MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, @@ -224,12 +353,12 @@ enum { }; static struct clk mstp_clks[MSTP_NR] = { - [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ - [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ - [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ - [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ - [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ - [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */ + [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */ + [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */ + [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */ + [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ + [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ + [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ }; @@ -240,6 +369,8 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("extal2", &extal2_clk), CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk), CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk), + CLKDEV_CON_ID("fsiack", &fsiack_clk), + CLKDEV_CON_ID("fsibck", &fsibck_clk), /* pll clock */ CLKDEV_CON_ID("pll1", &pll1_clk), @@ -248,6 +379,25 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("pll2s", &pll2s_clk), CLKDEV_CON_ID("pll2h", &pll2h_clk), + /* DIV6 */ + CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), + CLKDEV_CON_ID("sdhi0", &div6_clks[DIV6_SDHI0]), + CLKDEV_CON_ID("sdhi1", &div6_clks[DIV6_SDHI1]), + CLKDEV_CON_ID("sdhi2", &div6_clks[DIV6_SDHI2]), + CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]), + CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]), + CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), + CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]), + CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]), + CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]), + CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]), + CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]), + CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]), + CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]), + CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]), + CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]), + CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]), + /* MSTP */ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), @@ -263,19 +413,10 @@ static struct clk_lookup lookups[] = { void __init r8a73a4_clock_init(void) { - void __iomem *cpg_base, *reg; + void __iomem *reg; int k, ret = 0; u32 ckscr; - /* fix MPCLK to EXTAL2 for now. - * this is needed until more detailed clock topology is supported - */ - cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN); - BUG_ON(!cpg_base); - reg = cpg_base + (MPCKCR - CPG_BASE); - iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */ - iounmap(cpg_base); - reg = ioremap_nocache(CKSCR, PAGE_SIZE); BUG_ON(!reg); ckscr = ioread32(reg); @@ -303,6 +444,9 @@ void __init r8a73a4_clock_init(void) ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); if (!ret) + ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); + + if (!ret) ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); clkdev_add_table(lookups, ARRAY_SIZE(lookups)); -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/6] ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman ` (3 preceding siblings ...) 2013-05-26 13:05 ` [PATCH 4/6] ARM: shmobile: r8a73a4: add div6 clocks Simon Horman @ 2013-05-26 13:05 ` Simon Horman 2013-05-26 13:05 ` [PATCH 6/6] ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits Simon Horman 5 siblings, 0 replies; 9+ messages in thread From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw) To: linux-arm-kernel From: Maxime Ripard <maxime.ripard@free-electrons.com> Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is specified") removed the need to explictly setup the init_irq field in the machine description when using only irqchip_init. Remove that declaration for shmobile as well. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/mach-shmobile/setup-r8a73a4.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index c5a75a7..0b78896 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <linux/irq.h> -#include <linux/irqchip.h> #include <linux/kernel.h> #include <linux/of_platform.h> #include <linux/platform_data/irq-renesas-irqc.h> @@ -194,7 +193,6 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = { }; DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") - .init_irq = irqchip_init, .init_machine = r8a73a4_add_standard_devices_dt, .init_time = shmobile_timer_init, .dt_compat = r8a73a4_boards_compat_dt, -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/6] ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman ` (4 preceding siblings ...) 2013-05-26 13:05 ` [PATCH 5/6] ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description Simon Horman @ 2013-05-26 13:05 ` Simon Horman 5 siblings, 0 replies; 9+ messages in thread From: Simon Horman @ 2013-05-26 13:05 UTC (permalink / raw) To: linux-arm-kernel From: Magnus Damm <damm@opensource.se> Remove unused GIC CPU interface DT bits for r8a73a4. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm/boot/dts/r8a73a4.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index fde2a33..4ff2019 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -37,12 +37,6 @@ <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 0xf04>; - - gic-cpuif@4 { - compatible = "arm,gic-cpuif"; - cpuif-id = <4>; - cpu = <&cpu0>; - }; }; timer { -- 1.7.10.4 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-07-05 1:21 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-05-26 13:05 [PATCH 0/6] Renesas ARM based r8a73a0 SoC updates for v3.11 Simon Horman 2013-05-26 13:05 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add main clock Simon Horman 2013-07-04 20:38 ` [PATCH 1/6] ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it Guennadi Liakhovetski 2013-07-05 1:21 ` Magnus Damm 2013-05-26 13:05 ` [PATCH 2/6] ARM: shmobile: r8a73a4: add pll clocks Simon Horman 2013-05-26 13:05 ` [PATCH 3/6] ARM: shmobile: r8a73a4: add div4 clocks Simon Horman 2013-05-26 13:05 ` [PATCH 4/6] ARM: shmobile: r8a73a4: add div6 clocks Simon Horman 2013-05-26 13:05 ` [PATCH 5/6] ARM: shmobile: r8a73a4: Remove init_irq declaration in machine description Simon Horman 2013-05-26 13:05 ` [PATCH 6/6] ARM: shmobile: Remove unused r8a73a4 GIC CPU interface DT bits Simon Horman
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