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[202.79.124.123]) by smtp.gmail.com with ESMTPSA id e12-20020a17090ab38c00b002776350b50dsm10254760pjr.29.2023.10.25.04.33.09 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Oct 2023 04:33:11 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 13.4 \(3608.120.23.2.7\)) Subject: Re: [RFC PATCH v3 25/35] Documentation/devicetree/bindings/sh/cpus.yaml: Add SH CPU. From: "D. Jeff Dionne" In-Reply-To: <87ttqf6jjq.wl-ysato@users.sourceforge.jp> Date: Wed, 25 Oct 2023 20:33:07 +0900 Cc: Geert Uytterhoeven , linux-sh@vger.kernel.org, glaubitz@physik.fu-berlin.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <46ef748dd27127ef9b39fa6c97fe51e8d3422a4f.1697199949.git.ysato@users.sourceforge.jp> <87ttqf6jjq.wl-ysato@users.sourceforge.jp> To: Yoshinori Sato X-Mailer: Apple Mail (2.3608.120.23.2.7) Precedence: bulk List-ID: X-Mailing-List: linux-sh@vger.kernel.org Hi Sato-san, We must not imply that Renesas is responsible for J2, or that it is a = sanctioned SH core. J-Core has the responsibility for maintenance of those SH ISA compatible = cores. J. > On Oct 25, 2023, at 20:14, Yoshinori Sato = wrote: >=20 > On Wed, 18 Oct 2023 23:27:43 +0900, > Geert Uytterhoeven wrote: >>=20 >> Hi Sato-san, >>=20 >> On Sat, Oct 14, 2023 at 4:54=E2=80=AFPM Yoshinori Sato >> wrote: >>> Renesas SuperH binding definition. >>>=20 >>> Signed-off-by: Yoshinori Sato >>=20 >> Thanks for your patch! >>=20 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/sh/cpus.yaml >>> @@ -0,0 +1,45 @@ >>> +# SPDX-License-Identifier: GPL-2.0 >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/sh/cpus.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Renesas SuperH CPUs >>> + >>> +maintainers: >>> + - Yoshinori Sato >>> + >>> +description: |+ >>> + The device tree allows to describe the layout of CPUs in a system = through >>> + the "cpus" node, which in turn contains a number of subnodes (ie = "cpu") >>> + defining properties for every cpu. >>> + >>> + Bindings for CPU nodes follow the Devicetree Specification, = available from: >>> + >>> + https://www.devicetree.org/specifications/ >>> + >>> +properties: >>> + compatible: >>> + items: >>> + - enum: >>=20 >> Missing >>=20 >> - jcore,j2 >>=20 >>> + - renesas,sh4 >>=20 >>=20 >>> + - const: renesas,sh >>=20 >> I see arch/sh/boot/dts/j2_mimas_v2.dts lacks the fallback to >> "renesas,sh", though. >> Is there a common base of instructions that are available on all SH = cores? >=20 > The base instruction set is sh2. > Before that, there is sh1, but this is not compatible with Linux. > I think it would be a good idea to change this to "renesas,sh2", > but the SH7619 (SH2 CPU) would look like the following. > cpus { > cpu: cpu@0 { > compatible =3D "renesas,sh2", "renesas,sh2"; > }; > }; >=20 >> Missing reg property. >> Missing "device_type: true". >>=20 >>> + >>> + clock-frequency: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + description: | >>> + CPU core clock freqency. >>=20 >> Perhaps a "clocks" property instead, or as an alternative? >>=20 >> On sh7750, you do have >>=20 >> clocks =3D <&cpg SH7750_CPG_ICK>; >>=20 >>> + >>> +required: >>> + - compatible >>> + >>> +additionalProperties: true >>> + >>> +examples: >>> + - | >>> + cpus { >>=20 >> make dt_binding_check >> DT_SCHEMA_FILES=3DDocumentation/devicetree/bindings/sh/cpus.yaml: >>=20 >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: >> '#address-cells' is a required property >> from schema $id: http://devicetree.org/schemas/cpus.yaml# >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: >> '#size-cells' is a required property >> from schema $id: http://devicetree.org/schemas/cpus.yaml# >>=20 >>> + cpu: cpu@0 { >>> + compatible =3D "renesas,sh4", "renesas,sh"; >>=20 >> Documentation/devicetree/bindings/sh/cpus.example.dts:19.28-21.19: >> Warning (unit_address_vs_reg): /example-0/cpus/cpu@0: node has a unit >> name, but no reg or ranges property >> Documentation/devicetree/bindings/sh/cpus.example.dtb: cpus: cpu@0: >> 'cache-level' is a required property >> from schema $id: http://devicetree.org/schemas/cpus.yaml# >>=20 >>> + }; >>> + }; >>> +... >>=20 >> Gr{oetje,eeting}s, >>=20 >> Geert >>=20 >> --=20 >> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- = geert@linux-m68k.org >>=20 >> In personal conversations with technical people, I call myself a = hacker. But >> when I'm talking to journalists I just say "programmer" or something = like that. >> -- Linus Torvalds >=20 > --=20 > Yosinori Sato