[PATCH v2 0/8] SH pinctrl DT support

[PATCH v2 0/8] SH pinctrl DT support

[Laurent Pinchart]

Hello,

Here's the second version of the SuperH and SH Mobile pin controllers (PFC) DT
support patch set. The patches are based on the second version of my previous
PFC pinctrl and pinmux patch series ("[PATCH v2 00/29] SH pinctrl and pinmux
implementation") and are available from my git tree at

        git://linuxtv.org/pinchartl/fbdev.git pinmux-dt

The series is pretty self-explanatory. DT bindings are added in patch 1/9, and
the following patches move board code over to the device tree.

I've dropped pinctrl mappings move to DT, as pinctrl hogging in DT didn't work
with the new pinctrl device core code. The mappings will move to DT when DT
support will be implemented in the LCDC driver.

I'm still a bit unsure about the DT bindings. The platforms that implement
pinctrl DT bindings use a wide variety of architectures. I haven't found clear
guidelines regarding how those bindings should be implemented
(Documentation/devicetree/pinctrl just states that bindings are
driver-specific). Comments will be appreciated.

Changes since v1:

- Fixed gpio cell number 2 documentation
- Added missing gpio-controller and #gpio-cells properties to r8a7740 DT
- Split kzm9g DT patch into SoC and board patches
- Dropped pinctrl mappings move to DT

Laurent Pinchart (7):
  sh-pfc: Add OF support
  ARM: shmobile: r8a7740: Add pin control device in device tree
  ARM: shmobile: armadillo: Populate platform devices from device tree
  ARM: shmobile: Include sh73a0 DTSI in kzm9g
  ARM: shmobile: sh73a0: Add pin control device in device tree
  ARM: shmobile: kzm9g: Populate platform devices from device tree
  ARM: shmobile: kzm9g: Add LED1-LED4 to the device tree

Nobuhiro Iwamatsu (1):
  ARM: shmobile: Include DTSI of r8a7740 to armadillo800eva

 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       |   77 ++++++++++++++++++++
 arch/arm/boot/dts/r8a7740-armadillo800eva.dts      |    2 +-
 arch/arm/boot/dts/r8a7740.dtsi                     |    8 ++
 arch/arm/boot/dts/sh73a0-kzm9g.dts                 |   18 +++++-
 arch/arm/boot/dts/sh73a0.dtsi                      |   32 ++++++++
 arch/arm/mach-shmobile/board-armadillo800eva.c     |   10 ++-
 arch/arm/mach-shmobile/board-kzm9g.c               |    7 +-
 drivers/pinctrl/sh-pfc/core.c                      |   62 +++++++++++++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   |   54 ++++++++++++++
 9 files changed, 259 insertions(+), 11 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/sh73a0.dtsi

-- 
Regards,

Laurent Pinchart

[PATCH v2 1/8] sh-pfc: Add OF support

[Laurent Pinchart]

Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.

Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: devicetree-discuss@lists.ozlabs.org
---
 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       |   77 ++++++++++++++++++++
 drivers/pinctrl/sh-pfc/core.c                      |   62 +++++++++++++++-
 drivers/pinctrl/sh-pfc/pinctrl.c                   |   54 ++++++++++++++
 3 files changed, 191 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt

(Comment from the cover letter repeated here)

I'm still a bit unsure about the DT bindings. The platforms that implement
pinctrl DT bindings use a wide variety of architectures. I haven't found clear
guidelines regarding how those bindings should be implemented
(Documentation/devicetree/pinctrl just states that bindings are
driver-specific). Comments will be appreciated.

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 0000000..77752c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,77 @@
+* Renesas GPIO and Pin Mux/Config controller
+
+Required Properties:
+- compatible: should be one of the following.
+  - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+  - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+  - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
+  - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+
+- reg: Base address and length of each memory resource used by the pin
+  controller hardware module.
+
+- gpio-controller: Marks the device node as a gpio controller.
+
+- #gpio-cells: Should be 2. The first cell is the pin number and the second cell
+  is used to specify optional parameters as bit flags. Only the GPIO active low
+  flag (bit 0) is currently supported.
+
+
+The PFC node also acts as a container for pin control maps represented as
+subnodes. Each subnode contains a function name and one or more pin or pin group
+name. The subnode names are ignored, all subnodes are parsed through phandles
+and processed purely based on their content.
+
+Required Subnode Properties:
+- renesas,pins : An array of strings. Each string contains the name of a pin or
+  pin group.
+- renesas,function: A string containing the name of the function to mux to the
+  pin or pin group.
+
+  Valid values for group and function names can be found in the group and
+  function arrays of the PFC data file corresponding to the SoC
+  (drivers/pinctrl/spear/pfc-*.c)
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+
+The syntax of the gpio specifier used by client nodes should be the following
+with values derived from the SoC user manual.
+
+  <[phandle of the gpio controller node]
+   [pin number within the gpio controller]
+   [flags and pull up/down]>
+
+
+Example 1: SH73A0 (SH-Mobile AG5) pin controller node
+
+	gpio: pfc@e6050000 {
+		compatible = "renesas,pfc-sh73a0";
+		reg = <0xe6050000 0x8000>,
+		      <0xe605801c 0x1c>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+Example 2: A GPIO LED node that references a GPIO
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&gpio 20 1>; /* Active low */
+		};
+	};
+
+Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state and pin control maps
+           for the LCD device
+
+	&gpio {
+		pinctrl-0 = <&lcd_pins>;
+		pinctrl-names = "default";
+
+		lcd_pins: pfc_lcd_pins {
+			renesas,pins = "lcd_data24", "lcd_sync";
+			renesas,function = "lcd";
+		};
+	};
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 912b579..d0e8e77 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -19,6 +19,7 @@
 #include <linux/ioport.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
@@ -510,8 +511,55 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 	return sh_pfc_config_mux(pfc, mark, pinmux_type, cfg_mode);
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id sh_pfc_of_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A7740
+	{
+		.compatible = "renesas,pfc-r8a7740",
+		.data = &r8a7740_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7779
+	{
+		.compatible = "renesas,pfc-r8a7779",
+		.data = &r8a7779_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7367
+	{
+		.compatible = "renesas,pfc-sh7367",
+		.data = &sh7367_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7372
+	{
+		.compatible = "renesas,pfc-sh7372",
+		.data = &sh7372_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH7377
+	{
+		.compatible = "renesas,pfc-sh7377",
+		.data = &sh7377_pinmux_info,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_PFC_SH73A0
+	{
+		.compatible = "renesas,pfc-sh73a0",
+		.data = &sh73a0_pinmux_info,
+	},
+#endif
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
+#endif
+
 static int sh_pfc_probe(struct platform_device *pdev)
 {
+	const struct platform_device_id *platid = platform_get_device_id(pdev);
+#ifdef CONFIG_OF
+	struct device_node *np = pdev->dev.of_node;
+#endif
 	struct sh_pfc_soc_info *info;
 	struct sh_pfc *pfc;
 	int ret;
@@ -521,8 +569,15 @@ static int sh_pfc_probe(struct platform_device *pdev)
 	 */
 	BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 
-	info = pdev->id_entry->driver_data
-	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
+	if (platid)
+		info = (void *)platid->driver_data;
+#ifdef CONFIG_OF
+	else if (np)
+		info = (void *)of_match_device(sh_pfc_of_table, &pdev->dev)->data;
+#endif
+	else
+		info = pdev->dev.platform_data;
+
 	if (info = NULL)
 		return -ENODEV;
 
@@ -646,6 +701,9 @@ static struct platform_driver sh_pfc_driver = {
 	.driver		= {
 		.name	= DRV_NAME,
 		.owner	= THIS_MODULE,
+#ifdef CONFIG_OF
+		.of_match_table = sh_pfc_of_table,
+#endif
 	},
 };
 
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 6ee4105..78b78d2 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -15,7 +15,9 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/pinctrl/pinctrl.h>
@@ -65,11 +67,63 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 	seq_printf(s, "%s", DRV_NAME);
 }
 
+static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
+				 struct device_node *np,
+				 struct pinctrl_map **map, unsigned *num_maps)
+{
+	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+	struct pinctrl_map *maps;
+	struct property *prop;
+	unsigned int index = 0;
+	const char *function;
+	const char *group;
+	int ret;
+
+	ret = of_property_read_string(np, "renesas,function", &function);
+	if (ret < 0) {
+		dev_err(pmx->pfc->dev, "No function provided in DT\n");
+		return ret;
+	}
+
+	ret = of_property_count_strings(np, "renesas,pins");
+	if (ret < 0)
+		return ret;
+
+	if (!ret) {
+		dev_err(pmx->pfc->dev, "No pin(group) provided in DT node\n");
+		return -ENODEV;
+	}
+
+	maps = kzalloc(sizeof(*maps) * ret, GFP_KERNEL);
+	if (maps = NULL)
+		return -ENOMEM;
+
+	of_property_for_each_string(np, "renesas,pins", prop, group) {
+		maps[index].type = PIN_MAP_TYPE_MUX_GROUP;
+		maps[index].data.mux.group = group;
+		maps[index].data.mux.function = function;
+		index++;
+	}
+
+	*map = maps;
+	*num_maps = index;
+
+	return 0;
+}
+
+static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
+			       struct pinctrl_map *map, unsigned num_maps)
+{
+	kfree(map);
+}
+
 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 	.get_groups_count	= sh_pfc_get_groups_count,
 	.get_group_name		= sh_pfc_get_group_name,
 	.get_group_pins		= sh_pfc_get_group_pins,
 	.pin_dbg_show		= sh_pfc_pin_dbg_show,
+	.dt_node_to_map		= sh_pfc_dt_node_to_map,
+	.dt_free_map		= sh_pfc_dt_free_map,
 };
 
 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
-- 
1.7.8.6

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Guennadi Liakhovetski]

Hi Laurent

On Wed, 9 Jan 2013, Laurent Pinchart wrote:

> Support device instantiation through the device tree. The compatible
> property is used to select the SoC pinmux information.
> 
> Set the gpio_chip device field to the PFC device to enable automatic
> GPIO OF support.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Cc: devicetree-discuss@lists.ozlabs.org

This whole pinctrl mega-series is a very welcome improvement to the 
sh-/r-mobile GPIO framework, and is very well done IMHO! But, 
unfortunately, as discussed with you privately yesterday, there is still a 
problem with pinctrl DT support on sh73a0, which will, probably, enforce 
an update to one or several of patches from this lot. To explain to other 
readers, on sh73a0 pin numbers are not contiguous, they are sparse. 
When pins are referred to from C code, macro names are used, which are 
then correctly decoded to respective positions in pin descriptor tables. 
Whereas with DT, pins are referred to from .dts files using their physical 
numbers, which then refer to either wrong or missing entries in those 
tables.

I do not know where this problem should be solved best - either in 
descriptor tables, or in DT handling code, so, I don't know which patches 
would be affected. Don't think you'll want to keep the one-to-one 
index-to-pin mapping by also making pin-descriptor arrays sparse, so, so 
far I only see one possibility to fix this - by using the .enum_id field 
from struct sh_pfc_pin instead of just the index - both in  C and in DT 
case, and those .enum_id values will have to provide physical pin numbers 
instead of plane indices. That way you'd have to update at least 
drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the sh_pfc_map_gpios() function in 
drivers/pinctrl/sh-pfc/pinctrl.c.

Anyway, I'm sure you'll find a suitable solution of this problem and for 
now I'll let Simon decide which patches he wants to apply and which ones 
he'd prefer to hold back;-)

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Simon Horman]

On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> Hi Laurent
> 
> On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> 
> > Support device instantiation through the device tree. The compatible
> > property is used to select the SoC pinmux information.
> > 
> > Set the gpio_chip device field to the PFC device to enable automatic
> > GPIO OF support.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree-discuss@lists.ozlabs.org
> 
> This whole pinctrl mega-series is a very welcome improvement to the 
> sh-/r-mobile GPIO framework, and is very well done IMHO! But, 
> unfortunately, as discussed with you privately yesterday, there is still a 
> problem with pinctrl DT support on sh73a0, which will, probably, enforce 
> an update to one or several of patches from this lot. To explain to other 
> readers, on sh73a0 pin numbers are not contiguous, they are sparse. 
> When pins are referred to from C code, macro names are used, which are 
> then correctly decoded to respective positions in pin descriptor tables. 
> Whereas with DT, pins are referred to from .dts files using their physical 
> numbers, which then refer to either wrong or missing entries in those 
> tables.
> 
> I do not know where this problem should be solved best - either in 
> descriptor tables, or in DT handling code, so, I don't know which patches 
> would be affected. Don't think you'll want to keep the one-to-one 
> index-to-pin mapping by also making pin-descriptor arrays sparse, so, so 
> far I only see one possibility to fix this - by using the .enum_id field 
> from struct sh_pfc_pin instead of just the index - both in  C and in DT 
> case, and those .enum_id values will have to provide physical pin numbers 
> instead of plane indices. That way you'd have to update at least 
> drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the sh_pfc_map_gpios() function in 
> drivers/pinctrl/sh-pfc/pinctrl.c.
> 
> Anyway, I'm sure you'll find a suitable solution of this problem and for 
> now I'll let Simon decide which patches he wants to apply and which ones 
> he'd prefer to hold back;-)

Actually, I'd appreciate some guidance from Laurent on this.
It seems that the problems you raise go quite far back into the mega-series.

I was intending to send pull requests for the following branches soon.
But I am now concerned that at least the sh73a0 patches may need reworking.

pfc2: (based on a merge of sh-soc2 and pfc)
sh-pfc: Add shx3 pinmux support
sh-pfc: Add sh7786 pinmux support
sh-pfc: Add sh7785 pinmux support
sh-pfc: Add sh7757 pinmux support
sh-pfc: Add sh7734 pinmux support
sh-pfc: Add sh7724 pinmux support
sh-pfc: Add sh7723 pinmux support
sh-pfc: Add sh7722 pinmux support
sh-pfc: Add sh7720 pinmux support
sh-pfc: Add sh7269 pinmux support
sh-pfc: Add sh7264 pinmux support
sh-pfc: Add sh7203 pinmux support
sh-pfc: Add sh73a0 pinmux support
sh-pfc: Add sh7372 pinmux support
sh-pfc: Add r8a7779 pinmux support
sh-pfc: Add r8a7740 pinmux support
sh-pfc: Support pinmux info in driver data instead of platform data
sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
sh-pfc: Remove unused resource and num_resources platform data fields
sh-pfc: Remove platform device registration

sh-soc2: (based on pfc)
sh: shx3: Register PFC platform device
sh: sh7786: Register PFC platform device
sh: sh7785: Register PFC platform device
sh: sh7757: Register PFC platform device
sh: sh7734: Register PFC platform device
sh: sh7724: Register PFC platform device
sh: sh7723: Register PFC platform device
sh: sh7722: Register PFC platform device
sh: sh7720: Register PFC platform device
sh: sh7269: Register PFC platform device
sh: sh7264: Register PFC platform device
sh: sh7203: Register PFC platform device
sh: Add PFC platform device registration helper function


soc: (based on sh-soc)
ARM: shmobile: sh73a0: Add pin control resources
ARM: shmobile: sh7372: Add pin control resources
ARM: shmobile: r8a7740: Add pin control resources
ARM: shmobile: sh73a0: Register PFC platform device
ARM: shmobile: sh7372: Register PFC platform device
ARM: shmobile: r8a7779: Register PFC platform device
ARM: shmobile: r8a7740: Register PFC platform device
ARM: shmobile: Select PINCTRL
ARM: shmobile: add function declarations for sh7372 DT helper functions
ARM: sh7372: fix cache clean / invalidate order
ARM: sh7372: add clock lookup entries for DT-based devices
ARM: mach-shmobile: sh73a0 external IRQ wake update
ARM: shmobile: sh73a0: fixup div4_clks bitmap
ARM: shmobile: r8a7740: add TMU timer support
ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c

pfc: (based on sh-soc)
sh-pfc: Support passing resources through platform device
sh-pfc: Split platform device and platform driver registration
sh-pfc: Use sh_pfc_ namespace prefix through the whole driver
sh-pfc: Sort headers alphabetically
sh-pfc: Remove check for impossible error condition
sh-pfc: Let the compiler decide whether to inline functions
sh-pfc: Use devm_ioremap_nocache()
sh-pfc: Use devm_kzalloc()
sh-pfc: Move platform device and driver to the core
sh-pfc: Merge PFC core and gpio
sh-pfc: Merge PFC core and pinctrl
sh-pfc: Move private definitions and declarations to private header
sh-pfc: Split platform data from the sh_pfc structure
sh-pfc: Remove all use of __devinit/__devexit

sh-soc:
sh: shx3: Fix last GPIO index
sh: sh7786: Fix last GPIO index
sh: sh7786: Fix port E, G and J GPIOs
sh: sh7757: Fix GPIO_FN_ET0_MDIO and GPIO_FN_ET1_MDIO GPIO entries
sh: sh7723: Rename GPIO_FN_SIUOSPD to GPIO_FN_SIUAOSPD
sh: sh7269: Rename CRX0CRX1(CRX2) marks to match GPIO names
sh: sh7264: Rename CRX0CRX1 mark to match GPIO names

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Simon Horman]

On Tue, Jan 15, 2013 at 10:10:19AM +0900, Simon Horman wrote:
> On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> > Hi Laurent
> > 
> > On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > 
> > > Support device instantiation through the device tree. The compatible
> > > property is used to select the SoC pinmux information.
> > > 
> > > Set the gpio_chip device field to the PFC device to enable automatic
> > > GPIO OF support.
> > > 
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > > Cc: devicetree-discuss@lists.ozlabs.org
> > 
> > This whole pinctrl mega-series is a very welcome improvement to the 
> > sh-/r-mobile GPIO framework, and is very well done IMHO! But, 
> > unfortunately, as discussed with you privately yesterday, there is still a 
> > problem with pinctrl DT support on sh73a0, which will, probably, enforce 
> > an update to one or several of patches from this lot. To explain to other 
> > readers, on sh73a0 pin numbers are not contiguous, they are sparse. 
> > When pins are referred to from C code, macro names are used, which are 
> > then correctly decoded to respective positions in pin descriptor tables. 
> > Whereas with DT, pins are referred to from .dts files using their physical 
> > numbers, which then refer to either wrong or missing entries in those 
> > tables.
> > 
> > I do not know where this problem should be solved best - either in 
> > descriptor tables, or in DT handling code, so, I don't know which patches 
> > would be affected. Don't think you'll want to keep the one-to-one 
> > index-to-pin mapping by also making pin-descriptor arrays sparse, so, so 
> > far I only see one possibility to fix this - by using the .enum_id field 
> > from struct sh_pfc_pin instead of just the index - both in  C and in DT 
> > case, and those .enum_id values will have to provide physical pin numbers 
> > instead of plane indices. That way you'd have to update at least 
> > drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the sh_pfc_map_gpios() function in 
> > drivers/pinctrl/sh-pfc/pinctrl.c.
> > 
> > Anyway, I'm sure you'll find a suitable solution of this problem and for 
> > now I'll let Simon decide which patches he wants to apply and which ones 
> > he'd prefer to hold back;-)
> 
> Actually, I'd appreciate some guidance from Laurent on this.
> It seems that the problems you raise go quite far back into the mega-series.
> 
> I was intending to send pull requests for the following branches soon.
> But I am now concerned that at least the sh73a0 patches may need reworking.

I have concluded that the changes below are safe and have
proceeded with sending them to arm-soc. However, I am still awaiting
a response from arm-soc.

> pfc2: (based on a merge of sh-soc2 and pfc)
> sh-pfc: Add shx3 pinmux support
> sh-pfc: Add sh7786 pinmux support
> sh-pfc: Add sh7785 pinmux support
> sh-pfc: Add sh7757 pinmux support
> sh-pfc: Add sh7734 pinmux support
> sh-pfc: Add sh7724 pinmux support
> sh-pfc: Add sh7723 pinmux support
> sh-pfc: Add sh7722 pinmux support
> sh-pfc: Add sh7720 pinmux support
> sh-pfc: Add sh7269 pinmux support
> sh-pfc: Add sh7264 pinmux support
> sh-pfc: Add sh7203 pinmux support
> sh-pfc: Add sh73a0 pinmux support
> sh-pfc: Add sh7372 pinmux support
> sh-pfc: Add r8a7779 pinmux support
> sh-pfc: Add r8a7740 pinmux support
> sh-pfc: Support pinmux info in driver data instead of platform data
> sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
> sh-pfc: Remove unused resource and num_resources platform data fields
> sh-pfc: Remove platform device registration
> 
> sh-soc2: (based on pfc)
> sh: shx3: Register PFC platform device
> sh: sh7786: Register PFC platform device
> sh: sh7785: Register PFC platform device
> sh: sh7757: Register PFC platform device
> sh: sh7734: Register PFC platform device
> sh: sh7724: Register PFC platform device
> sh: sh7723: Register PFC platform device
> sh: sh7722: Register PFC platform device
> sh: sh7720: Register PFC platform device
> sh: sh7269: Register PFC platform device
> sh: sh7264: Register PFC platform device
> sh: sh7203: Register PFC platform device
> sh: Add PFC platform device registration helper function
> 
> 
> soc: (based on sh-soc)
> ARM: shmobile: sh73a0: Add pin control resources
> ARM: shmobile: sh7372: Add pin control resources
> ARM: shmobile: r8a7740: Add pin control resources
> ARM: shmobile: sh73a0: Register PFC platform device
> ARM: shmobile: sh7372: Register PFC platform device
> ARM: shmobile: r8a7779: Register PFC platform device
> ARM: shmobile: r8a7740: Register PFC platform device
> ARM: shmobile: Select PINCTRL
> ARM: shmobile: add function declarations for sh7372 DT helper functions
> ARM: sh7372: fix cache clean / invalidate order
> ARM: sh7372: add clock lookup entries for DT-based devices
> ARM: mach-shmobile: sh73a0 external IRQ wake update
> ARM: shmobile: sh73a0: fixup div4_clks bitmap
> ARM: shmobile: r8a7740: add TMU timer support
> ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in setup-r8a7740.c
> 
> pfc: (based on sh-soc)
> sh-pfc: Support passing resources through platform device
> sh-pfc: Split platform device and platform driver registration
> sh-pfc: Use sh_pfc_ namespace prefix through the whole driver
> sh-pfc: Sort headers alphabetically
> sh-pfc: Remove check for impossible error condition
> sh-pfc: Let the compiler decide whether to inline functions
> sh-pfc: Use devm_ioremap_nocache()
> sh-pfc: Use devm_kzalloc()
> sh-pfc: Move platform device and driver to the core
> sh-pfc: Merge PFC core and gpio
> sh-pfc: Merge PFC core and pinctrl
> sh-pfc: Move private definitions and declarations to private header
> sh-pfc: Split platform data from the sh_pfc structure
> sh-pfc: Remove all use of __devinit/__devexit
> 
> sh-soc:
> sh: shx3: Fix last GPIO index
> sh: sh7786: Fix last GPIO index
> sh: sh7786: Fix port E, G and J GPIOs
> sh: sh7757: Fix GPIO_FN_ET0_MDIO and GPIO_FN_ET1_MDIO GPIO entries
> sh: sh7723: Rename GPIO_FN_SIUOSPD to GPIO_FN_SIUAOSPD
> sh: sh7269: Rename CRX0CRX1(CRX2) marks to match GPIO names
> sh: sh7264: Rename CRX0CRX1 mark to match GPIO names
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
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> 

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Laurent Pinchart]

Hi Simon,

On Monday 21 January 2013 09:38:28 Simon Horman wrote:
> On Tue, Jan 15, 2013 at 10:10:19AM +0900, Simon Horman wrote:
> > On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> > > On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > > > Support device instantiation through the device tree. The compatible
> > > > property is used to select the SoC pinmux information.
> > > > 
> > > > Set the gpio_chip device field to the PFC device to enable automatic
> > > > GPIO OF support.
> > > > 
> > > > Signed-off-by: Laurent Pinchart
> > > > <laurent.pinchart+renesas@ideasonboard.com>
> > > > Cc: devicetree-discuss@lists.ozlabs.org
> > > 
> > > This whole pinctrl mega-series is a very welcome improvement to the
> > > sh-/r-mobile GPIO framework, and is very well done IMHO! But,
> > > unfortunately, as discussed with you privately yesterday, there is still
> > > a problem with pinctrl DT support on sh73a0, which will, probably,
> > > enforce an update to one or several of patches from this lot. To explain
> > > to other readers, on sh73a0 pin numbers are not contiguous, they are
> > > sparse. When pins are referred to from C code, macro names are used,
> > > which are then correctly decoded to respective positions in pin
> > > descriptor tables. Whereas with DT, pins are referred to from .dts files
> > > using their physical numbers, which then refer to either wrong or
> > > missing entries in those tables.
> > > 
> > > I do not know where this problem should be solved best - either in
> > > descriptor tables, or in DT handling code, so, I don't know which
> > > patches would be affected. Don't think you'll want to keep the one-to-
> > > one index-to-pin mapping by also making pin-descriptor arrays sparse,
> > > so, so far I only see one possibility to fix this - by using the
> > > .enum_id field from struct sh_pfc_pin instead of just the index - both
> > > in  C and in DT case, and those .enum_id values will have to provide
> > > physical pin numbers instead of plane indices. That way you'd have to
> > > update at least drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the
> > > sh_pfc_map_gpios() function in drivers/pinctrl/sh-pfc/pinctrl.c.
> > > 
> > > Anyway, I'm sure you'll find a suitable solution of this problem and for
> > > now I'll let Simon decide which patches he wants to apply and which ones
> > > he'd prefer to hold back;-)
> > 
> > Actually, I'd appreciate some guidance from Laurent on this.
> > It seems that the problems you raise go quite far back into the
> > mega-series.
> > 
> > I was intending to send pull requests for the following branches soon.
> > But I am now concerned that at least the sh73a0 patches may need
> > reworking.
> 
> I have concluded that the changes below are safe and have
> proceeded with sending them to arm-soc. However, I am still awaiting
> a response from arm-soc.

Sorry for the late reply. The below changes are indeed safe, what I need to 
rework are the pinctrl API and DT series.

> > pfc2: (based on a merge of sh-soc2 and pfc)
> > sh-pfc: Add shx3 pinmux support
> > sh-pfc: Add sh7786 pinmux support
> > sh-pfc: Add sh7785 pinmux support
> > sh-pfc: Add sh7757 pinmux support
> > sh-pfc: Add sh7734 pinmux support
> > sh-pfc: Add sh7724 pinmux support
> > sh-pfc: Add sh7723 pinmux support
> > sh-pfc: Add sh7722 pinmux support
> > sh-pfc: Add sh7720 pinmux support
> > sh-pfc: Add sh7269 pinmux support
> > sh-pfc: Add sh7264 pinmux support
> > sh-pfc: Add sh7203 pinmux support
> > sh-pfc: Add sh73a0 pinmux support
> > sh-pfc: Add sh7372 pinmux support
> > sh-pfc: Add r8a7779 pinmux support
> > sh-pfc: Add r8a7740 pinmux support
> > sh-pfc: Support pinmux info in driver data instead of platform data
> > sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
> > sh-pfc: Remove unused resource and num_resources platform data fields
> > sh-pfc: Remove platform device registration
> > 
> > sh-soc2: (based on pfc)
> > sh: shx3: Register PFC platform device
> > sh: sh7786: Register PFC platform device
> > sh: sh7785: Register PFC platform device
> > sh: sh7757: Register PFC platform device
> > sh: sh7734: Register PFC platform device
> > sh: sh7724: Register PFC platform device
> > sh: sh7723: Register PFC platform device
> > sh: sh7722: Register PFC platform device
> > sh: sh7720: Register PFC platform device
> > sh: sh7269: Register PFC platform device
> > sh: sh7264: Register PFC platform device
> > sh: sh7203: Register PFC platform device
> > sh: Add PFC platform device registration helper function
> > 
> > 
> > soc: (based on sh-soc)
> > ARM: shmobile: sh73a0: Add pin control resources
> > ARM: shmobile: sh7372: Add pin control resources
> > ARM: shmobile: r8a7740: Add pin control resources
> > ARM: shmobile: sh73a0: Register PFC platform device
> > ARM: shmobile: sh7372: Register PFC platform device
> > ARM: shmobile: r8a7779: Register PFC platform device
> > ARM: shmobile: r8a7740: Register PFC platform device
> > ARM: shmobile: Select PINCTRL
> > ARM: shmobile: add function declarations for sh7372 DT helper functions
> > ARM: sh7372: fix cache clean / invalidate order
> > ARM: sh7372: add clock lookup entries for DT-based devices
> > ARM: mach-shmobile: sh73a0 external IRQ wake update
> > ARM: shmobile: sh73a0: fixup div4_clks bitmap
> > ARM: shmobile: r8a7740: add TMU timer support
> > ARM: shmobile: Remove duplicate inclusion of dma-mapping.h in
> > setup-r8a7740.c
> > 
> > pfc: (based on sh-soc)
> > sh-pfc: Support passing resources through platform device
> > sh-pfc: Split platform device and platform driver registration
> > sh-pfc: Use sh_pfc_ namespace prefix through the whole driver
> > sh-pfc: Sort headers alphabetically
> > sh-pfc: Remove check for impossible error condition
> > sh-pfc: Let the compiler decide whether to inline functions
> > sh-pfc: Use devm_ioremap_nocache()
> > sh-pfc: Use devm_kzalloc()
> > sh-pfc: Move platform device and driver to the core
> > sh-pfc: Merge PFC core and gpio
> > sh-pfc: Merge PFC core and pinctrl
> > sh-pfc: Move private definitions and declarations to private header
> > sh-pfc: Split platform data from the sh_pfc structure
> > sh-pfc: Remove all use of __devinit/__devexit
> > 
> > sh-soc:
> > sh: shx3: Fix last GPIO index
> > sh: sh7786: Fix last GPIO index
> > sh: sh7786: Fix port E, G and J GPIOs
> > sh: sh7757: Fix GPIO_FN_ET0_MDIO and GPIO_FN_ET1_MDIO GPIO entries
> > sh: sh7723: Rename GPIO_FN_SIUOSPD to GPIO_FN_SIUAOSPD
> > sh: sh7269: Rename CRX0CRX1(CRX2) marks to match GPIO names
> > sh: sh7264: Rename CRX0CRX1 mark to match GPIO names

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Simon Horman]

On Thu, Jan 24, 2013 at 12:17:32PM +0100, Laurent Pinchart wrote:
> Hi Simon,
> 
> On Monday 21 January 2013 09:38:28 Simon Horman wrote:
> > On Tue, Jan 15, 2013 at 10:10:19AM +0900, Simon Horman wrote:
> > > On Sat, Jan 12, 2013 at 06:18:54PM +0100, Guennadi Liakhovetski wrote:
> > > > On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > > > > Support device instantiation through the device tree. The compatible
> > > > > property is used to select the SoC pinmux information.
> > > > > 
> > > > > Set the gpio_chip device field to the PFC device to enable automatic
> > > > > GPIO OF support.
> > > > > 
> > > > > Signed-off-by: Laurent Pinchart
> > > > > <laurent.pinchart+renesas@ideasonboard.com>
> > > > > Cc: devicetree-discuss@lists.ozlabs.org
> > > > 
> > > > This whole pinctrl mega-series is a very welcome improvement to the
> > > > sh-/r-mobile GPIO framework, and is very well done IMHO! But,
> > > > unfortunately, as discussed with you privately yesterday, there is still
> > > > a problem with pinctrl DT support on sh73a0, which will, probably,
> > > > enforce an update to one or several of patches from this lot. To explain
> > > > to other readers, on sh73a0 pin numbers are not contiguous, they are
> > > > sparse. When pins are referred to from C code, macro names are used,
> > > > which are then correctly decoded to respective positions in pin
> > > > descriptor tables. Whereas with DT, pins are referred to from .dts files
> > > > using their physical numbers, which then refer to either wrong or
> > > > missing entries in those tables.
> > > > 
> > > > I do not know where this problem should be solved best - either in
> > > > descriptor tables, or in DT handling code, so, I don't know which
> > > > patches would be affected. Don't think you'll want to keep the one-to-
> > > > one index-to-pin mapping by also making pin-descriptor arrays sparse,
> > > > so, so far I only see one possibility to fix this - by using the
> > > > .enum_id field from struct sh_pfc_pin instead of just the index - both
> > > > in  C and in DT case, and those .enum_id values will have to provide
> > > > physical pin numbers instead of plane indices. That way you'd have to
> > > > update at least drivers/pinctrl/sh-pfc/pfc-sh73a0.c and the
> > > > sh_pfc_map_gpios() function in drivers/pinctrl/sh-pfc/pinctrl.c.
> > > > 
> > > > Anyway, I'm sure you'll find a suitable solution of this problem and for
> > > > now I'll let Simon decide which patches he wants to apply and which ones
> > > > he'd prefer to hold back;-)
> > > 
> > > Actually, I'd appreciate some guidance from Laurent on this.
> > > It seems that the problems you raise go quite far back into the
> > > mega-series.
> > > 
> > > I was intending to send pull requests for the following branches soon.
> > > But I am now concerned that at least the sh73a0 patches may need
> > > reworking.
> > 
> > I have concluded that the changes below are safe and have
> > proceeded with sending them to arm-soc. However, I am still awaiting
> > a response from arm-soc.
> 
> Sorry for the late reply. The below changes are indeed safe, what I need to 
> rework are the pinctrl API and DT series.

Thanks. After some discussions with arm-soc I have finally sent a
pull-request for these changes which now live in the pfc branch of
my renesas tree.

Re: [PATCH v2 1/8] sh-pfc: Add OF support

[Laurent Pinchart]

Hi Guennadi,

On Saturday 12 January 2013 18:18:54 Guennadi Liakhovetski wrote:
> On Wed, 9 Jan 2013, Laurent Pinchart wrote:
> > Support device instantiation through the device tree. The compatible
> > property is used to select the SoC pinmux information.
> > 
> > Set the gpio_chip device field to the PFC device to enable automatic
> > GPIO OF support.
> > 
> > Signed-off-by: Laurent Pinchart
> > <laurent.pinchart+renesas@ideasonboard.com>
> > Cc: devicetree-discuss@lists.ozlabs.org
> 
> This whole pinctrl mega-series is a very welcome improvement to the
> sh-/r-mobile GPIO framework, and is very well done IMHO! But,
> unfortunately, as discussed with you privately yesterday, there is still a
> problem with pinctrl DT support on sh73a0, which will, probably, enforce
> an update to one or several of patches from this lot. To explain to other
> readers, on sh73a0 pin numbers are not contiguous, they are sparse.
> When pins are referred to from C code, macro names are used, which are
> then correctly decoded to respective positions in pin descriptor tables.
> Whereas with DT, pins are referred to from .dts files using their physical
> numbers, which then refer to either wrong or missing entries in those
> tables.
> 
> I do not know where this problem should be solved best - either in
> descriptor tables, or in DT handling code, so, I don't know which patches
> would be affected. Don't think you'll want to keep the one-to-one
> index-to-pin mapping by also making pin-descriptor arrays sparse, so, so
> far I only see one possibility to fix this - by using the .enum_id field
> from struct sh_pfc_pin instead of just the index - both in  C and in DT
> case, and those .enum_id values will have to provide physical pin numbers
> instead of plane indices.

I was thinking about something similar as well. I will use physical pin 
numbers, but I then need to find a way to number the pins, as they're not 
numbered in the documentation. Opinions on possible numbering schemes from 
anyone familiar with several SoCs both in SH Mobile and SuperH will be 
appreciated.

> That way you'd have to update at least drivers/pinctrl/sh-pfc/pfc-sh73a0.c
> and the sh_pfc_map_gpios() function in drivers/pinctrl/sh-pfc/pinctrl.c.
> 
> Anyway, I'm sure you'll find a suitable solution of this problem and for
> now I'll let Simon decide which patches he wants to apply and which ones
> he'd prefer to hold back;-)

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 0/8] SH pinctrl DT support

[Simon Horman]

On Wed, Jan 09, 2013 at 02:03:07AM +0100, Laurent Pinchart wrote:
> Hello,
> 
> Here's the second version of the SuperH and SH Mobile pin controllers (PFC) DT
> support patch set. The patches are based on the second version of my previous
> PFC pinctrl and pinmux patch series ("[PATCH v2 00/29] SH pinctrl and pinmux
> implementation") and are available from my git tree at
> 
>         git://linuxtv.org/pinchartl/fbdev.git pinmux-dt
> 
> The series is pretty self-explanatory. DT bindings are added in patch 1/9, and
> the following patches move board code over to the device tree.

Thanks applied to the following branches:

patch 1: pfc3 branch
patch 2, 4, 5, 8, 8: boards branch
patch 3, 6: soc2 branch

Re: [PATCH v2 0/8] SH pinctrl DT support

[Simon Horman]

On Wed, Jan 09, 2013 at 02:03:07AM +0100, Laurent Pinchart wrote:
> Hello,
> 
> Here's the second version of the SuperH and SH Mobile pin controllers (PFC) DT
> support patch set. The patches are based on the second version of my previous
> PFC pinctrl and pinmux patch series ("[PATCH v2 00/29] SH pinctrl and pinmux
> implementation") and are available from my git tree at
> 
>         git://linuxtv.org/pinchartl/fbdev.git pinmux-dt

Hi Laurent,

I am experiencing some difficulty in booting the kzm9g board using the
branch above (HEAD commit id: f6f658f46274a06835c7ae562793a5144fac36ad)
with its defconfig plus CONFIG_ARM_APPENDED_DTB=y.

I see the following and I was wondering if you could take a look into this.
I'm quite prepared to believe that I have messed something up but at this
stage I'm entirely unsure what it might be.

...
sh_mobile_sdhi sh_mobile_sdhi.0: mmc0 base at 0xee100000 clock rate 69 MHz
Unable to handle kernel NULL pointer dereference at virtual address 0000002c
pgd = c0004000
[0000002c] *pgd\0000000
Internal error: Oops: 5 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0    Not tainted  (3.8.0-rc2+ #605)
PC is at __gpio_to_irq+0x18/0x3c
LR is at mmc_gpio_request_cd+0x20/0xb8
pc : [<c0194a48>]    lr : [<c02392e0>]    psr: 20000113
sp : de04bd78  ip : de04bd88  fp : de04bd84
r10: 00000000  r9 : 00000a00  r8 : c0443f00
r7 : c0443ef0  r6 : 0000000d  r5 : de279000  r4 : de279280
r3 : c04848f0  r2 : 0000000d  r1 : 0000000d  r0 : 00000000
Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5387d  Table: 4100404a  DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xde04a238)
Stack: (0xde04bd78 to 0xde04c000)
bd60:                                                       de04bdb4 de04bd88
bd80: c02392e0 c0194a3c de04bdb4 de04bd98 c01d5158 de279280 de279000 de27e9c4
bda0: c0443ef0 c0443f00 de04bdec de04bdb8 c023d42c c02392cc c0443ef0 de04bdfc
bdc0: c045fc20 de27e9c0 c0443ef0 c0444828 c045fc20 de27e9c4 0000006a c0443f00
bde0: de04be2c de04bdf0 c023e94c c023d0fc 00000000 c045fc20 c040a270 00000000
be00: de04be1c c0443f00 c0443f34 00000000 c045fc20 c040a270 0000006a 00000000
be20: de04be3c de04be30 c01d10f0 c023e7cc de04be5c de04be40 c01cfd44 c01d10dc
be40: c0443f00 c0443f34 c045fc20 00000000 de04be7c de04be60 c01cfee0 c01cfc8c
be60: c045fc20 de04be80 c01cfe78 00000000 de04bea4 de04be80 c01ce5e8 c01cfe84
be80: de05b718 de13cb74 c045fc20 de27ecc0 c045a268 00000007 de04beb4 de04bea8
bea0: c01cfb68 c01ce5a0 de04bedc de04beb8 c01cedfc c01cfb54 c03bdec0 de04bec8
bec0: c045fc20 c041e44c c0465f00 00000007 de04befc de04bee0 c01d0528 c01ced60
bee0: c042737c c041e44c c0465f00 00000007 de04bf0c de04bf00 c01d13e0 c01d048c
bf00: de04bf1c de04bf10 c041e460 c01d13a0 de04bf6c de04bf20 c0009414 c041e458
bf20: c003c5f0 c040a27c 00000006 00000006 0000006a c0407160 60000113 c0a67164
bf40: de04bf6c c042737c c042ff4c c0465f00 00000007 c040a270 0000006a c0427384
bf60: de04bfac de04bf70 c031e428 c0009370 00000006 00000006 c040a270 c031e330
bf80: 00000000 00000000 c031e330 00000000 00000000 00000000 00000000 00000000
bfa0: 00000000 de04bfb0 c000f058 c031e33c 00000000 00000000 00000000 00000000
bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 fb7fffff ffff77ff
Backtrace: 
[<c0194a30>] (__gpio_to_irq+0x0/0x3c) from [<c02392e0>] (mmc_gpio_request_cd+0x20/0xb8)
[<c02392c0>] (mmc_gpio_request_cd+0x0/0xb8) from [<c023d42c>] (tmio_mmc_host_probe+0x33c/0x3b0)
 r8:c0443f00 r7:c0443ef0 r6:de27e9c4 r5:de279000 r4:de279280
[<c023d0f0>] (tmio_mmc_host_probe+0x0/0x3b0) from [<c023e94c>] (sh_mobile_sdhi_probe+0x18c/0x420)
[<c023e7c0>] (sh_mobile_sdhi_probe+0x0/0x420) from [<c01d10f0>] (platform_drv_probe+0x20/0x24)
[<c01d10d0>] (platform_drv_probe+0x0/0x24) from [<c01cfd44>] (driver_probe_device+0xc4/0x1f8)
[<c01cfc80>] (driver_probe_device+0x0/0x1f8) from [<c01cfee0>] (__driver_attach+0x68/0x8c)
 r7:00000000 r6:c045fc20 r5:c0443f34 r4:c0443f00
[<c01cfe78>] (__driver_attach+0x0/0x8c) from [<c01ce5e8>] (bus_for_each_dev+0x54/0x94)
 r7:00000000 r6:c01cfe78 r5:de04be80 r4:c045fc20
[<c01ce594>] (bus_for_each_dev+0x0/0x94) from [<c01cfb68>] (driver_attach+0x20/0x28)
 r7:00000007 r6:c045a268 r5:de27ecc0 r4:c045fc20
[<c01cfb48>] (driver_attach+0x0/0x28) from [<c01cedfc>] (bus_add_driver+0xa8/0x218)
[<c01ced54>] (bus_add_driver+0x0/0x218) from [<c01d0528>] (driver_register+0xa8/0x140)
 r7:00000007 r6:c0465f00 r5:c041e44c r4:c045fc20
[<c01d0480>] (driver_register+0x0/0x140) from [<c01d13e0>] (platform_driver_register+0x4c/0x60)
 r7:00000007 r6:c0465f00 r5:c041e44c r4:c042737c
[<c01d1394>] (platform_driver_register+0x0/0x60) from [<c041e460>] (sh_mobile_sdhi_driver_init+0x14/0x1c)
[<c041e44c>] (sh_mobile_sdhi_driver_init+0x0/0x1c) from [<c0009414>] (do_one_initcall+0xb0/0x180)
[<c0009364>] (do_one_initcall+0x0/0x180) from [<c031e428>] (kernel_init+0xf8/0x29c)
[<c031e330>] (kernel_init+0x0/0x29c) from [<c000f058>] (ret_from_fork+0x14/0x3c)
Code: e24cb004 e59f3024 e1a02000 e7930180 (e590302c) 
---[ end trace 97935dbe35bb7737 ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

CPU1: stopping
Backtrace: 
[<c00129f4>] (dump_backtrace+0x0/0x110) from [<c03254f0>] (dump_stack+0x18/0x1c)
 r7:c043a458 r6:de085f60 r5:00000001 r4:00000000
[<c03254d8>] (dump_stack+0x0/0x1c) from [<c0013c9c>] (handle_IPI+0xe0/0x138)
[<c0013bbc>] (handle_IPI+0x0/0x138) from [<c0009330>] (gic_handle_irq+0x64/0x6c)
 r5:f0000110 r4:f000010c
[<c00092cc>] (gic_handle_irq+0x0/0x6c) from [<c000eb80>] (__irq_svc+0x40/0x70)
Exception stack(0xde085f60 to 0xde085fa8)
5f60: 00000020 c043aa08 00000001 00000000 de084000 c043d4a0 c0465fc8 c032b09c
5f80: 4100406a 412fc098 00000000 de085fb4 de085fb8 de085fa8 c000fbbc c000fbc0
5fa0: 60000113 ffffffff
 r7:de085f94 r6:ffffffff r5:60000113 r4:c000fbc0
[<c000fb94>] (default_idle+0x0/0x34) from [<c000ffb8>] (cpu_idle+0x90/0xdc)
[<c000ff28>] (cpu_idle+0x0/0xdc) from [<c032024c>] (secondary_start_kernel+0x114/0x138)
 r7:c0466298 r6:de084000 r5:00000001 r4:c0447b88
[<c0320138>] (secondary_start_kernel+0x0/0x138) from [<4131fa88>] (0x4131fa88)
 r7:c0466298 r6:10c0387d r5:00000015 r4:5f07006a