* [RFC PATCH 00/12] Device Tree support for SH7751 based board
@ 2023-08-30 8:42 Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 01/12] sh: Add OF target boards Yoshinori Sato
` (11 more replies)
0 siblings, 12 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
This is an updated version of something I wrote about 7 years ago.
Minimum support for R2D-plus and LANDISK.
I think R2D-1 will work if you add AX88796 to dts.
And board-specific functions and SCI's SPI functions are not supported.
Yoshinori Sato (12):
sh: Add OF target boards.
sh: Update OF handling.
sh: SH4 OF support.
clk: SH7750 / 7751 clk driver.
drivers/irqchip: Add SH7751 and boards specific irqchip.
drivers/pci: Add SH7751 PCI Host bridge driver.
clocksource: Update sh_tmu of handling.
mfd/sm501: Add OF properties.
of: FDT vaddr support for SH.
serial/sh-sci: Fix earlyprintk / earlycon.
sh: target dts.
sh: OF defconfig.
.../devicetree/bindings/display/sm501fb.txt | 11 +
arch/sh/Kconfig | 12 +-
arch/sh/boards/Kconfig | 28 ++
arch/sh/boards/of-generic.c | 28 +-
arch/sh/boot/compressed/head_32.S | 5 +-
arch/sh/boot/dts/include/dt-bindings | 1 +
arch/sh/boot/dts/landisk.dts | 142 +++++++
arch/sh/boot/dts/rts7751r2dplus.dts | 168 ++++++++
arch/sh/boot/dts/usl-5p.dts | 146 +++++++
arch/sh/configs/landisk-of_defconfig | 161 ++++++++
arch/sh/configs/rts7751r2dplus-of_defconfig | 159 ++++++++
arch/sh/drivers/Makefile | 2 +
arch/sh/include/asm/io.h | 10 +
arch/sh/include/asm/pci.h | 4 +
arch/sh/kernel/cpu/Makefile | 8 +-
arch/sh/kernel/cpu/clock.c | 3 +-
arch/sh/kernel/cpu/sh4/Makefile | 2 +
arch/sh/kernel/head_32.S | 2 +-
arch/sh/kernel/setup.c | 26 +-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/sh/Kconfig | 7 +
drivers/clk/sh/Makefile | 2 +
drivers/clk/sh/clk-sh7750.c | 193 +++++++++
drivers/clk/sh/clk-shdiv.c | 341 ++++++++++++++++
drivers/clocksource/sh_tmu.c | 33 +-
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-iodata-julian.c | 163 ++++++++
drivers/irqchip/irq-renesas-r2d.c | 175 ++++++++
drivers/irqchip/irq-renesas-sh7751.c | 186 +++++++++
drivers/mfd/sm501.c | 113 +++++-
drivers/of/fdt.c | 3 +
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pci-sh7751.c | 382 ++++++++++++++++++
drivers/pci/controller/pci-sh7751.h | 267 ++++++++++++
drivers/sh/Makefile | 2 +
drivers/tty/serial/sh-sci.c | 10 +-
39 files changed, 2779 insertions(+), 33 deletions(-)
create mode 120000 arch/sh/boot/dts/include/dt-bindings
create mode 100644 arch/sh/boot/dts/landisk.dts
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
create mode 100644 arch/sh/boot/dts/usl-5p.dts
create mode 100644 arch/sh/configs/landisk-of_defconfig
create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
create mode 100644 drivers/clk/sh/Kconfig
create mode 100644 drivers/clk/sh/Makefile
create mode 100644 drivers/clk/sh/clk-sh7750.c
create mode 100644 drivers/clk/sh/clk-shdiv.c
create mode 100644 drivers/irqchip/irq-iodata-julian.c
create mode 100644 drivers/irqchip/irq-renesas-r2d.c
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
create mode 100644 drivers/pci/controller/pci-sh7751.c
create mode 100644 drivers/pci/controller/pci-sh7751.h
--
2.39.2
^ permalink raw reply [flat|nested] 15+ messages in thread
* [RFC PATCH 01/12] sh: Add OF target boards.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 02/12] sh: Update OF handling Yoshinori Sato
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/Kconfig | 12 +++++++++---
arch/sh/boards/Kconfig | 28 ++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 2b3ce4fd3956..7a3e54bf0da9 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -64,10 +64,10 @@ config SUPERH
select MODULES_USE_ELF_RELA
select NEED_SG_DMA_LENGTH
select NO_DMA if !MMU && !DMA_COHERENT
- select NO_GENERIC_PCI_IOPORT_MAP if PCI
+ select NO_GENERIC_PCI_IOPORT_MAP if !SH_DEVICE_TREE
select OLD_SIGACTION
select OLD_SIGSUSPEND
- select PCI_DOMAINS if PCI
+ select PCI_DOMAINS if PCI && !SH_DEVICE_TREE
select PERF_EVENTS
select PERF_USE_VMALLOC
select RTC_LIB
@@ -363,14 +363,17 @@ config CPU_SUBTYPE_SH7091
config CPU_SUBTYPE_SH7750R
bool "Support SH7750R processor"
select CPU_SH4
+ select COMMON_CLK_SH7750 if COMMMON_CLK
config CPU_SUBTYPE_SH7750S
bool "Support SH7750S processor"
select CPU_SH4
+ select COMMON_CLK_SH7750 if COMMMON_CLK
config CPU_SUBTYPE_SH7751
bool "Support SH7751 processor"
select CPU_SH4
+ select COMMON_CLK_SH7750 if COMMMON_CLK
help
Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
or if you have a HD6417751R CPU.
@@ -378,6 +381,8 @@ config CPU_SUBTYPE_SH7751
config CPU_SUBTYPE_SH7751R
bool "Support SH7751R processor"
select CPU_SH4
+ select COMMON_CLK_SH7750 if COMMMON_CLK
+ select PCI_SH7751 if SH_DEVICE_TREE
config CPU_SUBTYPE_SH7760
bool "Support SH7760 processor"
@@ -702,7 +707,7 @@ config BUILTIN_DTB_SOURCE
config ZERO_PAGE_OFFSET
hex
default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
- SH_7751_SOLUTION_ENGINE
+ SH_7751_SOLUTION_ENGINE || SH_RTS7751R2D_OF
default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
default "0x00002000" if PAGE_SIZE_8KB
default "0x00001000"
@@ -744,6 +749,7 @@ config ROMIMAGE_MMCIF
choice
prompt "Kernel command line"
optional
+ depends on !SH_DEVICE_TREE
default CMDLINE_OVERWRITE
help
Setting this option allows the kernel command line arguments
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index fafe15d3ba1d..ffdada2a128d 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -16,9 +16,14 @@ config SH_DEVICE_TREE
bool
select OF
select OF_EARLY_FLATTREE
+ select OF_ADDRESS
select TIMER_OF
select COMMON_CLK
select GENERIC_CALIBRATE_DELAY
+ select GENERIC_IOMAP
+ select GENERIC_IRQ_CHIP
+ select SYS_SUPPORTS_PCI
+ select GENERIC_PCI_IOMAP if PCI
config SH_JCORE_SOC
bool "J-Core SoC"
@@ -161,6 +166,17 @@ config SH_RTS7751R2D
Select RTS7751R2D if configuring for a Renesas Technology
Sales SH-Graphics board.
+config SH_RTS7751R2D_OF
+ bool "RTS7751R2D (DeviceTree)"
+ depends on CPU_SUBTYPE_SH7751R
+ select HAVE_PCI
+ select IO_TRAPPED if MMU
+ select SH_DEVICE_TREE
+ select COMMON_CLK
+ help
+ Select RTS7751R2D if configuring for a Renesas Technology
+ Sales SH-Graphics board. (Use DeviceTree)
+
config SH_RSK
bool "Renesas Starter Kit"
depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \
@@ -300,8 +316,20 @@ config SH_LANDISK
bool "LANDISK"
depends on CPU_SUBTYPE_SH7751R
select HAVE_PCI
+ select SYS_SUPPORTS_PCI
+ help
+ I-O DATA DEVICE, INC. "LANDISK Series" support.
+
+config SH_LANDISK_OF
+ bool "LANDISK (DeviceTree)"
+ depends on CPU_SUBTYPE_SH7751R
+ select HAVE_PCI
+ select SYS_SUPPORTS_PCI
+ select SH_DEVICE_TREE
+ select COMMON_CLK
help
I-O DATA DEVICE, INC. "LANDISK Series" support.
+ Use Device Tree.
config SH_TITAN
bool "TITAN"
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 02/12] sh: Update OF handling.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 01/12] sh: Add OF target boards Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 03/12] sh: SH4 OF support Yoshinori Sato
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
- avoid build warning.
- reserve external dtb area.
- use generic interfaces on internal peripheral driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boards/of-generic.c | 28 +++++++++++++++++++++++++---
arch/sh/boot/compressed/head_32.S | 5 +++--
arch/sh/kernel/head_32.S | 2 +-
arch/sh/kernel/setup.c | 26 +++++++++++++++++++++++++-
4 files changed, 54 insertions(+), 7 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index f7f3e618e85b..ff4643b3deee 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -8,6 +8,7 @@
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <asm/machvec.h>
@@ -107,7 +108,7 @@ static int noopi(void)
return 0;
}
-static void __init sh_of_mem_reserve(void)
+static void __init sh_of_mem_init(void)
{
early_init_fdt_reserve_self();
early_init_fdt_scan_reserved_mem();
@@ -116,6 +117,8 @@ static void __init sh_of_mem_reserve(void)
static void __init sh_of_setup(char **cmdline_p)
{
struct device_node *root;
+ struct device_node *cpu;
+ int freq;
sh_mv.mv_name = "Unknown SH model";
root = of_find_node_by_path("/");
@@ -125,6 +128,9 @@ static void __init sh_of_setup(char **cmdline_p)
}
sh_of_smp_probe();
+ cpu = of_find_node_by_name(NULL, "cpu");
+ if (!of_property_read_u32(cpu, "clock-frequency", &freq))
+ preset_lpj = freq / 500;
}
static int sh_of_irq_demux(int irq)
@@ -157,8 +163,7 @@ static struct sh_machine_vector __initmv sh_of_generic_mv = {
.mv_init_irq = sh_of_init_irq,
.mv_clk_init = sh_of_clk_init,
.mv_mode_pins = noopi,
- .mv_mem_init = noop,
- .mv_mem_reserve = sh_of_mem_reserve,
+ .mv_mem_init = sh_of_mem_init,
};
struct sh_clk_ops;
@@ -170,3 +175,20 @@ void __init __weak arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
void __init __weak plat_irq_setup(void)
{
}
+
+static int __init sh_of_device_init(void)
+{
+ pr_info("SH generic board support: populating platform devices\n");
+ if (of_have_populated_dt()) {
+ of_platform_populate(NULL, of_default_bus_match_table,
+ NULL, NULL);
+ } else {
+ pr_crit("Device tree not populated\n");
+ }
+ return 0;
+}
+arch_initcall_sync(sh_of_device_init);
+
+void intc_finalize(void)
+{
+}
diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 7bb168133dbb..c5227ef636c3 100644
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -15,7 +15,8 @@ startup:
/* Load initial status register */
mov.l init_sr, r1
ldc r1, sr
-
+ /* Save FDT address */
+ mov r4, r13
/* Move myself to proper location if necessary */
mova 1f, r0
mov.l 1f, r2
@@ -84,7 +85,7 @@ l1:
/* Jump to the start of the decompressed kernel */
mov.l kernel_start_addr, r0
jmp @r0
- nop
+ mov r13,r4
.align 2
bss_start_addr:
diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S
index b603b7968b38..28cd8806f67c 100644
--- a/arch/sh/kernel/head_32.S
+++ b/arch/sh/kernel/head_32.S
@@ -56,7 +56,7 @@ ENTRY(empty_zero_page)
*/
ENTRY(_stext)
! Initialize Status Register
- mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
+ mov.l 1f, r0 ! MD=1, RB=0, BL=1, IMASK=0xF
ldc r0, sr
! Initialize global interrupt mask
#ifdef CONFIG_CPU_HAS_SR_RB
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index b3da2757faaf..8389b673f2e8 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -31,6 +31,7 @@
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
#include <linux/uaccess.h>
#include <uapi/linux/mount.h>
#include <asm/io.h>
@@ -79,7 +80,9 @@ extern int root_mountflags;
#define RAMDISK_PROMPT_FLAG 0x8000
#define RAMDISK_LOAD_FLAG 0x4000
+#ifndef CONFIG_OF
static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, };
+#endif
static struct resource code_resource = {
.name = "Kernel code",
@@ -104,6 +107,10 @@ unsigned long memory_limit = 0;
static struct resource mem_resources[MAX_NUMNODES];
+#if defined(CONFIG_OF)
+static void *dt_virt;
+#endif
+
int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
static int __init early_parse_mem(char *p)
@@ -180,7 +187,12 @@ void __init check_for_initrd(void)
#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
void calibrate_delay(void)
{
+#ifndef CONFIG_OF
struct clk *clk = clk_get(NULL, "cpu_clk");
+#else
+ struct device_node *cpu = of_find_node_by_name(NULL, "cpu");
+ struct clk *clk = of_clk_get_by_name(cpu, NULL);
+#endif
if (IS_ERR(clk))
panic("Need a sane CPU clock definition!");
@@ -249,7 +261,6 @@ void __init __weak plat_early_device_setup(void)
void __ref sh_fdt_init(phys_addr_t dt_phys)
{
static int done = 0;
- void *dt_virt;
/* Avoid calling an __init function on secondary cpus. */
if (done) return;
@@ -274,8 +285,16 @@ void __ref sh_fdt_init(phys_addr_t dt_phys)
void __init setup_arch(char **cmdline_p)
{
+#ifdef CONFIG_OF
+#ifndef CONFIG_USE_BUILTIN_DTB
+ memblock_reserve(__pa(dt_virt), fdt_totalsize(dt_virt));
+#endif
+ unflatten_device_tree();
+#endif
enable_mmu();
+
+#ifndef CONFIG_OF
ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
printk(KERN_NOTICE "Boot params:\n"
@@ -313,10 +332,15 @@ void __init setup_arch(char **cmdline_p)
strlcat(command_line, CONFIG_CMDLINE, sizeof(command_line));
#endif
#endif
+#endif
+#if !defined(CONFIG_OF) || defined(USE_BUILTIN_DTB)
/* Save unparsed command line copy for /proc/cmdline */
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
+#else
+ *cmdline_p = boot_command_line;
+#endif
parse_early_param();
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 03/12] sh: SH4 OF support.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 01/12] sh: Add OF target boards Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 02/12] sh: Update OF handling Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 04/12] clk: SH7750 / 7751 clk driver Yoshinori Sato
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
- switch generic framework in clock / PCI.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/drivers/Makefile | 2 ++
arch/sh/include/asm/io.h | 10 ++++++++++
arch/sh/include/asm/pci.h | 4 ++++
arch/sh/kernel/cpu/Makefile | 8 ++++++--
arch/sh/kernel/cpu/clock.c | 3 ++-
arch/sh/kernel/cpu/sh4/Makefile | 2 ++
6 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile
index 56b0acace6e7..eacbcefb26b2 100644
--- a/arch/sh/drivers/Makefile
+++ b/arch/sh/drivers/Makefile
@@ -5,7 +5,9 @@
obj-y += dma/ platform_early.o
+ifndef CONFIG_SH_DEVICE_TREE
obj-$(CONFIG_PCI) += pci/
+endif
obj-$(CONFIG_SUPERHYWAY) += superhyway/
obj-$(CONFIG_PUSH_SWITCH) += push-switch.o
obj-$(CONFIG_HEARTBEAT) += heartbeat.o
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index d8f3537ef57f..d14adf034780 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -292,4 +292,14 @@ static inline void iounmap(volatile void __iomem *addr) { }
int valid_phys_addr_range(phys_addr_t addr, size_t size);
int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+
+#ifdef __KERNEL__
+#define PCI_IOBASE 0xfe240000UL
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET PCI_IOBASE
+#define PIO_MASK 0x3ffffUL
+#define PIO_RESERVED 0x40000UL
+#endif /* __KERNEL__ */
+
#endif /* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 54c30126ea17..92b3bd604319 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -2,6 +2,7 @@
#ifndef __ASM_SH_PCI_H
#define __ASM_SH_PCI_H
+#ifndef CONFIG_SH_DEVICE_TREE
/* Can be used to override the logic in pci_scan_bus for skipping
already-configured bus numbers - to be used for buggy BIOSes
or architectures with incomplete PCI setup by the loader */
@@ -88,4 +89,7 @@ static inline int pci_proc_domain(struct pci_bus *bus)
return hose->need_domain_info;
}
+#else /* CONFIG_SH_DEVICE_TREE */
+#include <asm-generic/pci.h>
+#endif
#endif /* __ASM_SH_PCI_H */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 46118236bf04..e462a9552c92 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -16,6 +16,10 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
# Common interfaces.
obj-$(CONFIG_SH_ADC) += adc.o
+ifndef CONFIG_COMMON_CLK
obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
-
-obj-y += irq/ init.o clock.o fpu.o pfc.o proc.o
+endif
+ifndef CONFIG_GENERIC_IRQ_CHIP
+obj-y += irq/
+endif
+obj-y += init.o clock.o fpu.o pfc.o proc.o
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 6fb34410d630..e6c75d4ba7e1 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -14,12 +14,13 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
+#include <linux/of.h>
#include <asm/clock.h>
#include <asm/machvec.h>
int __init clk_init(void)
{
- int ret;
+ int ret = 0;
#ifndef CONFIG_COMMON_CLK
ret = arch_clk_init();
diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile
index 00c16331e07e..1e196c320b96 100644
--- a/arch/sh/kernel/cpu/sh4/Makefile
+++ b/arch/sh/kernel/cpu/sh4/Makefile
@@ -15,6 +15,7 @@ perf-$(CONFIG_CPU_SUBTYPE_SH7750) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7750S) := perf_event.o
perf-$(CONFIG_CPU_SUBTYPE_SH7091) := perf_event.o
+ifndef CONFIG_OF
# CPU subtype setup
obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
obj-$(CONFIG_CPU_SUBTYPE_SH7750R) += setup-sh7750.o
@@ -32,6 +33,7 @@ endif
# Additional clocks by subtype
clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
+endif
obj-y += $(clock-y)
obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 04/12] clk: SH7750 / 7751 clk driver.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (2 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 03/12] sh: SH4 OF support Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 05/12] drivers/irqchip: Add SH7751 and boards specific irqchip Yoshinori Sato
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
Use COMMON_CLK framework clock driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/sh/Kconfig | 7 +
drivers/clk/sh/Makefile | 2 +
drivers/clk/sh/clk-sh7750.c | 193 ++++++++++++++++++++
drivers/clk/sh/clk-shdiv.c | 341 ++++++++++++++++++++++++++++++++++++
drivers/sh/Makefile | 2 +
7 files changed, 547 insertions(+)
create mode 100644 drivers/clk/sh/Kconfig
create mode 100644 drivers/clk/sh/Makefile
create mode 100644 drivers/clk/sh/clk-sh7750.c
create mode 100644 drivers/clk/sh/clk-shdiv.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 93f38a8178ba..6aa0b6ece32d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -485,6 +485,7 @@ source "drivers/clk/ralink/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
+source "drivers/clk/sh/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/socfpga/Kconfig"
source "drivers/clk/sprd/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7cb000549b61..dd597305d494 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -136,3 +136,4 @@ endif
obj-y += xilinx/
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
+obj-$(CONFIG_SUPERH) += sh/
diff --git a/drivers/clk/sh/Kconfig b/drivers/clk/sh/Kconfig
new file mode 100644
index 000000000000..71b9bbb989cb
--- /dev/null
+++ b/drivers/clk/sh/Kconfig
@@ -0,0 +1,7 @@
+config COMMON_CLK_SH7750
+ bool "Clcok driver for SH7750/SH7751"
+ depends on CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
+ CPU_SUBTYPE_SH7750R || \
+ CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
+ help
+ This driver supports the Renesas SH7750 and SH7751 CPG.
diff --git a/drivers/clk/sh/Makefile b/drivers/clk/sh/Makefile
new file mode 100644
index 000000000000..7122c37655aa
--- /dev/null
+++ b/drivers/clk/sh/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_COMMON_CLK_SH7750) += clk-sh7750.o
+obj-$(CONFIG_COMMON_CLK_SH7750) += clk-shdiv.o
diff --git a/drivers/clk/sh/clk-sh7750.c b/drivers/clk/sh/clk-sh7750.c
new file mode 100644
index 000000000000..f41712a9cf44
--- /dev/null
+++ b/drivers/clk/sh/clk-sh7750.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas SH7750/51 clock driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+struct clk *sh_div_clk_register(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock);
+
+static DEFINE_SPINLOCK(clklock);
+
+static struct clk_div_table pdiv_table[] = {
+ { .val = 0, .div = 2, },
+ { .val = 1, .div = 3, },
+ { .val = 2, .div = 4, },
+ { .val = 3, .div = 6, },
+ { .val = 4, .div = 8, },
+ { .val = 0, .div = 0, },
+};
+
+static struct clk_div_table div_table[] = {
+ { .val = 0, .div = 1, },
+ { .val = 1, .div = 2, },
+ { .val = 2, .div = 3, },
+ { .val = 3, .div = 4, },
+ { .val = 4, .div = 6, },
+ { .val = 5, .div = 8, },
+ { .val = 0, .div = 0, },
+};
+
+struct pll_clock {
+ struct clk_hw hw;
+ void __iomem *frqcr;
+ void __iomem *wdt;
+ int md;
+ bool div1;
+};
+
+#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct pll_clock *pll_clock = to_pll_clock(hw);
+ unsigned long rate = parent_rate;
+ uint16_t frqcr;
+ static const int pll1[] = { 12, 12, 6, 12, 6, 12, 1};
+
+ frqcr = ioread16(pll_clock->frqcr);
+ if (frqcr & (1 << 10)) {
+ rate *= pll1[pll_clock->md];
+ if (pll_clock->md < 6 && pll_clock->div1)
+ rate /= 2;
+ }
+ return rate;
+}
+
+static const struct clk_ops pll_ops = {
+ .recalc_rate = pll_recalc_rate,
+};
+
+static void __init sh7750_pll_clk_setup(struct device_node *node)
+{
+ unsigned int num_parents;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ struct pll_clock *pll_clock;
+ struct clk_init_data init;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: no parent found", clk_name);
+ return;
+ }
+
+ pll_clock = kzalloc(sizeof(struct pll_clock), GFP_KERNEL);
+ if (!pll_clock)
+ return;
+
+ pll_clock->frqcr = of_iomap(node, 0);
+ if (pll_clock->frqcr == NULL) {
+ pr_err("%s: failed to map frequenct control register",
+ clk_name);
+ goto free_clock;
+ }
+
+ pll_clock->wdt = of_iomap(node, 1);
+ if (pll_clock->wdt == NULL) {
+ pr_err("%s: failed to map watchdog register", clk_name);
+ goto unmap_frqcr;
+ }
+
+ of_property_read_u32_index(node, "sh7750,md", 0, &pll_clock->md);
+ if (pll_clock->md >= 7) {
+ pr_err("%s: failed to clock mode setting (%d)\n",
+ clk_name, pll_clock->md);
+ goto unmap_wdt;
+ }
+ pll_clock->div1 = !of_property_read_bool(node, "sh7750,rtype");
+ parent_name = of_clk_get_parent_name(node, 0);
+ init.name = clk_name;
+ init.ops = &pll_ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ pll_clock->hw.init = &init;
+
+ clk = clk_register(NULL, &pll_clock->hw);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register %s pll clock (%ld)\n",
+ __func__, clk_name, PTR_ERR(clk));
+ goto unmap_wdt;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ return;
+
+unmap_wdt:
+ iounmap(pll_clock->wdt);
+unmap_frqcr:
+ iounmap(pll_clock->frqcr);
+free_clock:
+ kfree(pll_clock);
+}
+
+static void __init sh7750_div_clk_setup(struct device_node *node)
+{
+ unsigned int num_parents;
+ struct clk *clk;
+ const char *clk_name = node->name;
+ const char *parent_name;
+ void __iomem *freqcr = NULL;
+ int i;
+ int num_clks;
+ int offset;
+
+ num_parents = of_clk_get_parent_count(node);
+ if (num_parents < 1) {
+ pr_err("%s: no parent found", clk_name);
+ return;
+ }
+
+ num_clks = of_property_count_strings(node, "clock-output-names");
+ if (num_clks < 0) {
+ pr_err("%s: failed to count clocks", clk_name);
+ return;
+ }
+
+ freqcr = of_iomap(node, 0);
+ if (freqcr == NULL) {
+ pr_err("%s: failed to map divide register", clk_name);
+ goto error;
+ }
+
+ of_property_read_u32_index(node, "renesas,offset", 0, &offset);
+
+ parent_name = of_clk_get_parent_name(node, 0);
+ for (i = 0; i < num_clks; i++) {
+ of_property_read_string_index(node, "clock-output-names", i,
+ &clk_name);
+ clk = sh_div_clk_register(NULL, clk_name, parent_name,
+ freqcr,
+ offset, 3,
+ (offset == 0)?pdiv_table:div_table,
+ &clklock);
+ if (IS_ERR(clk))
+ pr_err("%s: failed to register %s div clock (%ld)\n",
+ __func__, clk_name, PTR_ERR(clk));
+ else
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ }
+error:
+ if (freqcr)
+ iounmap(freqcr);
+}
+
+CLK_OF_DECLARE(sh7750_div_clk, "renesas,sh7750-div-clock",
+ sh7750_div_clk_setup);
+CLK_OF_DECLARE(sh7750_pll_clk, "renesas,sh7750-pll-clock",
+ sh7750_pll_clk_setup);
diff --git a/drivers/clk/sh/clk-shdiv.c b/drivers/clk/sh/clk-shdiv.c
new file mode 100644
index 000000000000..2c016c413dd6
--- /dev/null
+++ b/drivers/clk/sh/clk-shdiv.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas SuperH divider clock driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+#define div_mask(width) ((1 << (width)) - 1)
+
+static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
+ u8 width)
+{
+ unsigned int maxdiv = 0, mask = div_mask(width);
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div > maxdiv && clkt->val <= mask)
+ maxdiv = clkt->div;
+ return maxdiv;
+}
+
+static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width)
+{
+ if (table)
+ return _get_table_maxdiv(table, width);
+ return div_mask(width) + 1;
+}
+
+static unsigned int _get_table_div(const struct clk_div_table *table,
+ unsigned int val)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->val == val)
+ return clkt->div;
+ return 0;
+}
+
+static unsigned int _get_div(const struct clk_div_table *table,
+ unsigned int val, u8 width)
+{
+ if (table)
+ return _get_table_div(table, val);
+ return val + 1;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return clkt->val;
+ return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+ unsigned int div, u8 width)
+{
+ if (table)
+ return _get_table_val(table, div);
+ return div - 1;
+}
+
+static unsigned long sh_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int div;
+
+ div = _get_div(table, val, divider->width);
+
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static unsigned long sh_clk_divider_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int val;
+
+ val = __raw_readw(divider->reg) >> divider->shift;
+ val &= div_mask(divider->width);
+
+ return sh_divider_recalc_rate(hw, parent_rate, val, divider->table);
+}
+
+static bool _is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
+{
+ const struct clk_div_table *clkt;
+
+ for (clkt = table; clkt->div; clkt++)
+ if (clkt->div == div)
+ return true;
+ return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div)
+{
+ if (table)
+ return _is_valid_table_div(table, div);
+ return true;
+}
+
+static int _round_up_table(const struct clk_div_table *table, int div)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round_up(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (table)
+ div = _round_up_table(table, div);
+
+ return div;
+}
+
+static int _div_round(const struct clk_div_table *table,
+ unsigned long parent_rate, unsigned long rate)
+{
+ return _div_round_up(table, parent_rate, rate);
+}
+
+static bool _is_best_div(unsigned long rate, unsigned long now,
+ unsigned long best)
+{
+ return now <= rate && now > best;
+}
+
+static int _next_div(const struct clk_div_table *table, int div)
+{
+ div++;
+
+ if (table)
+ return _round_up_table(table, div);
+
+ return div;
+}
+
+static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ int i, bestdiv = 0;
+ unsigned long parent_rate, best = 0, now, maxdiv;
+ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ maxdiv = _get_maxdiv(table, width);
+
+ if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
+ parent_rate = *best_parent_rate;
+ bestdiv = _div_round(table, parent_rate, rate);
+ bestdiv = bestdiv == 0 ? 1 : bestdiv;
+ bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
+ return bestdiv;
+ }
+
+ /*
+ * The maximum divider we can use without overflowing
+ * unsigned long in rate * i below
+ */
+ maxdiv = min(ULONG_MAX / rate, maxdiv);
+
+ for (i = _next_div(table, 0); i <= maxdiv;
+ i = _next_div(table, i)) {
+ if (rate * i == parent_rate_saved) {
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ *best_parent_rate = parent_rate_saved;
+ return i;
+ }
+ parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
+ rate * i);
+ now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
+ if (_is_best_div(rate, now, best)) {
+ bestdiv = i;
+ best = now;
+ *best_parent_rate = parent_rate;
+ }
+ }
+
+ if (!bestdiv) {
+ bestdiv = _get_maxdiv(table, width);
+ *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
+ }
+
+ return bestdiv;
+}
+
+static long sh_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate, const struct clk_div_table *table,
+ u8 width)
+{
+ int div;
+
+ div = clk_divider_bestdiv(hw, rate, prate, table, width);
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
+static long sh_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+
+ return sh_divider_round_rate(hw, rate, prate, divider->table,
+ divider->width);
+}
+
+static int sh_divider_get_val(unsigned long rate, unsigned long parent_rate,
+ const struct clk_div_table *table, u8 width)
+{
+ unsigned int div, value;
+
+ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ if (!_is_valid_div(table, div))
+ return -EINVAL;
+
+ value = _get_val(table, div, width);
+
+ return min_t(unsigned int, value, div_mask(width));
+}
+
+static int sh_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_divider *divider = to_clk_divider(hw);
+ unsigned int value;
+ unsigned long flags = 0;
+ u16 val;
+
+ value = sh_divider_get_val(rate, parent_rate, divider->table,
+ divider->width);
+
+ if (divider->lock)
+ spin_lock_irqsave(divider->lock, flags);
+ else
+ __acquire(divider->lock);
+
+ val = __raw_readw(divider->reg);
+ val &= ~(div_mask(divider->width) << divider->shift);
+ val |= value << divider->shift;
+ __raw_writew(val, divider->reg);
+
+ if (divider->lock)
+ spin_unlock_irqrestore(divider->lock, flags);
+ else
+ __release(divider->lock);
+
+ return 0;
+}
+
+static const struct clk_ops sh_clk_divider_ops = {
+ .recalc_rate = sh_clk_divider_recalc_rate,
+ .round_rate = sh_clk_divider_round_rate,
+ .set_rate = sh_clk_divider_set_rate,
+};
+
+static struct clk *_register_divider(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ struct clk_divider *div;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the divider */
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &sh_clk_divider_ops;
+ init.flags = 0;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ /* struct clk_divider assignments */
+ div->reg = reg;
+ div->shift = shift;
+ div->width = width;
+ div->lock = lock;
+ div->hw.init = &init;
+ div->table = table;
+
+ /* register the clock */
+ clk = clk_register(dev, &div->hw);
+
+ if (IS_ERR(clk))
+ kfree(div);
+
+ return clk;
+}
+
+struct clk *sh_div_clk_register(struct device *dev, const char *name,
+ const char *parent_name,
+ void __iomem *reg, u8 shift, u8 width,
+ const struct clk_div_table *table,
+ spinlock_t *lock)
+{
+ return _register_divider(dev, name, parent_name, reg, shift,
+ width, table, lock);
+}
+EXPORT_SYMBOL_GPL(sh_div_clk_register);
diff --git a/drivers/sh/Makefile b/drivers/sh/Makefile
index c53262835e85..ed0985caa414 100644
--- a/drivers/sh/Makefile
+++ b/drivers/sh/Makefile
@@ -2,7 +2,9 @@
#
# Makefile for the SuperH specific drivers.
#
+ifneq ($(CONFIG_RENESAS_SH_INTC),y)
obj-$(CONFIG_SH_INTC) += intc/
+endif
ifneq ($(CONFIG_COMMON_CLK),y)
obj-$(CONFIG_HAVE_CLK) += clk/
endif
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 05/12] drivers/irqchip: Add SH7751 and boards specific irqchip.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (3 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 04/12] clk: SH7750 / 7751 clk driver Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 06/12] drivers/pci: Add SH7751 PCI Host bridge driver Yoshinori Sato
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
- irq-renesas-sh7751: Renesas SH7751 internal INTC.
- irq-renesas-r2d: Renesas RTS7751R2D external interrupt encoder.
- irq-iodata-julian: IO DATA Device LANDISK external interrupt encoder.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-iodata-julian.c | 163 +++++++++++++++++++++++
drivers/irqchip/irq-renesas-r2d.c | 175 +++++++++++++++++++++++++
drivers/irqchip/irq-renesas-sh7751.c | 186 +++++++++++++++++++++++++++
5 files changed, 529 insertions(+)
create mode 100644 drivers/irqchip/irq-iodata-julian.c
create mode 100644 drivers/irqchip/irq-renesas-r2d.c
create mode 100644 drivers/irqchip/irq-renesas-sh7751.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 09e422da482f..372b22d5183f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -660,6 +660,10 @@ config APPLE_AIC
help
Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
such as the M1.
+config RENESAS_SH_INTC
+ def_bool y if SH_DEVICE_TREE
+ select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
config MCHP_EIC
bool "Microchip External Interrupt Controller"
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index ffd945fe71aa..a3859bdd0442 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -120,3 +120,4 @@ obj-$(CONFIG_IRQ_IDT3243X) += irq-idt3243x.o
obj-$(CONFIG_APPLE_AIC) += irq-apple-aic.o
obj-$(CONFIG_MCHP_EIC) += irq-mchp-eic.o
obj-$(CONFIG_SUNPLUS_SP7021_INTC) += irq-sp7021-intc.o
+obj-$(CONFIG_RENESAS_SH_INTC) += irq-renesas-sh7751.o irq-iodata-julian.o irq-renesas-r2d.o
diff --git a/drivers/irqchip/irq-iodata-julian.c b/drivers/irqchip/irq-iodata-julian.c
new file mode 100644
index 000000000000..95e502904a68
--- /dev/null
+++ b/drivers/irqchip/irq-iodata-julian.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IO-DATA DEVICE LANDISK / USL-5P (a.k.a Julian) interrupt encoder
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define NUM_IRQ 16
+
+struct julian_intc_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct irq_domain *irq_domain;
+};
+
+static struct julian_intc_priv *irq_data_to_priv(struct irq_data *data)
+{
+ return data->domain->host_data;
+}
+
+static void julian_intc_mask_irq(struct irq_data *data)
+{
+ struct julian_intc_priv *priv = irq_data_to_priv(data);
+ int irq = data->irq;
+ u8 mask;
+
+ mask = __raw_readb(priv->base + 5);
+ mask &= ~(1 << (irq - 5));
+ __raw_writeb(mask, priv->base + 5);
+}
+
+static void julian_intc_unmask_irq(struct irq_data *data)
+{
+ struct julian_intc_priv *priv = irq_data_to_priv(data);
+ int irq = data->irq;
+ u8 mask;
+
+ mask = __raw_readb(priv->base + 5);
+ mask |= (1 << (irq - 5));
+ __raw_writeb(mask, priv->base + 5);
+}
+
+static struct irq_chip julian_intc_chip = {
+ .name = "JULIAN-INTC",
+ .irq_unmask = julian_intc_unmask_irq,
+ .irq_mask = julian_intc_mask_irq,
+};
+
+static __init int julian_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &julian_intc_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+
+static int julian_intc_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec, unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (fwspec->param[0] >= NUM_IRQ)
+ return -EINVAL;
+
+ switch (fwspec->param_count) {
+ case 2:
+ *type = fwspec->param[1];
+ fallthrough;
+ case 1:
+ *hwirq = fwspec->param[0];
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct irq_domain_ops julian_intc_domain_ops = {
+ .map = julian_intc_map,
+ .translate = julian_intc_translate,
+};
+
+static int julian_intc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct julian_intc_priv *priv;
+ struct irq_domain *d;
+ int ret = 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ d = irq_domain_add_tree(np, &julian_intc_domain_ops, priv);
+ if (d == NULL) {
+ dev_err(dev, "cannot initialize irq domain\n");
+ kfree(priv);
+ ret = -ENOMEM;
+ } else {
+ priv->irq_domain = d;
+ irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED);
+ }
+ return ret;
+}
+
+static int julian_intc_remove(struct platform_device *pdev)
+{
+ struct julian_intc_priv *priv = platform_get_drvdata(pdev);
+
+ irq_domain_remove(priv->irq_domain);
+ return 0;
+}
+
+static const struct of_device_id julian_intc_dt_ids[] = {
+ { .compatible = "iodata,julian-intc" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, julian_intc_dt_ids);
+
+static struct platform_driver julian_intc_device_driver = {
+ .probe = julian_intc_probe,
+ .remove = julian_intc_remove,
+ .driver = {
+ .name = "iodata_julian_intc",
+ .of_match_table = julian_intc_dt_ids,
+ }
+};
+
+static int __init julian_intc_init(void)
+{
+ return platform_driver_register(&julian_intc_device_driver);
+}
+postcore_initcall(julian_intc_init);
+
+static void __exit julian_intc_exit(void)
+{
+ platform_driver_unregister(&julian_intc_device_driver);
+}
+module_exit(julian_intc_exit);
+
+MODULE_AUTHOR("Yoshinori Sato");
+MODULE_DESCRIPTION("IO-DATA JULIAN external interrupt encoder");
diff --git a/drivers/irqchip/irq-renesas-r2d.c b/drivers/irqchip/irq-renesas-r2d.c
new file mode 100644
index 000000000000..595057c1f5aa
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-r2d.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RTS7751R2D interrupt encoder
+ *
+ * Copyright (C) 2023 Yoshinori Sato
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define NUM_IRQ 15
+
+struct r2d_intc_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct irq_domain *irq_domain;
+};
+
+static const int imask[] = {
+ 1 << 11, /* PCI INTD */
+ 1 << 9, /* CF IDE */
+ 1 << 8, /* CF CD */
+ 1 << 12, /* PCI INTC */
+ 1 << 10, /* SM501 */
+ 1 << 6, /* AX88796 / KEY */
+ 1 << 5, /* RTC ALARM */
+ 1 << 4, /* RTC T */
+ 1 << 7, /* SDCARD */
+ 1 << 14, /* PCI INTA */
+ 1 << 13, /* PCI INTB */
+ 1 << 0, /* EXT */
+ 1 << 15, /* TP */
+};
+
+static struct r2d_intc_priv *irq_data_to_priv(struct irq_data *data)
+{
+ return data->domain->host_data;
+}
+
+static void r2d_intc_mask_irq(struct irq_data *data)
+{
+ struct r2d_intc_priv *priv = irq_data_to_priv(data);
+ u16 mask;
+
+ mask = __raw_readw(priv->base);
+ mask &= ~(imask[data->irq]);
+ __raw_writew(mask, priv->base);
+}
+
+static void r2d_intc_unmask_irq(struct irq_data *data)
+{
+ struct r2d_intc_priv *priv = irq_data_to_priv(data);
+ u16 mask;
+
+ mask = __raw_readw(priv->base);
+ mask |= imask[data->irq];
+ __raw_writew(mask, priv->base);
+}
+
+static struct irq_chip r2d_intc_chip = {
+ .name = "R2D-INTC",
+ .irq_unmask = r2d_intc_unmask_irq,
+ .irq_mask = r2d_intc_mask_irq,
+};
+
+static __init int r2d_intc_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &r2d_intc_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+
+static int r2d_intc_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec, unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (fwspec->param[0] >= NUM_IRQ)
+ return -EINVAL;
+
+ switch (fwspec->param_count) {
+ case 2:
+ *type = fwspec->param[1];
+ fallthrough;
+ case 1:
+ *hwirq = fwspec->param[0];
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct irq_domain_ops r2d_intc_domain_ops = {
+// .alloc = r2d_intc_alloc,
+ .map = r2d_intc_map,
+ .translate = r2d_intc_translate,
+};
+
+static int r2d_intc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct r2d_intc_priv *priv;
+ struct irq_domain *d;
+ int ret = 0;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ d = irq_domain_add_tree(np, &r2d_intc_domain_ops, priv);
+ if (d == NULL) {
+ dev_err(dev, "cannot initialize irq domain\n");
+ kfree(priv);
+ ret = -ENOMEM;
+ } else {
+ priv->irq_domain = d;
+ irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED);
+ }
+ return ret;
+}
+
+static int r2d_intc_remove(struct platform_device *pdev)
+{
+ struct r2d_intc_priv *priv = platform_get_drvdata(pdev);
+
+ irq_domain_remove(priv->irq_domain);
+ return 0;
+}
+
+static const struct of_device_id r2d_intc_dt_ids[] = {
+ { .compatible = "renesas,rts7751r2d-intc" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, r2d_intc_dt_ids);
+
+static struct platform_driver r2d_intc_device_driver = {
+ .probe = r2d_intc_probe,
+ .remove = r2d_intc_remove,
+ .driver = {
+ .name = "renesas_r2d_intc",
+ .of_match_table = r2d_intc_dt_ids,
+ }
+};
+
+static int __init r2d_intc_init(void)
+{
+ return platform_driver_register(&r2d_intc_device_driver);
+}
+postcore_initcall(r2d_intc_init);
+
+static void __exit r2d_intc_exit(void)
+{
+ platform_driver_unregister(&r2d_intc_device_driver);
+}
+module_exit(r2d_intc_exit);
+
+MODULE_AUTHOR("Yoshinori Sato");
+MODULE_DESCRIPTION("Renesas RTS7751R2D external interrupt encoder");
diff --git a/drivers/irqchip/irq-renesas-sh7751.c b/drivers/irqchip/irq-renesas-sh7751.c
new file mode 100644
index 000000000000..1c4b2be44c27
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-sh7751.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 interrupt controller driver
+ *
+ * Copyright 2023 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of.h>
+#include <linux/io.h>
+
+static struct sh7751_intc_regs {
+ void *icr;
+ void *ipr;
+ void *intpri00;
+ void *intreq00;
+ void *intmsk00;
+ void *intmskclr00;
+} sh7751_regs;
+
+#define ICR_IRLM (1 << 7)
+
+static const unsigned int ipr_table[] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0 - 7 */
+ 0x41, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, /* 8 - 15 */
+ 0x03, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x11, /* 16 - 23 */
+ 0x11, 0x11, 0x11, 0x13, 0x12, 0x12, 0xff, 0xff, /* 24 - 31 */
+ 0x30, 0x33, 0x32, 0x32, 0x32, 0x32, 0x32, 0x21, /* 32 - 39 */
+ 0x21, 0x21, 0x21, 0x21, 0x32, 0x32, 0x32, 0x32, /* 40 - 47 */
+ 0xff, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, /* 48 - 55 */
+ 0xff, 0xff, 0xff, 0x40, 0xff, 0xff, 0xff, 0xff, /* 56 - 63 */
+};
+
+static const unsigned int pri_table[] = {
+ 0, 4, 4, 4, 4, 4, 4, 4,
+ 8, 32, 32, 32, 12, 32, 32, 32,
+};
+
+/* Bitmap of IRQ masked */
+#define IMASK_PRIORITY 15
+
+static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
+static int interrupt_priority;
+
+static inline void set_interrupt_registers(int ip)
+{
+ unsigned long __dummy;
+
+ asm volatile(
+#ifdef CONFIG_CPU_HAS_SR_RB
+ "ldc %2, r6_bank\n\t"
+#endif
+ "stc sr, %0\n\t"
+ "and #0xf0, %0\n\t"
+ "shlr2 %0\n\t"
+ "cmp/eq #0x3c, %0\n\t"
+ "bt/s 1f ! CLI-ed\n\t"
+ " stc sr, %0\n\t"
+ "and %1, %0\n\t"
+ "or %2, %0\n\t"
+ "ldc %0, sr\n"
+ "1:"
+ : "=&z" (__dummy)
+ : "r" (~0xf0), "r" (ip << 4)
+ : "t");
+}
+
+static void update_ipr(struct sh7751_intc_regs *reg, int irq, int on)
+{
+ unsigned int addr;
+ int pos;
+ uint16_t pri;
+
+ if (irq < 64) {
+ if (ipr_table[irq] != 0xff) {
+ addr = (ipr_table[irq] & 0xf0) >> 2;
+ pos = (ipr_table[irq] & 0x0f) * 4;
+ pri = ~(0x000f << pos);
+ pri &= __raw_readw(reg->ipr + addr);
+ if (on)
+ pri |= 1 << pos;
+ __raw_writew(pri, reg->ipr + addr);
+ }
+ } else {
+ if (pri_table[irq - 64] < 32) {
+ pos = pri_table[irq - 64];
+ pri = ~(0x000f << pos);
+ pri &= __raw_readw(reg->intpri00);
+ if (on)
+ pri |= 1 << pos;
+ __raw_writew(pri, reg->intpri00);
+ }
+ }
+}
+
+static void sh7751_disable_irq(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ struct sh7751_intc_regs *reg = data->chip_data;
+ uint16_t icr = __raw_readw(reg->icr);
+
+ if (irq < 16 && (icr & ICR_IRLM) == 0) {
+ clear_bit(irq, imask_mask);
+ if (interrupt_priority < IMASK_PRIORITY - irq)
+ interrupt_priority = IMASK_PRIORITY - irq;
+ set_interrupt_registers(interrupt_priority);
+ } else
+ update_ipr(reg, irq, 0);
+}
+
+static void sh7751_enable_irq(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ struct sh7751_intc_regs *reg = data->chip_data;
+ uint16_t icr = __raw_readw(reg->icr);
+
+ if (irq < 16 && (icr & ICR_IRLM) == 0) {
+ set_bit(irq, imask_mask);
+ interrupt_priority = IMASK_PRIORITY -
+ find_first_bit(imask_mask, IMASK_PRIORITY);
+ set_interrupt_registers(interrupt_priority);
+ } else
+ update_ipr(reg, irq, 1);
+}
+
+struct irq_chip sh7751_irq_chip = {
+ .name = "SH7751-INTC",
+ .irq_unmask = sh7751_enable_irq,
+ .irq_mask = sh7751_disable_irq,
+};
+
+static int irq_sh7751_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw_irq_num)
+{
+ irq_set_chip_and_handler(virq, &sh7751_irq_chip, handle_level_irq);
+ irq_get_irq_data(virq)->chip_data = h->host_data;
+ irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOPROBE);
+ return 0;
+}
+static const struct irq_domain_ops irq_ops = {
+ .map = irq_sh7751_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sh7751_intc_of_init(struct device_node *intc,
+ struct device_node *parent)
+{
+ unsigned short icr;
+ struct irq_domain *domain;
+ void *intc_baseaddr;
+ void *intc_baseaddr2;
+
+ intc_baseaddr = of_iomap(intc, 0);
+ intc_baseaddr2 = of_iomap(intc, 1);
+ if (!intc_baseaddr) {
+ pr_err("Invalid INTC address\n");
+ return -EINVAL;
+ }
+
+ sh7751_regs.icr = intc_baseaddr;
+ sh7751_regs.ipr = intc_baseaddr + 4;
+ sh7751_regs.intpri00 = intc_baseaddr2;
+ sh7751_regs.intreq00 = intc_baseaddr2 + 0x20;
+ sh7751_regs.intmsk00 = intc_baseaddr2 + 0x40;
+ sh7751_regs.intmskclr00 = intc_baseaddr2 + 0x60;
+
+ if (of_property_read_bool(intc, "sh7751,irlm")) {
+ icr = __raw_readw(sh7751_regs.icr);
+ icr |= 0x80; // IRLM = 1
+ __raw_writew(icr, sh7751_regs.icr);
+ }
+
+ domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, &sh7751_regs);
+ if (!domain) {
+ pr_err("Unable to allocate domain handle\n");
+ return -ENOMEM;
+ }
+ irq_set_default_host(domain);
+ return 0;
+}
+
+IRQCHIP_DECLARE(sh_7751_intc,
+ "renesas,sh7751-intc", sh7751_intc_of_init);
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 06/12] drivers/pci: Add SH7751 PCI Host bridge driver.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (4 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 05/12] drivers/irqchip: Add SH7751 and boards specific irqchip Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 07/12] clocksource: Update sh_tmu of handling Yoshinori Sato
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
Use Common framework host bridge driver.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pci-sh7751.c | 382 ++++++++++++++++++++++++++++
drivers/pci/controller/pci-sh7751.h | 267 +++++++++++++++++++
4 files changed, 659 insertions(+)
create mode 100644 drivers/pci/controller/pci-sh7751.c
create mode 100644 drivers/pci/controller/pci-sh7751.h
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 8d49bad7f847..2aac15bec897 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -343,6 +343,15 @@ config PCIE_XILINX_CPM
Say 'Y' here if you want kernel support for the
Xilinx Versal CPM host bridge.
+config PCI_SH7751
+ bool "Renesas SH7751 PCI controller"
+ depends on OF
+ depends on CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
+ select PCI_HOST_COMMON
+ help
+ Say 'Y' here if you want kernel to support the Renesas SH7751 PCI
+ Host Bridge driver.
+
source "drivers/pci/controller/cadence/Kconfig"
source "drivers/pci/controller/dwc/Kconfig"
source "drivers/pci/controller/mobiveil/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 37c8663de7fe..ce96cfe9f1f2 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
+obj-$(CONFIG_PCI_SH7751) += pci-sh7751.o
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
diff --git a/drivers/pci/controller/pci-sh7751.c b/drivers/pci/controller/pci-sh7751.c
new file mode 100644
index 000000000000..b81f489b4f05
--- /dev/null
+++ b/drivers/pci/controller/pci-sh7751.c
@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas SH7751 PCI Host bridge driver
+ * Copyright (C) 2023 Yoshinori Sato
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci-ecam.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <asm-generic/pci.h>
+#include "pci-sh7751.h"
+
+#define pcic_writel(val, reg) __raw_writel(val, pci_reg_base + (reg))
+#define pcic_readl(reg) __raw_readl(pci_reg_base + (reg))
+
+DEFINE_RAW_SPINLOCK(pci_config_lock);
+
+/*
+ * PCIC fixups
+ */
+
+#define PCIMCR_MRSET 0x40000000
+#define PCIMCR_RFSH 0x00000004
+
+static void __init julian_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
+{
+ unsigned long bcr1, mcr;
+
+ bcr1 = __raw_readl(bcr + SH7751_BCR1);
+ bcr1 |= 0x00080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
+ pcic_writel(bcr1, SH4_PCIBCR1);
+
+ mcr = __raw_readl(bcr + SH7751_MCR);
+ mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
+ pcic_writel(mcr, SH4_PCIMCR);
+
+ pcic_writel(0x0c000000, SH7751_PCICONF5);
+ pcic_writel(0xd0000000, SH7751_PCICONF6);
+ pcic_writel(0x0c000000, SH4_PCILAR0);
+ pcic_writel(0x00000000, SH4_PCILAR1);
+}
+
+static void __init r2dplus_fixup(void __iomem *pci_reg_base, void __iomem *bcr)
+{
+ unsigned long bcr1, mcr;
+
+ bcr1 = ioread32(bcr + SH7751_BCR1);
+ bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
+ pcic_writel(bcr1, SH4_PCIBCR1);
+
+ /* Enable all interrupts, so we known what to fix */
+ pcic_writel(0x0000c3ff, SH4_PCIINTM);
+ pcic_writel(0x0000380f, SH4_PCIAINTM);
+
+ pcic_writel(0xfb900047, SH7751_PCICONF1);
+ pcic_writel(0xab000001, SH7751_PCICONF4);
+
+ mcr = ioread32(bcr + SH7751_MCR);
+ mcr &= (~PCIMCR_MRSET) & (~PCIMCR_RFSH);
+ pcic_writel(mcr, SH4_PCIMCR);
+
+ pcic_writel(0x0c000000, SH7751_PCICONF5);
+ pcic_writel(0xd0000000, SH7751_PCICONF6);
+ pcic_writel(0x0c000000, SH4_PCILAR0);
+ pcic_writel(0x00000000, SH4_PCILAR1);
+}
+
+static const __initconst struct fixups {
+ char *compatible;
+ void (*fixup)(void __iomem *pcic_base, void __iomem *bcr);
+} fixup_list[] = {
+ {
+ .compatible = "iodata,julian",
+ .fixup = julian_fixup,
+ },
+ {
+ .compatible = "renesas,rts7751r2dplus",
+ .fixup = r2dplus_fixup,
+ },
+};
+
+static __init void pcic_fixups(struct device_node *np,
+ void __iomem *pcic, void __iomem *bcr)
+{
+ int i;
+ const struct fixups *f = fixup_list;
+
+ for (i = 0; i < ARRAY_SIZE(fixup_list); i++) {
+ if (of_device_is_compatible(np, f->compatible)) {
+ f->fixup(pcic, bcr);
+ break;
+ }
+ }
+}
+
+/*
+ * Direct access to PCI hardware...
+ */
+#define CONFIG_CMD(bus, devfn, where) \
+ (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
+
+/*
+ * Functions for accessing PCI configuration space with type 1 accesses
+ */
+static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)cfg->res.start;
+ unsigned long flags;
+ u32 data;
+
+ /*
+ * PCIPDR may only be accessed as 32 bit words,
+ * so we must do byte alignment by hand
+ */
+ raw_spin_lock_irqsave(&pci_config_lock, flags);
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ data = pcic_readl(SH4_PCIPDR);
+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+
+ switch (size) {
+ case 1:
+ *val = (data >> ((where & 3) << 3)) & 0xff;
+ break;
+ case 2:
+ *val = (data >> ((where & 2) << 3)) & 0xffff;
+ break;
+ case 4:
+ *val = data;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * Since SH4 only does 32bit access we'll have to do a read,
+ * mask,write operation.
+ * We'll allow an odd byte offset, though it should be illegal.
+ */
+static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)cfg->res.start;
+ unsigned long flags;
+ int shift;
+ u32 data;
+
+ raw_spin_lock_irqsave(&pci_config_lock, flags);
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ data = pcic_readl(SH4_PCIPDR);
+ raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+
+ switch (size) {
+ case 1:
+ shift = (where & 3) << 3;
+ data &= ~(0xff << shift);
+ data |= ((val & 0xff) << shift);
+ break;
+ case 2:
+ shift = (where & 2) << 3;
+ data &= ~(0xffff << shift);
+ data |= ((val & 0xffff) << shift);
+ break;
+ case 4:
+ data = val;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+
+ pcic_writel(data, SH4_PCIPDR);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * Called after each bus is probed, but before its children
+ * are examined.
+ */
+void pcibios_fixup_bus(struct pci_bus *bus)
+{
+}
+
+/*
+ * We need to avoid collisions with `mirrored' VGA ports
+ * and other strange ISA hardware, so we always want the
+ * addresses to be allocated in the 0x000-0x0ff region
+ * modulo 0x400.
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+ resource_size_t size, resource_size_t align)
+{
+ resource_size_t start = res->start;
+
+ return start;
+}
+
+int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+ enum pci_mmap_state mmap_state, int write_combine)
+{
+ /*
+ * I/O space can be accessed via normal processor loads and stores on
+ * this platform but for now we elect not to do this and portable
+ * drivers should not do this anyway.
+ */
+ if (mmap_state == pci_mmap_io)
+ return -EINVAL;
+
+ /*
+ * Ignore write-combine; for now only return uncached mappings.
+ */
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+ vma->vm_end - vma->vm_start,
+ vma->vm_page_prot);
+}
+
+static int __init area_sdram_check(void __iomem *pci_reg_base,
+ void __iomem *bcr,
+ unsigned int area)
+{
+ unsigned long word;
+
+ word = __raw_readl(bcr + SH7751_BCR1);
+ /* check BCR for SDRAM in area */
+ if (((word >> area) & 1) == 0) {
+ pr_info("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, SH4_PCIBCR1);
+
+ word = __raw_readw(bcr + SH7751_BCR2);
+ /* check BCR2 for 32bit SDRAM interface*/
+ if (((word >> (area << 1)) & 0x3) != 0x3) {
+ pr_info("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
+ area, word);
+ return 0;
+ }
+ pcic_writel(word, SH4_PCIBCR2);
+
+ return 1;
+}
+
+static __init int sh7751_pci_probe(struct platform_device *pdev)
+{
+ struct resource *res, *wres;
+ u32 id;
+ u32 reg, word;
+ void __iomem *pci_reg_base;
+ void __iomem *bcr;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pci_reg_base = (void __iomem *)res->start;
+ if (IS_ERR(pci_reg_base))
+ return PTR_ERR(pci_reg_base);
+
+ wres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (IS_ERR(wres))
+ return PTR_ERR(wres);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ bcr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pci_reg_base))
+ return PTR_ERR(bcr);
+
+ /* check for SH7751/SH7751R hardware */
+ id = pcic_readl(SH7751_PCICONF0);
+ if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
+ id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
+ pr_warn("PCI: This is not an SH7751(R)\n");
+ return -ENODEV;
+ }
+ dev_info(&pdev->dev, "PCI core found at %p\n",
+ pci_reg_base);
+
+ /* Set the BCR's to enable PCI access */
+ reg = __raw_readl(bcr);
+ reg |= 0x80000;
+ __raw_writel(reg, bcr);
+
+ /* Turn the clocks back on (not done in reset)*/
+ pcic_writel(0, SH4_PCICLKR);
+ /* Clear Powerdown IRQ's (not done in reset) */
+ word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
+ pcic_writel(word, SH4_PCIPINT);
+
+ /* set the command/status bits to:
+ * Wait Cycle Control + Parity Enable + Bus Master +
+ * Mem space enable
+ */
+ word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
+ SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
+ pcic_writel(word, SH7751_PCICONF1);
+
+ /* define this host as the host bridge */
+ word = PCI_BASE_CLASS_BRIDGE << 24;
+ pcic_writel(word, SH7751_PCICONF2);
+
+ /* Set IO and Mem windows to local address
+ * Make PCI and local address the same for easy 1 to 1 mapping
+ */
+ word = wres->end - wres->start - 1;
+ pcic_writel(word, SH4_PCILSR0);
+ /* Set the values on window 0 PCI config registers */
+ word = P2SEGADDR(wres->start);
+ pcic_writel(word, SH4_PCILAR0);
+ pcic_writel(word, SH7751_PCICONF5);
+
+ /* check BCR for SDRAM in specified area */
+ area_sdram_check(pci_reg_base, bcr, (wres->start >> 27) & 0x07);
+
+ /* configure the wait control registers */
+ word = __raw_readl(bcr + SH7751_WCR1);
+ pcic_writel(word, SH4_PCIWCR1);
+ word = __raw_readl(bcr + SH7751_WCR2);
+ pcic_writel(word, SH4_PCIWCR2);
+ word = __raw_readl(bcr + SH7751_WCR3);
+ pcic_writel(word, SH4_PCIWCR3);
+ word = __raw_readl(bcr + SH7751_MCR);
+ pcic_writel(word, SH4_PCIMCR);
+
+ pcic_fixups(pdev->dev.of_node, pci_reg_base, bcr);
+
+ /* SH7751 init done, set central function init complete */
+ /* use round robin mode to stop a device starving/overruning */
+ word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
+ pcic_writel(word, SH4_PCICR);
+
+ return pci_host_common_probe(pdev);
+}
+
+static void __iomem *sh4_pci_map_bus(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *pci_reg_base = (void __iomem *)cfg->res.start;
+
+ pcic_writel(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
+ return pci_reg_base + SH4_PCIPDR;
+}
+
+static const struct pci_ecam_ops pci_sh7751_bus_ops = {
+ .pci_ops = {
+ .map_bus = sh4_pci_map_bus,
+ .read = sh4_pci_read,
+ .write = sh4_pci_write,
+ }
+};
+
+static const struct of_device_id sh7751_pci_of_match[] = {
+ { .compatible = "renesas,sh7751-pci",
+ .data = &pci_sh7751_bus_ops },
+
+ { },
+};
+MODULE_DEVICE_TABLE(of, sh7751_pci_of_match);
+
+static struct platform_driver sh7751_pci_driver = {
+ .driver = {
+ .name = "sh7751-pci",
+ .of_match_table = sh7751_pci_of_match,
+ },
+ .probe = sh7751_pci_probe,
+};
+module_platform_driver(sh7751_pci_driver);
+
+MODULE_DESCRIPTION("SH7751 PCI Host brige driver");
+MODULE_AUTHOR("Yoshinori Sato");
+
diff --git a/drivers/pci/controller/pci-sh7751.h b/drivers/pci/controller/pci-sh7751.h
new file mode 100644
index 000000000000..b2d74d57addb
--- /dev/null
+++ b/drivers/pci/controller/pci-sh7751.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Low-Level PCI Support for SH7751 targets
+ *
+ * Dustin McIntire (dustin@sensoria.com) (c) 2001
+ * Paul Mundt (lethal@linux-sh.org) (c) 2003
+ *
+ */
+
+#ifndef _PCI_SH7751_H_
+#define _PCI_SH7751_H_
+
+#define SH4_PCICR 0x100 /* PCI Control Register */
+ #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
+ #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
+ #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */
+ #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */
+ #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
+ #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
+ #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */
+ #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */
+ #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */
+ #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */
+ #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
+#define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */
+#define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */
+#define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */
+#define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */
+#define SH4_PCIINT 0x114 /* PCI Interrupt Register */
+ #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */
+ #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */
+ #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */
+ #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
+ #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */
+ #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */
+ #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
+ #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */
+ #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
+ #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
+ #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
+ #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */
+#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */
+ #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
+ #define SH4_PCIINTM_TMTOIM BIT(9) /* Target retry timeout */
+ #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
+ #define SH4_PCIINTM_APEDIM BIT(7) /* Address parity error detection */
+ #define SH4_PCIINTM_SDIM BIT(6) /* SERR detection */
+ #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
+ #define SH4_PCIINTM_PEDITRM BIT(4) /* PERR detection for target read */
+ #define SH4_PCIINTM_TADIMM BIT(3) /* Target abort for master */
+ #define SH4_PCIINTM_MADIMM BIT(2) /* Master abort for master */
+ #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
+ #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
+#define SH4_PCIALR 0x11C /* Error Address Register */
+#define SH4_PCICLR 0x120 /* Error Command/Data */
+ #define SH4_PCICLR_MPIO 0x80000000
+ #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
+ #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
+ #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
+ #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
+ #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
+ #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
+#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */
+ #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
+ #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
+ #define SH4_PCIAINT_MBTO 0x00000800 /* Master Bus Time Out */
+ #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */
+ #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */
+ #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
+ #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
+#define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
+#define SH4_PCIBMLR 0x138 /* Error Bus Master Register */
+ #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
+ #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
+ #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
+ #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
+ #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
+#define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
+ #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
+#define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
+#define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */
+#define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
+#define SH4_PCIDCR0 0x18C /* DMA0 Control Register */
+ #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
+ #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
+ #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
+ #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
+ #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */
+ #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
+ #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
+ #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
+ #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
+ #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */
+#define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
+#define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */
+#define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
+#define SH4_PCIDCR1 0x19C /* DMA1 Control Register */
+#define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
+#define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */
+#define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
+#define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
+#define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
+#define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */
+#define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
+#define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */
+#define SH4_PCIPAR 0x1C0 /* PIO Address Register */
+ #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
+ #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
+ #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
+ #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */
+#define SH4_PCIMBR 0x1C4 /* Memory Base Address */
+ #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
+ #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
+#define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */
+ #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
+ #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
+#define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
+ #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
+ #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
+#define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
+#define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */
+ #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
+ #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
+/* For definitions of BCR, MCR see ... */
+#define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */
+ #define SH4_PCIMBR0 SH4_PCIBCR1
+#define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */
+ #define SH4_PCIMBMR0 SH4_PCIBCR2
+#define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */
+#define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */
+#define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */
+ #define SH4_PCIMBR2 SH4_PCIWCR3
+#define SH4_PCIMCR 0x1F4 /* Memory Control Register */
+#define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */
+#define SH4_PCIPCTR 0x200 /* Port Control Register */
+ #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
+ #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
+ #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
+ #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
+ #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
+ #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
+ #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
+ #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
+ #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
+#define SH4_PCIPDTR 0x204 /* Port Data Register */
+ #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
+ #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
+ #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
+ #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
+ #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
+ #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
+#define SH4_PCIPDR 0x220 /* Port IO Data Register */
+
+/* Platform Specific Values */
+#define SH7751_VENDOR_ID 0x1054
+#define SH7751_DEVICE_ID 0x3505
+#define SH7751R_DEVICE_ID 0x350e
+
+/* SH7751 Specific Values */
+#define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
+#define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
+#define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
+#define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+#define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
+#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
+
+#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
+
+#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
+ #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
+ #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */
+#define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
+ #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */
+ #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */
+ #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */
+ #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */
+ #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */
+ #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */
+ #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */
+ #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */
+ #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */
+ #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */
+ #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */
+ #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */
+ #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */
+ #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */
+ #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */
+ #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */
+ #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
+ #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */
+ #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */
+ #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
+ #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */
+#define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
+ #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
+ #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
+ #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
+ #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
+#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
+ #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
+ #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
+ #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
+ #define SH7751_PCICONF3_HD7 0x00800000 /* Single Function device */
+ #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */
+ #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */
+ #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */
+#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
+ #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
+ #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
+ #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
+#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
+ #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
+ #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
+ #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
+ #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
+/* PCICONF7 - PCICONF10 are undefined */
+#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
+ #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
+ #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */
+/* PCICONF12 is undefined */
+#define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
+ #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */
+/* PCICONF14 is undefined */
+#define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
+ #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */
+#define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
+ #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */
+ #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */
+ #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */
+ #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */
+ #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */
+ #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */
+ #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */
+ #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */
+#define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
+ #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */
+ #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */
+ #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */
+ #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */
+ #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */
+ #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */
+/* SH7751 Internal PCI Registers */
+
+/* Memory Control Registers */
+#define SH7751_BCR1 0x0000 /* Memory BCR1 Register */
+#define SH7751_BCR2 0x0004 /* Memory BCR2 Register */
+#define SH7751_BCR3 0x0050 /* Memory BCR3 Register */
+#define SH7751_WCR1 0x0008 /* Wait Control 1 Register */
+#define SH7751_WCR2 0x000C /* Wait Control 2 Register */
+#define SH7751_WCR3 0x0010 /* Wait Control 3 Register */
+#define SH7751_MCR 0x0014 /* Memory Control Register */
+
+/* General Memory Config Addresses */
+#define SH7751_CS0_BASE_ADDR 0x0
+#define SH7751_MEM_REGION_SIZE 0x04000000
+#define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
+
+#endif /* _PCI_SH7751_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 07/12] clocksource: Update sh_tmu of handling.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (5 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 06/12] drivers/pci: Add SH7751 PCI Host bridge driver Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 08/12] mfd/sm501: Add OF properties Yoshinori Sato
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/clocksource/sh_tmu.c | 33 +++++++++++++++++----------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index beffff81c00f..de65e1c96780 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -420,9 +420,6 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
ced->suspend = sh_tmu_clock_event_suspend;
ced->resume = sh_tmu_clock_event_resume;
- dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
- ch->index);
-
clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);
ret = request_irq(ch->irq, sh_tmu_interrupt,
@@ -500,12 +497,12 @@ static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
tmu->model = SH_TMU;
tmu->num_channels = 3;
- of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
-
- if (tmu->num_channels != 2 && tmu->num_channels != 3) {
- dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
- tmu->num_channels);
- return -EINVAL;
+ if (of_property_read_u32(np, "#renesas,channels", &tmu->num_channels)) {
+ if (tmu->num_channels != 2 && tmu->num_channels != 3) {
+ dev_err(&tmu->pdev->dev,
+ "invalid number of channels %u\n", tmu->num_channels);
+ return -EINVAL;
+ }
}
return 0;
@@ -513,7 +510,6 @@ static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
{
- unsigned int i;
int ret;
tmu->pdev = pdev;
@@ -535,6 +531,11 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
return -ENXIO;
}
+ if (tmu->num_channels < 2) {
+ dev_err(&tmu->pdev->dev, "Invalid channels.\n");
+ return -ENXIO;
+ }
+
/* Get hold of clock. */
tmu->clk = clk_get(&tmu->pdev->dev, "fck");
if (IS_ERR(tmu->clk)) {
@@ -573,12 +574,12 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
* Use the first channel as a clock event device and the second channel
* as a clock source.
*/
- for (i = 0; i < tmu->num_channels; ++i) {
- ret = sh_tmu_channel_setup(&tmu->channels[i], i,
- i == 0, i == 1, tmu);
- if (ret < 0)
- goto err_unmap;
- }
+ ret = sh_tmu_channel_setup(&tmu->channels[0], 0, false, true, tmu);
+ if (ret < 0)
+ goto err_unmap;
+ ret = sh_tmu_channel_setup(&tmu->channels[1], 1, true, false, tmu);
+ if (ret < 0)
+ goto err_unmap;
platform_set_drvdata(pdev, tmu);
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 08/12] mfd/sm501: Add OF properties.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (6 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 07/12] clocksource: Update sh_tmu of handling Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 09/12] of: FDT vaddr support for SH Yoshinori Sato
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
Some parameters only platform_device.
Added same parameters in OF property.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
.../devicetree/bindings/display/sm501fb.txt | 11 ++
drivers/mfd/sm501.c | 113 +++++++++++++++++-
2 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sm501fb.txt b/Documentation/devicetree/bindings/display/sm501fb.txt
index 1c79c267a57f..4c4920394431 100644
--- a/Documentation/devicetree/bindings/display/sm501fb.txt
+++ b/Documentation/devicetree/bindings/display/sm501fb.txt
@@ -20,6 +20,17 @@ Optional properties:
set different foreign endian.
- big-endian: available on little endian systems, to
set different foreign endian.
+- sm501,devices: select peripheral functions.
+ available usb-host, usb-gadget, ssp0, ssp,1 uart0, uart1, accel,
+ ac97, i2s, gpio and all.
+- sm501,mclk: SM501 mclk frequency.
+- sm501,m1xclk: SM501 m1xclk frequency.
+- sm501,misc-timing: SM501 Miscellaneous Timing reg value.
+- sm501,misc-control: SM501 Miscellaneous Control reg value.
+- sm501,gpio-low: SM501 GPIO31-0 Control reg value.
+- sm501,gpio-high: SM501 GPIO63-32 Control reg value.
+- sm501,num-i2c: I2C channel number.
+- sm501,gpio-i2c: I2C assigned GPIO.
Example for MPC5200:
display@1,0 {
diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c
index 28027982cf69..39871ca1b9f7 100644
--- a/drivers/mfd/sm501.c
+++ b/drivers/mfd/sm501.c
@@ -80,6 +80,9 @@ struct sm501_devdata {
unsigned int irq;
void __iomem *regs;
unsigned int rev;
+#if defined(CONFIG_OF)
+ struct device_node *np;
+#endif
};
@@ -1370,6 +1373,106 @@ static int sm501_init_dev(struct sm501_devdata *sm)
return 0;
}
+static unsigned int sm501_parse_devices_str(const char *str)
+{
+ char *sep;
+ unsigned int device = 0;
+ int i;
+ int len;
+ static const struct {
+ char *devname;
+ unsigned int devid;
+ } devlist[] = {
+ { "usb-host", SM501_USE_USB_HOST },
+ { "usb-gadget", SM501_USE_USB_SLAVE },
+ { "ssp0", SM501_USE_SSP0 },
+ { "ssp1", SM501_USE_SSP1 },
+ { "uart0", SM501_USE_UART0 },
+ { "uart1", SM501_USE_UART1 },
+ { "accel", SM501_USE_FBACCEL },
+ { "ac97", SM501_USE_AC97 },
+ { "i2s", SM501_USE_I2S },
+ { "gpio", SM501_USE_GPIO },
+ { "all", SM501_USE_ALL },
+ };
+
+ do {
+ sep = strchr(str, ',');
+ len = sep ? sep - str : strlen(str);
+ for (i = 0; i < ARRAY_SIZE(devlist); i++) {
+ if (strncasecmp(str, devlist[i].devname, len) == 0) {
+ device |= devlist[i].devid;
+ break;
+ }
+ }
+ str = sep + 1;
+ } while (sep);
+ return device;
+}
+
+#if defined(CONFIG_OF)
+static void sm501_of_read_reg_init(struct sm501_devdata *sm,
+ const char *propname, struct sm501_reg_init *val)
+{
+ u32 u32_val;
+
+ if (!of_property_read_u32_index(sm->np, propname, 0, &u32_val))
+ val->set = u32_val;
+ if (!of_property_read_u32_index(sm->np, propname, 1, &u32_val))
+ val->mask = u32_val;
+}
+
+static int sm501_parse_dt(struct sm501_devdata *sm)
+{
+ struct sm501_platdata *plat;
+ const char *devstr;
+ u32 u32_val;
+
+ if (sm->np == NULL)
+ return 0;
+ plat = kzalloc(sizeof(struct sm501_platdata), GFP_KERNEL);
+ if (plat == NULL)
+ return -ENOMEM;
+ plat->init = kzalloc(sizeof(struct sm501_initdata), GFP_KERNEL);
+ if (plat->init == NULL)
+ goto err;
+
+ if (!of_property_read_string(sm->np, "sm501,devices", &devstr))
+ plat->init->devices = sm501_parse_devices_str(devstr);
+ if (!of_property_read_u32_index(sm->np, "sm501,mclk", 0, &u32_val))
+ plat->init->mclk = u32_val;
+ if (!of_property_read_u32_index(sm->np, "sm501,m1xclk", 0, &u32_val))
+ plat->init->m1xclk = u32_val;
+ sm501_of_read_reg_init(sm, "sm501,misc-timing", &plat->init->misc_timing);
+ sm501_of_read_reg_init(sm, "sm501,misc-control", &plat->init->misc_control);
+ sm501_of_read_reg_init(sm, "sm501,gpio-low", &plat->init->gpio_low);
+ sm501_of_read_reg_init(sm, "sm501,gpio-high", &plat->init->gpio_high);
+
+#ifdef CONFIG_MFD_SM501_GPIO
+ if (plat->init->devices & SM501_USE_GPIO) {
+ if (!of_property_read_u32_index(sm->np, "sm501,num-i2c", 0, &u32_val))
+ plat->gpio_i2c_nr = u32_val;
+ }
+ if (plat->gpio_i2c_nr > 0) {
+ plat->gpio_i2c = kcalloc(plat->gpio_i2c_nr,
+ sizeof(struct sm501_platdata_gpio_i2c),
+ GFP_KERNEL);
+ if (plat->gpio_i2c == NULL)
+ goto err;
+ of_property_read_variable_u32(sm->np, "sm501,gpio-i2c",
+ plat->gpio_i2c,
+ plat->gpio_i2c_nr * 5);
+ }
+#endif
+ sm->platdata = plat;
+ return 0;
+err:
+ kfree(plat->init);
+ kfree(plat);
+ return -ENOMEM;
+}
+#endif
+
static int sm501_plat_probe(struct platform_device *dev)
{
struct sm501_devdata *sm;
@@ -1384,7 +1487,6 @@ static int sm501_plat_probe(struct platform_device *dev)
sm->dev = &dev->dev;
sm->pdev_id = dev->id;
sm->platdata = dev_get_platdata(&dev->dev);
-
ret = platform_get_irq(dev, 0);
if (ret < 0)
goto err_res;
@@ -1406,6 +1508,15 @@ static int sm501_plat_probe(struct platform_device *dev)
goto err_res;
}
+#if defined(CONFIG_OF)
+ if (dev->dev.of_node) {
+ sm->np = dev->dev.of_node;
+ ret = sm501_parse_dt(sm);
+ if (ret)
+ goto err_res;
+ }
+#endif
+
platform_set_drvdata(dev, sm);
sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 09/12] of: FDT vaddr support for SH.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (7 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 08/12] mfd/sm501: Add OF properties Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 10/12] serial/sh-sci: Fix earlyprintk / earlycon Yoshinori Sato
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
sh using virt address in FDT.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/of/fdt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index bf502ba8da95..846df856f258 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -643,6 +643,9 @@ void __init early_init_fdt_scan_reserved_mem(void)
fdt_get_mem_rsv(initial_boot_params, n, &base, &size);
if (!size)
break;
+#ifdef CONFIG_SUPERH
+ base = virt_to_phys(base);
+#endif
memblock_reserve(base, size);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 10/12] serial/sh-sci: Fix earlyprintk / earlycon.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (8 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 09/12] of: FDT vaddr support for SH Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 11/12] sh: target dts Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 12/12] sh: OF defconfig Yoshinori Sato
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
- earlyprintk having fault.
- fix shortname conflict.
- fix SCI regshift in SH4.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
drivers/tty/serial/sh-sci.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 7c9457962a3d..541466b23b45 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2721,7 +2721,7 @@ static int sci_remap_port(struct uart_port *port)
if (port->membase)
return 0;
- if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
+ if ((port->dev && port->dev->of_node) || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size);
if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line);
@@ -3507,6 +3507,10 @@ static int __init early_console_setup(struct earlycon_device *device,
if (!device->port.membase)
return -ENODEV;
+ if (type == PORT_SCI &&
+ (IS_ENABLED(CONFIG_CPU_SH3) || IS_ENABLED(CONFIG_CPU_SH4))) {
+ device->port.regshift = 2;
+ }
device->port.serial_in = sci_serial_in;
device->port.serial_out = sci_serial_out;
device->port.type = type;
@@ -3556,8 +3560,8 @@ static int __init hscif_early_console_setup(struct earlycon_device *device,
OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
-OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
+OF_EARLYCON_DECLARE(rzscif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 11/12] sh: target dts.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (9 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 10/12] serial/sh-sci: Fix earlyprintk / earlycon Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
2023-08-31 16:17 ` Geert Uytterhoeven
2023-08-30 8:42 ` [RFC PATCH 12/12] sh: OF defconfig Yoshinori Sato
11 siblings, 1 reply; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
- rts7751r2dplus - Renesas RTS7751R2D-PLUS board.
- landisk - IO DATA DEVICE LANDISK
- usl-5p - IO DATA DECVICE USL-5P
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/boot/dts/include/dt-bindings | 1 +
arch/sh/boot/dts/landisk.dts | 142 ++++++++++++++++++++++
arch/sh/boot/dts/rts7751r2dplus.dts | 168 +++++++++++++++++++++++++++
arch/sh/boot/dts/usl-5p.dts | 146 +++++++++++++++++++++++
4 files changed, 457 insertions(+)
create mode 120000 arch/sh/boot/dts/include/dt-bindings
create mode 100644 arch/sh/boot/dts/landisk.dts
create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
create mode 100644 arch/sh/boot/dts/usl-5p.dts
diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..08c00e4972fa
--- /dev/null
+++ b/arch/sh/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/sh/boot/dts/landisk.dts b/arch/sh/boot/dts/landisk.dts
new file mode 100644
index 000000000000..0d0a5e44a2d7
--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree source for IO DATA DEVICE LANDISK
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+
+/dts-v1/;
+/ {
+ model = "IO-DATA Device LANDISK";
+ compatible = "iodata,landisk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+ chosen {
+ stdout-path = &sci1;
+ };
+ aliases {
+ serial1 = &sci1;
+ };
+
+ oclk: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+ pllclk: pllclk {
+ compatible = "renesas,sh7750-pll-clock";
+ clocks = <&oclk>;
+ #clock-cells = <0>;
+ sh7750,md = <5>;
+ sh7750,rtype = <1>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
+ iclk: iclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <6>;
+ clock-output-names = "ick";
+ };
+ bclk: bclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <3>;
+ clock-output-names = "bck";
+ };
+ fclk: fclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <0>;
+ clock-output-names = "fck";
+ };
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ clock-frequency = <266666666>;
+ };
+ };
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ };
+ julianintc: julianintc@a4000000 {
+ compatible = "iodata,julian-intc";
+ reg = <0xb0000000 0x08>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ };
+ sci1: serial@ffe80000 {
+ compatible = "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0
+ evt2irq(0x720) 0
+ evt2irq(0x760) 0
+ evt2irq(0x740) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
+ tmu: timer@ffd80008 {
+ compatible = "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0
+ evt2irq(0x420) 0
+ evt2irq(0x440) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ renesas,channels = <0x03>;
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,sh7751-pci", "iodata,julian";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0xfe240000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&julianintc>;
+ eth@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ interrupts = <5 0>;
+ };
+ ata@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ interrupts = <6 0>;
+ };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ interrupts = <7 0>;
+ };
+ usb@2,1 {
+ reg = <0x1100 0 0 0 0>;
+ interrupts = <8 0>;
+ };
+ usb@2,2 {
+ reg = <0x1200 0 0 0 0>;
+ interrupts = <5 0>;
+ };
+ };
+};
diff --git a/arch/sh/boot/dts/rts7751r2dplus.dts b/arch/sh/boot/dts/rts7751r2dplus.dts
new file mode 100644
index 000000000000..1d64753f47a2
--- /dev/null
+++ b/arch/sh/boot/dts/rts7751r2dplus.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree source for Renesas RTS7751R2D Plus
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+
+/dts-v1/;
+/ {
+ model = "Renesas RTS7715R2D Plus";
+ compatible = "renesas,r2dplus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+ chosen {
+ stdout-path = &sci1;
+ };
+ aliases {
+ serial1 = &sci1;
+ };
+
+ oclk: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+ pllclk: pllclk {
+ compatible = "renesas,sh7750-pll-clock";
+ clocks = <&oclk>;
+ #clock-cells = <0>;
+ sh7750,md = <5>;
+ sh7750,rtype = <1>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
+ iclk: iclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <6>;
+ clock-output-names = "ick";
+ };
+ bclk: bclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <3>;
+ clock-output-names = "bck";
+ };
+ fclk: fclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <0>;
+ clock-output-names = "fck";
+ };
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ clock-frequency = <266666666>;
+ };
+ };
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ };
+ r2dintc: r2dintc@a4000000 {
+ compatible = "renesas,rts7751r2d-intc";
+ reg = <0xa4000000 0x3a>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ };
+ sci1: serial@ffe80000 {
+ compatible = "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0
+ evt2irq(0x720) 0
+ evt2irq(0x760) 0
+ evt2irq(0x740) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
+ tmu: timer@ffd80008 {
+ compatible = "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0
+ evt2irq(0x420) 0
+ evt2irq(0x440) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ renesas,channels = <0x03>;
+ };
+
+ display@1,0 {
+ compatible = "smi,sm501";
+ reg = <0x10000000 0x03e00000
+ 0x13e00000 0x00200000>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <4 0>;
+ mode = "640x480-16@60";
+ little-endian;
+ sm501,devices = "usb-host,uart0";
+ };
+ compact-flash@b4001000 {
+ compatible = "ata-generic";
+ reg = <0xb4001000 0x0e>, <0xb400080c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&r2dintc>;
+ interrupts = <1 0>;
+ };
+
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x00000000 0x02000000>;
+ device-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x00000000 0x00040000>;
+ };
+ partition@1 {
+ label = "Environemt";
+ reg = <0x00040000 0x00040000>;
+ };
+ partition@2 {
+ label = "Kernel";
+ reg = <0x00080000 0x001c0000>;
+ };
+ partition@3 {
+ label = "Flash_FS";
+ reg = <0x00240000 0x00dc0000>;
+ };
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,sh7751-pci", "renesas,r2d";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0xfe240000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&r2dintc>;
+ eth@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ interrupts = <3 0>;
+ };
+ };
+};
diff --git a/arch/sh/boot/dts/usl-5p.dts b/arch/sh/boot/dts/usl-5p.dts
new file mode 100644
index 000000000000..3e6624c55c0e
--- /dev/null
+++ b/arch/sh/boot/dts/usl-5p.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree source for IO DATA DEVICE USL-5P
+ *
+ * Copyright 2023 Yoshinori Sato
+ */
+
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+
+/dts-v1/;
+/ {
+ model = "IO-DATA Device USL-5P";
+ compatible = "iodata,usl-5p";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+ chosen {
+ stdout-path = &sci1;
+ };
+ aliases {
+ serial1 = &sci1;
+ };
+
+ oclk: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+ pllclk: pllclk {
+ compatible = "renesas,sh7750-pll-clock";
+ clocks = <&oclk>;
+ #clock-cells = <0>;
+ sh7750,md = <5>;
+ sh7750,rtype = <1>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
+ iclk: iclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <6>;
+ clock-output-names = "ick";
+ };
+ bclk: bclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <3>;
+ clock-output-names = "bck";
+ };
+ fclk: fclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <0>;
+ clock-output-names = "fck";
+ };
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ clock-frequency = <266666666>;
+ };
+ };
+ memory@c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ };
+ julianintc: julianintc@a4000000 {
+ compatible = "iodata,julian-intc";
+ reg = <0xb0000000 0x08>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #interrupt-cells = <2>;
+ };
+ sci1: serial@ffe80000 {
+ compatible = "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0
+ evt2irq(0x720) 0
+ evt2irq(0x760) 0
+ evt2irq(0x740) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
+ tmu: timer@ffd80008 {
+ compatible = "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0
+ evt2irq(0x420) 0
+ evt2irq(0x440) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ renesas,channels = <0x03>;
+ };
+
+ compact-flash@b4001000 {
+ compatible = "ata-generic";
+ reg = <0xb4000040 0x0e>, <0xb400002c 2>;
+ reg-shift = <1>;
+ interrupt-parent = <&julianintc>;
+ interrupts = <10 0>;
+ };
+
+ pci@fe200000 {
+ compatible = "renesas,sh7751-pci", "iodata,julian";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0 0xfd000000 0xfd000000 0 0x01000000>,
+ <0x01000000 0 0xfe240000 0xfe240000 0 0x00040000>;
+ reg = <0xfe200000 0x0400>,
+ <0x0c000000 0x04000000>,
+ <0xff800000 0x0030>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&julianintc>;
+ eth@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ interrupts = <5 0>;
+ };
+ usb@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ interrupts = <7 0>;
+ };
+ usb@2,1 {
+ reg = <0x1100 0 0 0 0>;
+ interrupts = <8 0>;
+ };
+ usb@2,2 {
+ reg = <0x1200 0 0 0 0>;
+ interrupts = <5 0>;
+ };
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [RFC PATCH 12/12] sh: OF defconfig.
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
` (10 preceding siblings ...)
2023-08-30 8:42 ` [RFC PATCH 11/12] sh: target dts Yoshinori Sato
@ 2023-08-30 8:42 ` Yoshinori Sato
11 siblings, 0 replies; 15+ messages in thread
From: Yoshinori Sato @ 2023-08-30 8:42 UTC (permalink / raw)
To: linux-sh; +Cc: Yoshinori Sato
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
arch/sh/configs/landisk-of_defconfig | 161 ++++++++++++++++++++
arch/sh/configs/rts7751r2dplus-of_defconfig | 159 +++++++++++++++++++
2 files changed, 320 insertions(+)
create mode 100644 arch/sh/configs/landisk-of_defconfig
create mode 100644 arch/sh/configs/rts7751r2dplus-of_defconfig
diff --git a/arch/sh/configs/landisk-of_defconfig b/arch/sh/configs/landisk-of_defconfig
new file mode 100644
index 000000000000..0bd96aef77d8
--- /dev/null
+++ b/arch/sh/configs/landisk-of_defconfig
@@ -0,0 +1,161 @@
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_SH_LANDISK_OF=y
+CONFIG_MODULES=y
+CONFIG_SLAB=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_PCI=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ATA=y
+CONFIG_PATA_ATP867X=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_DAVICOM is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FUNGIBLE is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_ADI is not set
+# CONFIG_NET_VENDOR_LITEX is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETERION is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RDC is not set
+CONFIG_8139CP=y
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WANGXUN is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
+# CONFIG_SERIAL_SH_SCI_CONSOLE is not set
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_SCI=y
+CONFIG_MFD_SM501=y
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=m
+CONFIG_FB_SM501=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=m
+CONFIG_SND_YMFPCI=m
+CONFIG_HID_A4TECH=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_R9701=y
+CONFIG_COMMON_CLK_SH7750=y
+CONFIG_EXT2_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_MINIX_FS=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_CRC_T10DIF=y
+CONFIG_DEBUG_INFO_DWARF5=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
diff --git a/arch/sh/configs/rts7751r2dplus-of_defconfig b/arch/sh/configs/rts7751r2dplus-of_defconfig
new file mode 100644
index 000000000000..56b627142205
--- /dev/null
+++ b/arch/sh/configs/rts7751r2dplus-of_defconfig
@@ -0,0 +1,159 @@
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_CPU_SUBTYPE_SH7751R=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_SH_RTS7751R2D_OF=y
+CONFIG_MODULES=y
+CONFIG_SLAB=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+CONFIG_PCI=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_UEVENT_HELPER=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ATA=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_DAVICOM is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_FUNGIBLE is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_ADI is not set
+# CONFIG_NET_VENDOR_LITEX is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETERION is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RDC is not set
+CONFIG_8139CP=y
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WANGXUN is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
+# CONFIG_SERIAL_SH_SCI_CONSOLE is not set
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_SCI=y
+CONFIG_MFD_SM501=y
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=m
+CONFIG_FB_SM501=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_SUPERH_MONO is not set
+# CONFIG_LOGO_SUPERH_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=m
+CONFIG_SND_YMFPCI=m
+CONFIG_HID_A4TECH=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_R9701=y
+CONFIG_COMMON_CLK_SH7750=y
+CONFIG_EXT2_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_MINIX_FS=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_INIT_STACK_NONE=y
+CONFIG_CRC_T10DIF=y
+CONFIG_DEBUG_INFO_DWARF5=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
--
2.39.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [RFC PATCH 11/12] sh: target dts.
2023-08-30 8:42 ` [RFC PATCH 11/12] sh: target dts Yoshinori Sato
@ 2023-08-31 16:17 ` Geert Uytterhoeven
2023-09-01 13:32 ` Geert Uytterhoeven
0 siblings, 1 reply; 15+ messages in thread
From: Geert Uytterhoeven @ 2023-08-31 16:17 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh
Hi Sato-san,
On Wed, Aug 30, 2023 at 8:53 PM Yoshinori Sato
<ysato@users.sourceforge.jp> wrote:
> - rts7751r2dplus - Renesas RTS7751R2D-PLUS board.
> - landisk - IO DATA DEVICE LANDISK
> - usl-5p - IO DATA DECVICE USL-5P
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Thanks for your patch!
> ---
> arch/sh/boot/dts/include/dt-bindings | 1 +
> arch/sh/boot/dts/landisk.dts | 142 ++++++++++++++++++++++
> arch/sh/boot/dts/rts7751r2dplus.dts | 168 +++++++++++++++++++++++++++
> arch/sh/boot/dts/usl-5p.dts | 146 +++++++++++++++++++++++
> 4 files changed, 457 insertions(+)
> create mode 120000 arch/sh/boot/dts/include/dt-bindings
> create mode 100644 arch/sh/boot/dts/landisk.dts
> create mode 100644 arch/sh/boot/dts/rts7751r2dplus.dts
> create mode 100644 arch/sh/boot/dts/usl-5p.dts
>
> diff --git a/arch/sh/boot/dts/include/dt-bindings b/arch/sh/boot/dts/include/dt-bindings
> new file mode 120000
> index 000000000000..08c00e4972fa
> --- /dev/null
> +++ b/arch/sh/boot/dts/include/dt-bindings
> @@ -0,0 +1 @@
> +../../../../../include/dt-bindings
This should not be needed.
> --- /dev/null
> +++ b/arch/sh/boot/dts/landisk.dts
> @@ -0,0 +1,142 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree source for IO DATA DEVICE LANDISK
> + *
> + * Copyright 2023 Yoshinori Sato
> + */
> +
> +#include <dt-bindings/interrupt-controller/sh_intc.h>
You forgot to post commit d00349bf840505a0 ("sh: SH-INTC helper files")
in ysato/sh-of-wip.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC PATCH 11/12] sh: target dts.
2023-08-31 16:17 ` Geert Uytterhoeven
@ 2023-09-01 13:32 ` Geert Uytterhoeven
0 siblings, 0 replies; 15+ messages in thread
From: Geert Uytterhoeven @ 2023-09-01 13:32 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: linux-sh
Hi Sato-san,
On Thu, Aug 31, 2023 at 6:17 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Wed, Aug 30, 2023 at 8:53 PM Yoshinori Sato
> <ysato@users.sourceforge.jp> wrote:
> > --- /dev/null
> > +++ b/arch/sh/boot/dts/landisk.dts
> > @@ -0,0 +1,142 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree source for IO DATA DEVICE LANDISK
> > + *
> > + * Copyright 2023 Yoshinori Sato
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/sh_intc.h>
>
> You forgot to post commit d00349bf840505a0 ("sh: SH-INTC helper files")
> in ysato/sh-of-wip.
And that one needs:
--- a/include/dt-bindings/interrupt-controller/sh_intc.h
+++ b/include/dt-bindings/interrupt-controller/sh_intc.h
@@ -1,2 +1,2 @@
-#define evt2irq(evt) (((evt) >> 5) - 16)
-#define irq2evt(irq) (((irq) + 16) << 5)
+#define evt2irq(evt) (((evt) >> 5))
+#define irq2evt(irq) (((irq)) << 5)
Cfr. commit a8ac2961148e8c72 ("sh: Avoid using IRQ0 on SH3 and SH4") in v6.5.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-09-01 13:32 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-30 8:42 [RFC PATCH 00/12] Device Tree support for SH7751 based board Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 01/12] sh: Add OF target boards Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 02/12] sh: Update OF handling Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 03/12] sh: SH4 OF support Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 04/12] clk: SH7750 / 7751 clk driver Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 05/12] drivers/irqchip: Add SH7751 and boards specific irqchip Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 06/12] drivers/pci: Add SH7751 PCI Host bridge driver Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 07/12] clocksource: Update sh_tmu of handling Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 08/12] mfd/sm501: Add OF properties Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 09/12] of: FDT vaddr support for SH Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 10/12] serial/sh-sci: Fix earlyprintk / earlycon Yoshinori Sato
2023-08-30 8:42 ` [RFC PATCH 11/12] sh: target dts Yoshinori Sato
2023-08-31 16:17 ` Geert Uytterhoeven
2023-09-01 13:32 ` Geert Uytterhoeven
2023-08-30 8:42 ` [RFC PATCH 12/12] sh: OF defconfig Yoshinori Sato
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