* [PATCH v3 01/12] of: add vendor prefix for J-Core
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 13:18 ` Rob Herring
2016-05-25 5:43 ` [PATCH v3 11/12] sh: add defconfig for J-Core J2 Rich Felker
` (11 subsequent siblings)
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
The J-Core project (j-core.org) produces open source cpu and SoC
peripheral cores synthesizable as FPGA bitstreams or ASICs.
Signed-off-by: Rich Felker <dalias@libc.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 86740d4..9c070b8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -126,6 +126,7 @@ invensense InvenSense Inc.
isee ISEE 2007 S.L.
isil Intersil
issi Integrated Silicon Solutions Inc.
+jcore J-Core.org
jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH
keymile Keymile GmbH
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3 01/12] of: add vendor prefix for J-Core
2016-05-25 5:43 ` [PATCH v3 01/12] of: add vendor prefix for J-Core Rich Felker
@ 2016-05-25 13:18 ` Rob Herring
2016-07-27 5:31 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2016-05-25 13:18 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Wed, May 25, 2016 at 12:43 AM, Rich Felker <dalias@libc.org> wrote:
> The J-Core project (j-core.org) produces open source cpu and SoC
> peripheral cores synthesizable as FPGA bitstreams or ASICs.
>
> Signed-off-by: Rich Felker <dalias@libc.org>
Please add acks when posting subsequent versions.
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 86740d4..9c070b8 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -126,6 +126,7 @@ invensense InvenSense Inc.
> isee ISEE 2007 S.L.
> isil Intersil
> issi Integrated Silicon Solutions Inc.
> +jcore J-Core.org
> jedec JEDEC Solid State Technology Association
> karo Ka-Ro electronics GmbH
> keymile Keymile GmbH
> --
> 2.8.1
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 01/12] of: add vendor prefix for J-Core
2016-05-25 13:18 ` Rob Herring
@ 2016-07-27 5:31 ` Rich Felker
2016-08-04 22:27 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-07-27 5:31 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Wed, May 25, 2016 at 08:18:06AM -0500, Rob Herring wrote:
> On Wed, May 25, 2016 at 12:43 AM, Rich Felker <dalias@libc.org> wrote:
> > The J-Core project (j-core.org) produces open source cpu and SoC
> > peripheral cores synthesizable as FPGA bitstreams or ASICs.
> >
> > Signed-off-by: Rich Felker <dalias@libc.org>
>
> Please add acks when posting subsequent versions.
>
> > ---
> > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > index 86740d4..9c070b8 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > @@ -126,6 +126,7 @@ invensense InvenSense Inc.
> > isee ISEE 2007 S.L.
> > isil Intersil
> > issi Integrated Silicon Solutions Inc.
> > +jcore J-Core.org
> > jedec JEDEC Solid State Technology Association
> > karo Ka-Ro electronics GmbH
> > keymile Keymile GmbH
> > --
> > 2.8.1
Since this was previously acked, can I include it in my tree for
upstreaming? Or do you want me to submit the patch again?
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 01/12] of: add vendor prefix for J-Core
2016-07-27 5:31 ` Rich Felker
@ 2016-08-04 22:27 ` Rich Felker
[not found] ` <20160804222757.GO15995-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
0 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-08-04 22:27 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Wed, Jul 27, 2016 at 01:31:12AM -0400, Rich Felker wrote:
> On Wed, May 25, 2016 at 08:18:06AM -0500, Rob Herring wrote:
> > On Wed, May 25, 2016 at 12:43 AM, Rich Felker <dalias@libc.org> wrote:
> > > The J-Core project (j-core.org) produces open source cpu and SoC
> > > peripheral cores synthesizable as FPGA bitstreams or ASICs.
> > >
> > > Signed-off-by: Rich Felker <dalias@libc.org>
> >
> > Please add acks when posting subsequent versions.
> >
> > > ---
> > > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > > index 86740d4..9c070b8 100644
> > > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > > @@ -126,6 +126,7 @@ invensense InvenSense Inc.
> > > isee ISEE 2007 S.L.
> > > isil Intersil
> > > issi Integrated Silicon Solutions Inc.
> > > +jcore J-Core.org
> > > jedec JEDEC Solid State Technology Association
> > > karo Ka-Ro electronics GmbH
> > > keymile Keymile GmbH
> > > --
> > > 2.8.1
>
> Since this was previously acked, can I include it in my tree for
> upstreaming? Or do you want me to submit the patch again?
Ping. Should this go upstream via me or someone else? It doesn't
correspond to any specific driver subsystem.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v3 11/12] sh: add defconfig for J-Core J2
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
2016-05-25 5:43 ` [PATCH v3 01/12] of: add vendor prefix for J-Core Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 5:43 ` [PATCH v3 10/12] spi: add driver for J-Core SPI controller Rich Felker
` (10 subsequent siblings)
12 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: linux-kernel, linux-sh; +Cc: Rich Felker, Yoshinori Sato
This defconfig is intended not to be specific to a particular board;
it enables drivers for all currently-supported hardware, and should be
updated to include additional drivers as they are added.
Signed-off-by: Rich Felker <dalias@libc.org>
---
arch/sh/configs/j2_defconfig | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 arch/sh/configs/j2_defconfig
diff --git a/arch/sh/configs/j2_defconfig b/arch/sh/configs/j2_defconfig
new file mode 100644
index 0000000..fca167f
--- /dev/null
+++ b/arch/sh/configs/j2_defconfig
@@ -0,0 +1,38 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CPU_SUBTYPE_J2=y
+CONFIG_MEMORY_START=0x10000000
+CONFIG_MEMORY_SIZE=0x04000000
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_SH_DEVICE_TREE=y
+CONFIG_HZ_100=y
+CONFIG_CMDLINE_OVERWRITE=y
+CONFIG_CMDLINE="console=ttyUL0 earlycon"
+CONFIG_BINFMT_ELF_FDPIC=y
+CONFIG_BINFMT_FLAT=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_UARTLITE=y
+CONFIG_SERIAL_UARTLITE_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_SPI=y
+CONFIG_SPI_JCORE=y
+CONFIG_WATCHDOG=y
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
+CONFIG_CLKSRC_JCORE_PIT=y
+CONFIG_JCORE_AIC=y
+CONFIG_EXT4_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_UTF8=y
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v3 10/12] spi: add driver for J-Core SPI controller
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
2016-05-25 5:43 ` [PATCH v3 01/12] of: add vendor prefix for J-Core Rich Felker
2016-05-25 5:43 ` [PATCH v3 11/12] sh: add defconfig for J-Core J2 Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 10:17 ` Mark Brown
2016-05-25 5:43 ` [PATCH v3 09/12] clocksource: add J-Core timer/clocksource driver Rich Felker
` (9 subsequent siblings)
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: linux-kernel, linux-sh, linux-spi; +Cc: Mark Brown
The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.
This driver will be extended to support future versions of the J-Core
SPI controller with DMA transfers when they become available.
Signed-off-by: Rich Felker <dalias@libc.org>
---
This version of the SPI patch eliminates USE_MESSAGE_MODE (the open
coding of transfer_one_message logic) and makes severl other minor
changes based on ml discussion of the v2 patch. The chipselect change
has not been made yet, except for rewriting the current logic to be
more clear. If the decision is that it's needed, I can do it easily,
but it needs testing still.
drivers/spi/Kconfig | 4 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-jcore.c | 209 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 214 insertions(+)
create mode 100644 drivers/spi/spi-jcore.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9d8c84b..5bd2ccf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,10 @@ config SPI_IMX
This enables using the Freescale i.MX SPI controllers in master
mode.
+config SPI_JCORE
+ tristate "J-Core SPI Master"
+ depends on OF
+
config SPI_LM70_LLP
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
depends on PARPORT
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fbb255c..6a34124 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
obj-$(CONFIG_SPI_IMX) += spi-imx.o
+obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
diff --git a/drivers/spi/spi-jcore.c b/drivers/spi/spi-jcore.c
new file mode 100644
index 0000000..f239087
--- /dev/null
+++ b/drivers/spi/spi-jcore.c
@@ -0,0 +1,209 @@
+/*
+ * J-Core SPI controller driver
+ *
+ * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
+ *
+ * Current version by Rich Felker
+ * Based loosely on initial version by Oleksandr G Zhadan
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+
+#define DRV_NAME "jcore_spi"
+
+#define MAX_SPI_SPEED 12500000 /* 12.5 MHz */
+
+#define CTRL_REG 0x0
+#define DATA_REG 0x4
+
+#define SPI_NOCHIP_CS 0
+#define SPI_FLASH_CS 1
+#define SPI_CONF_CS 2
+#define SPI_SD_CS 2
+#define SPI_CODEC_CS 3
+
+#define JCORE_SPI_CTRL_XMIT 0x02
+#define JCORE_SPI_STAT_BUSY 0x02
+#define JCORE_SPI_CTRL_LOOP 0x08
+#define JCORE_SPI_CTRL_CS_BITS 0x15
+
+#define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000
+
+struct jcore_spi {
+ struct spi_master *master;
+ void __iomem *base;
+ volatile unsigned int ctrlReg;
+ unsigned int csReg;
+ unsigned int speedReg;
+ unsigned int speed_hz;
+};
+
+static void jcore_spi_wait_till_ready(struct jcore_spi *hw, int timeout)
+{
+ while (timeout--) {
+ hw->ctrlReg = readl(hw->base + CTRL_REG);
+ if (!(hw->ctrlReg & JCORE_SPI_STAT_BUSY))
+ return;
+ cpu_relax();
+ }
+ dev_err(hw->master->dev.parent, "%s: Timeout..\n", __func__);
+}
+
+static void jcore_spi_program(struct jcore_spi *hw)
+{
+ jcore_spi_wait_till_ready(hw, JCORE_SPI_WAIT_RDY_MAX_LOOP);
+ writel(hw->csReg | hw->speedReg, hw->base + CTRL_REG);
+}
+
+static void jcore_spi_chipsel(struct spi_device *spi, bool value)
+{
+ struct jcore_spi *hw = spi_master_get_devdata(spi->master);
+
+ dev_dbg(hw->master->dev.parent, "%s: CS=%d\n", __func__, value);
+
+ hw->csReg = JCORE_SPI_CTRL_CS_BITS ^ (!value << 2*spi->chip_select);
+
+ jcore_spi_program(hw);
+}
+
+static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
+{
+ if (speed = hw->speed_hz) return;
+ hw->speed_hz = speed;
+ hw->speedReg = ((MAX_SPI_SPEED / speed) - 1) << 27;
+ jcore_spi_program(hw);
+ dev_dbg(hw->master->dev.parent, "%s: speed=%d pre=0x%x\n",
+ __func__, speed, hw->speedReg);
+}
+
+static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
+ struct spi_transfer *t)
+{
+ struct jcore_spi *hw = spi_master_get_devdata(master);
+
+ void *ctrl_reg = hw->base + CTRL_REG;
+ void *data_reg = hw->base + DATA_REG;
+ unsigned int timeout;
+ u32 xmit;
+ u32 status;
+
+ /* data buffers */
+ const unsigned char *tx;
+ unsigned char *rx;
+ unsigned int len;
+ unsigned int count;
+
+ jcore_spi_baudrate(hw, t->speed_hz);
+
+ xmit = hw->csReg | hw->speedReg | JCORE_SPI_CTRL_XMIT;
+ tx = t->tx_buf;
+ rx = t->rx_buf;
+ len = t->len;
+
+ for (count = 0; count < len; count++) {
+ timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
+ do {
+ status = readl(ctrl_reg);
+ } while ((status & JCORE_SPI_STAT_BUSY) && --timeout);
+ if (!timeout)
+ break;
+
+ writel(tx ? *tx++ : 0, data_reg);
+ writel(xmit, ctrl_reg);
+
+ timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
+ do {
+ status = readl(ctrl_reg);
+ } while ((status & JCORE_SPI_STAT_BUSY) && --timeout);
+ if (!timeout)
+ break;
+
+ if (rx)
+ *rx++ = readl(data_reg);
+ }
+
+ spi_finalize_current_transfer(master);
+
+ return count<len ? -EREMOTEIO : 0;
+}
+
+static int jcore_spi_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct jcore_spi *hw;
+ struct spi_master *master;
+ struct resource *res;
+ int err = -ENODEV;
+
+ master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));
+ if (!master)
+ return err;
+
+ /* setup the master state. */
+ master->num_chipselect = 3;
+ master->mode_bits = SPI_MODE_3;
+ master->transfer_one = jcore_spi_txrx;
+ master->set_cs = jcore_spi_chipsel;
+ master->dev.of_node = node;
+
+ hw = spi_master_get_devdata(master);
+ hw->master = master;
+ platform_set_drvdata(pdev, hw);
+
+ /* find and map our resources */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ goto exit_busy;
+ if (!devm_request_mem_region
+ (&pdev->dev, res->start, resource_size(res), pdev->name))
+ goto exit_busy;
+ hw->base + devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
+ if (!hw->base)
+ goto exit_busy;
+
+ jcore_spi_baudrate(hw, 400000);
+
+ pdev->dev.dma_mask = 0;
+ /* register our spi controller */
+ err = devm_spi_register_master(&pdev->dev, master);
+ if (err)
+ goto exit;
+ dev_info(&pdev->dev, "base %p, noirq\n", hw->base);
+
+ return 0;
+
+exit_busy:
+ err = -EBUSY;
+exit:
+ platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+ return err;
+}
+
+static const struct of_device_id jcore_spi_of_match[] = {
+ { .compatible = "jcore,spi2" },
+ {},
+};
+
+static struct platform_driver jcore_spi_driver = {
+ .probe = jcore_spi_probe,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = jcore_spi_of_match,
+ },
+};
+
+module_platform_driver(jcore_spi_driver);
+
+MODULE_DESCRIPTION("J-Core SPI driver");
+MODULE_AUTHOR("Rich Felker <dalias@libc.org>");
+MODULE_ALIAS("platform:" DRV_NAME);
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller
2016-05-25 5:43 ` [PATCH v3 10/12] spi: add driver for J-Core SPI controller Rich Felker
@ 2016-05-25 10:17 ` Mark Brown
2016-05-27 1:16 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Mark Brown @ 2016-05-25 10:17 UTC (permalink / raw)
To: Rich Felker; +Cc: linux-kernel, linux-sh, linux-spi
[-- Attachment #1: Type: text/plain, Size: 642 bytes --]
On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> changes based on ml discussion of the v2 patch. The chipselect change
> has not been made yet, except for rewriting the current logic to be
> more clear. If the decision is that it's needed, I can do it easily,
> but it needs testing still.
You need to fix that, it's not good to just decide to ignore review
comments. It is astonishing that you are doing this while expecting to
bypass the normal process for merging things. I'm not going to look at
this version, please ensure you have addressed all the feedback from the
previous review before any new version you submit.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller
2016-05-25 10:17 ` Mark Brown
@ 2016-05-27 1:16 ` Rich Felker
2016-05-27 11:27 ` Mark Brown
0 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-27 1:16 UTC (permalink / raw)
To: Mark Brown; +Cc: linux-kernel, linux-sh, linux-spi
On Wed, May 25, 2016 at 11:17:08AM +0100, Mark Brown wrote:
> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
>
> > changes based on ml discussion of the v2 patch. The chipselect change
> > has not been made yet, except for rewriting the current logic to be
> > more clear. If the decision is that it's needed, I can do it easily,
> > but it needs testing still.
>
> You need to fix that, it's not good to just decide to ignore review
> comments. It is astonishing that you are doing this while expecting to
> bypass the normal process for merging things. I'm not going to look at
> this version, please ensure you have addressed all the feedback from the
> previous review before any new version you submit.
I've made and tested a change that looks like what you want, with the
hw->csReg's chipselect bits set initially high in the probe function,
and only the requested bit being modified by the chipselect function.
Would you prefer I continue to submit this driver with new versions of
the patch series, or separate it out for further review on its own?
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v3 09/12] clocksource: add J-Core timer/clocksource driver
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (2 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 10/12] spi: add driver for J-Core SPI controller Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 5:43 ` [PATCH v3 08/12] irqchip: add J-Core AIC driver Rich Felker
` (8 subsequent siblings)
12 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: linux-kernel, linux-sh; +Cc: Daniel Lezcano, Thomas Gleixner
At the hardware level, the J-Core PIT is integrated with the interrupt
controller, but it is represented as its own device and has an
independent programming interface. It provides a 12-bit countdown
timer, which is not presently used, and a periodic timer. The interval
length for the latter is programmable via a 32-bit throttle register
whose units are determined by a bus-period register. The periodic
timer is used to implement both periodic and oneshot clock event
modes; in oneshot mode the interrupt handler simply disables the timer
as soon as it fires.
Despite its device tree node representing an interrupt for the PIT,
the actual irq generated is programmable, not hard-wired. The driver
is responsible for programming the PIT to generate the hardware irq
number that the DT assigns to it.
On SMP configurations, J-Core provides cpu-local instances of the PIT;
no broadcast timer is needed. This driver supports the creation of the
necessary per-cpu clock_event_device instances. The code has been
tested and works on SMP, but will not be usable without additional
J-Core SMP-support patches and appropriate hardware capable of running
SMP.
A nanosecond-resolution clocksource is provided using the J-Core "RTC"
registers, which give a 64-bit seconds count and 32-bit nanoseconds.
The driver converts these to a 64-bit nanoseconds count.
Signed-off-by: Rich Felker <dalias@libc.org>
---
This driver has undergone significant changes based on feedback from
Daniel Lezcano. I've split out helper functions, eliminated the
repeated percpu offset computations, properly mapped each percpu base,
used container_of instead of static storage for driver data, added
comments for enable_val setup, removed confusing use of "RTC" name,
removed excess includes, used the "jcore_" prefix in naming
identifiers, and made error handling more extensive.
drivers/clocksource/Kconfig | 8 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/jcore-pit.c | 282 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 291 insertions(+)
create mode 100644 drivers/clocksource/jcore-pit.c
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c346be6..7bd39d2 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -297,6 +297,14 @@ config SYS_SUPPORTS_SH_TMU
config SYS_SUPPORTS_EM_STI
bool
+config CLKSRC_JCORE_PIT
+ bool "J-Core PIT timer driver"
+ depends on GENERIC_CLOCKEVENTS
+ depends on HAS_IOMEM
+ help
+ This enables build of clocksource and clockevent driver for
+ the integrated PIT in the J-Core synthesizable, open source SoC.
+
config SH_TIMER_CMT
bool "Renesas CMT timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index dc2b899..d825fcf 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
+obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
diff --git a/drivers/clocksource/jcore-pit.c b/drivers/clocksource/jcore-pit.c
new file mode 100644
index 0000000..dd78fcd
--- /dev/null
+++ b/drivers/clocksource/jcore-pit.c
@@ -0,0 +1,282 @@
+/*
+ * J-Core SoC PIT/clocksource driver
+ *
+ * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/cpu.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define PIT_IRQ_SHIFT 12
+#define PIT_PRIO_SHIFT 20
+#define PIT_ENABLE_SHIFT 26
+#define PIT_IRQ_MASK 0x3f
+#define PIT_PRIO_MASK 0xf
+
+#define REG_PITEN 0x00
+#define REG_THROT 0x10
+#define REG_COUNT 0x14
+#define REG_BUSPD 0x18
+#define REG_SECHI 0x20
+#define REG_SECLO 0x24
+#define REG_NSEC 0x28
+
+struct jcore_clocksource {
+ struct clocksource cs;
+ __iomem void *base;
+};
+
+struct jcore_pit {
+ struct clock_event_device ced;
+ __iomem void *base;
+ unsigned long periodic_delta;
+ unsigned cpu;
+ phys_addr_t paddr;
+ resource_size_t psize;
+ u32 enable_val;
+};
+
+struct jcore_pit_nb {
+ struct notifier_block nb;
+ struct jcore_pit __percpu *pit_percpu;
+};
+
+static cycle_t jcore_clocksource_read(struct clocksource *cs)
+{
+ __iomem void *base + container_of(cs, struct jcore_clocksource, cs)->base;
+ u32 sechi, seclo, nsec, sechi0, seclo0;
+
+ sechi = __raw_readl(base + REG_SECHI);
+ seclo = __raw_readl(base + REG_SECLO);
+ do {
+ sechi0 = sechi;
+ seclo0 = seclo;
+ nsec = __raw_readl(base + REG_NSEC);
+ sechi = __raw_readl(base + REG_SECHI);
+ seclo = __raw_readl(base + REG_SECLO);
+ } while (sechi0 != sechi || seclo0 != seclo);
+
+ return ((u64)sechi << 32 | seclo) * NSEC_PER_SEC + nsec;
+}
+
+static int jcore_pit_disable(struct jcore_pit *pit)
+{
+ __raw_writel(0, pit->base + REG_PITEN);
+ return 0;
+}
+
+static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
+{
+ jcore_pit_disable(pit);
+ __raw_writel(delta, pit->base + REG_THROT);
+ __raw_writel(pit->enable_val, pit->base + REG_PITEN);
+ return 0;
+}
+
+static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
+{
+ struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
+ return jcore_pit_disable(pit);
+}
+
+static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
+{
+ struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
+ return jcore_pit_disable(pit);
+}
+
+static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
+{
+ struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
+ return jcore_pit_set(pit->periodic_delta, pit);
+}
+
+static int jcore_pit_set_next_event(unsigned long delta,
+ struct clock_event_device *ced)
+{
+ struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
+ return jcore_pit_set(delta, pit);
+}
+
+static int jcore_pit_local_init(struct jcore_pit *pit)
+{
+ unsigned buspd;
+
+ pr_info("Local J-Core PIT init on cpu %u\n", pit->cpu);
+
+ pit->base = ioremap(pit->paddr, pit->psize);
+ if (!pit->base)
+ return -ENOMEM;
+
+ buspd = __raw_readl(pit->base + REG_BUSPD);
+ pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ*buspd);
+
+ clockevents_config_and_register(&pit->ced,
+ DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd),
+ 1, 0xffffffff);
+
+ return 0;
+}
+
+static int jcore_pit_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
+{
+ struct jcore_pit_nb *nb = container_of(self, struct jcore_pit_nb, nb);
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_STARTING:
+ jcore_pit_local_init(this_cpu_ptr(nb->pit_percpu));
+ break;
+ }
+ return NOTIFY_OK;
+}
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+ struct jcore_pit *pit = this_cpu_ptr(dev_id);
+
+ if (clockevent_state_oneshot(&pit->ced))
+ jcore_pit_disable(pit);
+
+ pit->ced.event_handler(&pit->ced);
+
+ return IRQ_HANDLED;
+}
+
+static void __init jcore_pit_init(struct device_node *node)
+{
+ int err;
+ __iomem void *pit_base;
+ unsigned pit_irq;
+ u32 percpu_offset = 0;
+ unsigned cpu;
+ struct resource res;
+ struct jcore_pit_nb *nb = 0;
+ struct jcore_clocksource *cs = 0;
+ struct jcore_pit __percpu *pit_percpu = 0;
+ unsigned long hwirq;
+ u32 irqprio, enable_val;
+
+ pit_base = of_iomap(node, 0);
+ if (!pit_base) {
+ pr_err("Error: Cannot map base address for J-Core PIT\n");
+ goto out;
+ }
+
+ pit_irq = irq_of_parse_and_map(node, 0);
+ if (!pit_irq) {
+ pr_err("Error: J-Core PIT has no IRQ\n");
+ goto out;
+ }
+
+ of_address_to_resource(node, 0, &res);
+ of_property_read_u32(node, "cpu-offset", &percpu_offset);
+
+ pr_info("Initializing J-Core PIT at %p IRQ %d\n", pit_base, pit_irq);
+
+ cs = kzalloc(sizeof *cs, GFP_KERNEL);
+ if (!cs) {
+ pr_err("Failed to allocate memory for clocksource\n");
+ goto out;
+ }
+
+ cs->base = pit_base;
+ cs->cs.name = "jcore_pit_cs";
+ cs->cs.rating = 400;
+ cs->cs.read = jcore_clocksource_read;
+ cs->cs.mult = 1;
+ cs->cs.shift = 0;
+ cs->cs.mask = CLOCKSOURCE_MASK(64);
+ cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+
+ err = clocksource_register_hz(&cs->cs, NSEC_PER_SEC);
+ if (err) {
+ pr_err("Error registering clocksource device: %d\n", err);
+ goto out;
+ }
+
+ pit_percpu = alloc_percpu(struct jcore_pit);
+ if (!pit_percpu) {
+ pr_err("Failed to allocate memory for clock event device\n");
+ goto out;
+ }
+
+ for_each_possible_cpu(cpu) {
+ struct jcore_pit *pit = per_cpu_ptr(pit_percpu, cpu);
+
+ pit->ced.name = "jcore_pit";
+ pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
+ | CLOCK_EVT_FEAT_ONESHOT
+ | CLOCK_EVT_FEAT_PERCPU;
+ pit->ced.cpumask = cpumask_of(cpu);
+ pit->ced.rating = 400;
+ pit->ced.irq = pit_irq;
+ pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
+ pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
+ pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
+ pit->ced.set_next_event = jcore_pit_set_next_event;
+
+ pit->paddr = res.start;
+ pit->psize = resource_size(&res);
+ res.start += percpu_offset;
+
+ pit->cpu = cpu;
+ }
+
+ nb = kzalloc(sizeof *nb, GFP_KERNEL);
+ if (!nb) {
+ pr_err("Failed to allocate memory for J-Core PIT notifier\n");
+ goto out;
+ }
+
+ nb->pit_percpu = pit_percpu;
+ nb->nb.notifier_call = jcore_pit_cpu_notify;
+ err = register_cpu_notifier(&nb->nb);
+ if (err) {
+ pr_err("Error registering J-Core PIT notifier: %d\n", err);
+ goto out;
+ }
+
+ err = request_irq(pit_irq, timer_interrupt,
+ IRQF_TIMER | IRQF_PERCPU, "jcore_pit", pit_percpu);
+ if (err) {
+ pr_err("pit irq request failed: %d\n", err);
+ goto out;
+ }
+
+ /* The J-Core PIT is not hard-wired to a particular IRQ, but
+ * integrated with the interrupt controller such that the IRQ it
+ * generates is programmable. The programming interface has a
+ * legacy field which was an interrupt priority for AIC1, but
+ * which is OR'd onto bits 2-5 of the generated IRQ number when
+ * used with J-Core AIC2, so set it to match these bits. */
+ hwirq = irq_get_irq_data(pit_irq)->hwirq;
+ irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
+ enable_val = (1U << PIT_ENABLE_SHIFT)
+ | (hwirq << PIT_IRQ_SHIFT)
+ | (irqprio << PIT_PRIO_SHIFT);
+
+ for_each_possible_cpu(cpu) {
+ struct jcore_pit *pit = per_cpu_ptr(pit_percpu, cpu);
+ pit->enable_val = enable_val;
+ }
+
+ jcore_pit_local_init(this_cpu_ptr(pit_percpu));
+
+ return;
+
+out:
+ pr_err("Could not initialize J-Core PIT driver\n");
+}
+
+CLOCKSOURCE_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (3 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 09/12] clocksource: add J-Core timer/clocksource driver Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-07-15 1:27 ` Rich Felker
` (2 more replies)
2016-05-25 5:43 ` [PATCH v3 03/12] of: add J-Core interrupt controller bindings Rich Felker
` (7 subsequent siblings)
12 siblings, 3 replies; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: linux-kernel, linux-sh; +Cc: Jason Cooper, Marc Zyngier, Thomas Gleixner
There are two versions of the J-Core interrupt controller in use, aic1
which generates interrupts with programmable priorities, but only
supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
and aic2 which uses traps in the range 64-127 and supports up to 128
irqs, with priorities dependent on the interrupt number. The Linux
driver does not make use of priorities anyway.
For simplicity, there is no aic1-specific logic in the driver beyond
setting the priority register, which is necessary for interrupts to
work at all. Eventually aic1 will likely be phased out, but it's
currently in use in deployments and all released bitstream binaries.
Signed-off-by: Rich Felker <dalias@libc.org>
---
This version fixes a missing "static" reported in the previous
version of the patch. I missed Marc Zyngier's reply to the v2 when
preparing the v3 patch series, but I'm still not sure exactly what, if
any, changes should come out of that discussion, and they'll probably
mostly in the area of comments or changelog.
drivers/irqchip/Kconfig | 6 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-jcore-aic.c | 95 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 102 insertions(+)
create mode 100644 drivers/irqchip/irq-jcore-aic.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3e12479..3cb37d6 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -149,6 +149,12 @@ config PIC32_EVIC
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
+config JCORE_AIC
+ bool "J-Core integrated AIC"
+ select IRQ_DOMAIN
+ help
+ Support for the J-Core integrated AIC.
+
config RENESAS_INTC_IRQPIN
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b03cfcb..5a1f1bf 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_I8259) += irq-i8259.o
obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
+obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
new file mode 100644
index 0000000..1348cdb
--- /dev/null
+++ b/drivers/irqchip/irq-jcore-aic.c
@@ -0,0 +1,95 @@
+/*
+ * J-Core SoC AIC driver
+ *
+ * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define AIC1_INTPRI 8
+
+static struct aic_data {
+ unsigned char __iomem *base;
+ u32 cpu_offset;
+ struct irq_chip chip;
+ struct irq_domain *domain;
+ struct notifier_block nb;
+} aic_data;
+
+static int aic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
+{
+ struct aic_data *aic = d->host_data;
+
+ irq_set_chip_data(irq, aic);
+ irq_set_chip_and_handler(irq, &aic->chip, handle_simple_irq);
+ irq_set_probe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops aic_irqdomain_ops = {
+ .map = aic_irqdomain_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+static void noop(struct irq_data *data)
+{
+}
+
+static void aic1_localenable(struct aic_data *aic)
+{
+ unsigned cpu = smp_processor_id();
+ pr_info("Local AIC enable on cpu %u\n", cpu);
+ writel(0xffffffff, aic->base + cpu * aic->cpu_offset + AIC1_INTPRI);
+}
+
+static int aic1_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
+{
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_STARTING:
+ aic1_localenable(container_of(self, struct aic_data, nb));
+ break;
+ }
+ return NOTIFY_OK;
+}
+
+int __init aic_irq_of_init(struct device_node *node, struct device_node *parent)
+{
+ struct aic_data *aic = &aic_data;
+
+ aic->base = of_iomap(node, 0);
+ of_property_read_u32(node, "cpu-offset", &aic->cpu_offset);
+
+ pr_info("Initializing J-Core AIC at %p\n", aic->base);
+
+ if (of_device_is_compatible(node, "jcore,aic1")) {
+ /* For aic1, need to enabled zero-priority-by-default irqs */
+ aic->nb.notifier_call = aic1_cpu_notify;
+ register_cpu_notifier(&aic->nb);
+ aic1_localenable(aic);
+ }
+
+ aic->chip.name = node->name;
+ aic->chip.irq_mask = noop;
+ aic->chip.irq_unmask = noop;
+
+ aic->domain = irq_domain_add_linear(node, 128, &aic_irqdomain_ops, aic);
+ irq_create_strict_mappings(aic->domain, 16, 16, 112);
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
+IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-05-25 5:43 ` [PATCH v3 08/12] irqchip: add J-Core AIC driver Rich Felker
@ 2016-07-15 1:27 ` Rich Felker
2016-07-15 18:19 ` Rich Felker
2016-07-15 15:35 ` Paul Gortmaker
2016-07-15 16:19 ` Jason Cooper
2 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-07-15 1:27 UTC (permalink / raw)
To: linux-kernel, linux-sh
Cc: Jason Cooper, Marc Zyngier, Thomas Gleixner, Daniel Lezcano
On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> There are two versions of the J-Core interrupt controller in use, aic1
> which generates interrupts with programmable priorities, but only
> supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
> and aic2 which uses traps in the range 64-127 and supports up to 128
> irqs, with priorities dependent on the interrupt number. The Linux
> driver does not make use of priorities anyway.
>
> For simplicity, there is no aic1-specific logic in the driver beyond
> setting the priority register, which is necessary for interrupts to
> work at all. Eventually aic1 will likely be phased out, but it's
> currently in use in deployments and all released bitstream binaries.
Any comments on changes I should make in resubmitting this for the 4.8
merge window? I could somewhat restrict the possible irqs, but aic1
allows the pit to be programmed to generate any trap number you want,
despite the hard-wired interrupts being limited to the range 17-24.
It might make sense to do something to allow percpu irq requests, but
I couldn't figure out how to make them work and the current timer
driver (that needs per-cpu irq delivery) just requests its irq through
normal request_irq and lets the hardware do the right thing.
One possible change would be allowing non-identity mapping between
hardware irq numbers (cpu trap numbers) and virqs, but then some
facility for setting up a mapping/dispatch function in do_IRQ is
needed.
Since the driver (and aic device) currently depends to some extent on
SH arch trap numbers and how the SH irq entry point passes them on
(identity mapping), should this driver just go in arch/sh/drivers
rather than drivers/irqchip?
Rich
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
>
> This version fixes a missing "static" reported in the previous
> version of the patch. I missed Marc Zyngier's reply to the v2 when
> preparing the v3 patch series, but I'm still not sure exactly what, if
> any, changes should come out of that discussion, and they'll probably
> mostly in the area of comments or changelog.
>
> drivers/irqchip/Kconfig | 6 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-jcore-aic.c | 95 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 102 insertions(+)
> create mode 100644 drivers/irqchip/irq-jcore-aic.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3e12479..3cb37d6 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -149,6 +149,12 @@ config PIC32_EVIC
> select GENERIC_IRQ_CHIP
> select IRQ_DOMAIN
>
> +config JCORE_AIC
> + bool "J-Core integrated AIC"
> + select IRQ_DOMAIN
> + help
> + Support for the J-Core integrated AIC.
> +
> config RENESAS_INTC_IRQPIN
> bool
> select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b03cfcb..5a1f1bf 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_I8259) += irq-i8259.o
> obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
> obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
> obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
> +obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
> obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
> obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
> obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
> diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
> new file mode 100644
> index 0000000..1348cdb
> --- /dev/null
> +++ b/drivers/irqchip/irq-jcore-aic.c
> @@ -0,0 +1,95 @@
> +/*
> + * J-Core SoC AIC driver
> + *
> + * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. See the file "COPYING" in the main directory of this archive
> + * for more details.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
> +#include <linux/cpu.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#define AIC1_INTPRI 8
> +
> +static struct aic_data {
> + unsigned char __iomem *base;
> + u32 cpu_offset;
> + struct irq_chip chip;
> + struct irq_domain *domain;
> + struct notifier_block nb;
> +} aic_data;
> +
> +static int aic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
> +{
> + struct aic_data *aic = d->host_data;
> +
> + irq_set_chip_data(irq, aic);
> + irq_set_chip_and_handler(irq, &aic->chip, handle_simple_irq);
> + irq_set_probe(irq);
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops aic_irqdomain_ops = {
> + .map = aic_irqdomain_map,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static void noop(struct irq_data *data)
> +{
> +}
> +
> +static void aic1_localenable(struct aic_data *aic)
> +{
> + unsigned cpu = smp_processor_id();
> + pr_info("Local AIC enable on cpu %u\n", cpu);
> + writel(0xffffffff, aic->base + cpu * aic->cpu_offset + AIC1_INTPRI);
> +}
> +
> +static int aic1_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
> +{
> + switch (action & ~CPU_TASKS_FROZEN) {
> + case CPU_STARTING:
> + aic1_localenable(container_of(self, struct aic_data, nb));
> + break;
> + }
> + return NOTIFY_OK;
> +}
> +
> +int __init aic_irq_of_init(struct device_node *node, struct device_node *parent)
> +{
> + struct aic_data *aic = &aic_data;
> +
> + aic->base = of_iomap(node, 0);
> + of_property_read_u32(node, "cpu-offset", &aic->cpu_offset);
> +
> + pr_info("Initializing J-Core AIC at %p\n", aic->base);
> +
> + if (of_device_is_compatible(node, "jcore,aic1")) {
> + /* For aic1, need to enabled zero-priority-by-default irqs */
> + aic->nb.notifier_call = aic1_cpu_notify;
> + register_cpu_notifier(&aic->nb);
> + aic1_localenable(aic);
> + }
> +
> + aic->chip.name = node->name;
> + aic->chip.irq_mask = noop;
> + aic->chip.irq_unmask = noop;
> +
> + aic->domain = irq_domain_add_linear(node, 128, &aic_irqdomain_ops, aic);
> + irq_create_strict_mappings(aic->domain, 16, 16, 112);
> +
> + return 0;
> +}
> +
> +IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
> +IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);
> --
> 2.8.1
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-07-15 1:27 ` Rich Felker
@ 2016-07-15 18:19 ` Rich Felker
0 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-07-15 18:19 UTC (permalink / raw)
To: linux-kernel, linux-sh
Cc: Jason Cooper, Marc Zyngier, Thomas Gleixner, Daniel Lezcano
On Thu, Jul 14, 2016 at 09:27:50PM -0400, Rich Felker wrote:
> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> > There are two versions of the J-Core interrupt controller in use, aic1
> > which generates interrupts with programmable priorities, but only
> > supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
> > and aic2 which uses traps in the range 64-127 and supports up to 128
> > irqs, with priorities dependent on the interrupt number. The Linux
> > driver does not make use of priorities anyway.
> >
> > For simplicity, there is no aic1-specific logic in the driver beyond
> > setting the priority register, which is necessary for interrupts to
> > work at all. Eventually aic1 will likely be phased out, but it's
> > currently in use in deployments and all released bitstream binaries.
>
> Any comments on changes I should make in resubmitting this for the 4.8
> merge window? I could somewhat restrict the possible irqs, but aic1
> allows the pit to be programmed to generate any trap number you want,
> despite the hard-wired interrupts being limited to the range 17-24.
>
> It might make sense to do something to allow percpu irq requests, but
> I couldn't figure out how to make them work and the current timer
> driver (that needs per-cpu irq delivery) just requests its irq through
> normal request_irq and lets the hardware do the right thing.
I've looked into this some more, and the request_percpu_irq system
looks misdesigned and unusable. It requires the IRQ controller driver
to know in advance, before it knows what devices/drivers are connected
to it, whether each irq will be used with a __percpu dev_id, and this
is not a property of the irq controller hardware or the connected
peripheral device hardware, but rather of the _driver_ for the
connected hardware. This is because the irq controller driver must, at
irqdomain mapping time, decide whether to register the handler as
handle_percpu_devid_irq (which interprets dev_id as a __percpu pointer
and remaps it for the local cpu before invoking the driver's handler)
or one of the other handlers that does not perform any percpu
remapping.
The right way for this to work would be for handle_irq_event_percpu to
be responsible for the remapping, but do it conditionally on whether
the irq was requested via request_irq or request_percpu_irq.
In the mean time until this is overhauled correctly, I believe drivers
(in my case, the J-Core timer driver and IPI "driver") should just
call request_irq with the IRQF_PERCPU flag (to ensure the handler runs
on the cpu the irq was received for) and should do their own
this_cpu_ptr(dev_id) as needed.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-05-25 5:43 ` [PATCH v3 08/12] irqchip: add J-Core AIC driver Rich Felker
2016-07-15 1:27 ` Rich Felker
@ 2016-07-15 15:35 ` Paul Gortmaker
2016-07-15 15:41 ` Rich Felker
2016-07-15 16:19 ` Jason Cooper
2 siblings, 1 reply; 52+ messages in thread
From: Paul Gortmaker @ 2016-07-15 15:35 UTC (permalink / raw)
To: Rich Felker; +Cc: LKML, linux-sh, Jason Cooper, Marc Zyngier, Thomas Gleixner
On Wed, May 25, 2016 at 1:43 AM, Rich Felker <dalias@libc.org> wrote:
> There are two versions of the J-Core interrupt controller in use, aic1
> which generates interrupts with programmable priorities, but only
> supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
> and aic2 which uses traps in the range 64-127 and supports up to 128
> irqs, with priorities dependent on the interrupt number. The Linux
> driver does not make use of priorities anyway.
>
> For simplicity, there is no aic1-specific logic in the driver beyond
> setting the priority register, which is necessary for interrupts to
> work at all. Eventually aic1 will likely be phased out, but it's
> currently in use in deployments and all released bitstream binaries.
>
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
>
> This version fixes a missing "static" reported in the previous
> version of the patch. I missed Marc Zyngier's reply to the v2 when
> preparing the v3 patch series, but I'm still not sure exactly what, if
> any, changes should come out of that discussion, and they'll probably
> mostly in the area of comments or changelog.
>
> drivers/irqchip/Kconfig | 6 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-jcore-aic.c | 95 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 102 insertions(+)
> create mode 100644 drivers/irqchip/irq-jcore-aic.c
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3e12479..3cb37d6 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -149,6 +149,12 @@ config PIC32_EVIC
> select GENERIC_IRQ_CHIP
> select IRQ_DOMAIN
>
> +config JCORE_AIC
> + bool "J-Core integrated AIC"
> + select IRQ_DOMAIN
> + help
> + Support for the J-Core integrated AIC.
> +
> config RENESAS_INTC_IRQPIN
> bool
> select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b03cfcb..5a1f1bf 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_I8259) += irq-i8259.o
> obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
> obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
> obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
> +obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
> obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
> obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
> obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
> diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
> new file mode 100644
> index 0000000..1348cdb
> --- /dev/null
> +++ b/drivers/irqchip/irq-jcore-aic.c
> @@ -0,0 +1,95 @@
> +/*
> + * J-Core SoC AIC driver
> + *
> + * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. See the file "COPYING" in the main directory of this archive
> + * for more details.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
Please don't use module.h or MODULE_* in code that is controlled by
a bool Kconfig.
Thanks,
Paul.
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-07-15 15:35 ` Paul Gortmaker
@ 2016-07-15 15:41 ` Rich Felker
0 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-07-15 15:41 UTC (permalink / raw)
To: Paul Gortmaker
Cc: LKML, linux-sh, Jason Cooper, Marc Zyngier, Thomas Gleixner
On Fri, Jul 15, 2016 at 11:35:55AM -0400, Paul Gortmaker wrote:
> > +++ b/drivers/irqchip/irq-jcore-aic.c
> > @@ -0,0 +1,95 @@
> > +/*
> > + * J-Core SoC AIC driver
> > + *
> > + * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
> > + *
> > + * This file is subject to the terms and conditions of the GNU General Public
> > + * License. See the file "COPYING" in the main directory of this archive
> > + * for more details.
> > + */
> > +
> > +#include <linux/irq.h>
> > +#include <linux/io.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/module.h>
>
> Please don't use module.h or MODULE_* in code that is controlled by
> a bool Kconfig.
Thanks for catching this. Fixed.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-05-25 5:43 ` [PATCH v3 08/12] irqchip: add J-Core AIC driver Rich Felker
2016-07-15 1:27 ` Rich Felker
2016-07-15 15:35 ` Paul Gortmaker
@ 2016-07-15 16:19 ` Jason Cooper
2016-07-15 17:02 ` Rich Felker
2 siblings, 1 reply; 52+ messages in thread
From: Jason Cooper @ 2016-07-15 16:19 UTC (permalink / raw)
To: Rich Felker; +Cc: linux-kernel, linux-sh, Marc Zyngier, Thomas Gleixner
Hi Rich,
On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> There are two versions of the J-Core interrupt controller in use, aic1
> which generates interrupts with programmable priorities, but only
> supports 8 irq lines and maps them to cpu traps in the range 17 to 24,
> and aic2 which uses traps in the range 64-127 and supports up to 128
> irqs, with priorities dependent on the interrupt number. The Linux
> driver does not make use of priorities anyway.
>
> For simplicity, there is no aic1-specific logic in the driver beyond
> setting the priority register, which is necessary for interrupts to
> work at all. Eventually aic1 will likely be phased out, but it's
> currently in use in deployments and all released bitstream binaries.
>
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
>
> This version fixes a missing "static" reported in the previous
> version of the patch. I missed Marc Zyngier's reply to the v2 when
> preparing the v3 patch series, but I'm still not sure exactly what, if
> any, changes should come out of that discussion, and they'll probably
> mostly in the area of comments or changelog.
>
> drivers/irqchip/Kconfig | 6 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-jcore-aic.c | 95 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 102 insertions(+)
> create mode 100644 drivers/irqchip/irq-jcore-aic.c
Thanks for the ping, this slipped off my plate while getting back up to
speed... :-/
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3e12479..3cb37d6 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -149,6 +149,12 @@ config PIC32_EVIC
> select GENERIC_IRQ_CHIP
> select IRQ_DOMAIN
>
> +config JCORE_AIC
> + bool "J-Core integrated AIC"
> + select IRQ_DOMAIN
> + help
> + Support for the J-Core integrated AIC.
> +
> config RENESAS_INTC_IRQPIN
> bool
> select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index b03cfcb..5a1f1bf 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_I8259) += irq-i8259.o
> obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
> obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
> obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
> +obj-$(CONFIG_JCORE_AIC) += irq-jcore-aic.o
> obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
> obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
> obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
> diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
> new file mode 100644
> index 0000000..1348cdb
> --- /dev/null
> +++ b/drivers/irqchip/irq-jcore-aic.c
> @@ -0,0 +1,95 @@
> +/*
> + * J-Core SoC AIC driver
> + *
> + * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. See the file "COPYING" in the main directory of this archive
> + * for more details.
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
> +#include <linux/cpu.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#define AIC1_INTPRI 8
> +
> +static struct aic_data {
> + unsigned char __iomem *base;
void __iomem *base;
> + u32 cpu_offset;
> + struct irq_chip chip;
> + struct irq_domain *domain;
> + struct notifier_block nb;
> +} aic_data;
> +
> +static int aic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
> +{
> + struct aic_data *aic = d->host_data;
> +
> + irq_set_chip_data(irq, aic);
> + irq_set_chip_and_handler(irq, &aic->chip, handle_simple_irq);
> + irq_set_probe(irq);
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops aic_irqdomain_ops = {
> + .map = aic_irqdomain_map,
> + .xlate = irq_domain_xlate_onecell,
> +};
> +
> +static void noop(struct irq_data *data)
> +{
> +}
> +
> +static void aic1_localenable(struct aic_data *aic)
> +{
> + unsigned cpu = smp_processor_id();
> + pr_info("Local AIC enable on cpu %u\n", cpu);
> + writel(0xffffffff, aic->base + cpu * aic->cpu_offset + AIC1_INTPRI);
> +}
> +
> +static int aic1_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
> +{
> + switch (action & ~CPU_TASKS_FROZEN) {
> + case CPU_STARTING:
> + aic1_localenable(container_of(self, struct aic_data, nb));
> + break;
> + }
> + return NOTIFY_OK;
> +}
Please take a look at the series posted by Anna-Maria Gleixner for
recent changes to the cpu hp state machine.
https://lkml.kernel.org/r/20160713153333.416260485@linutronix.de
> +
> +int __init aic_irq_of_init(struct device_node *node, struct device_node *parent)
> +{
> + struct aic_data *aic = &aic_data;
> +
> + aic->base = of_iomap(node, 0);
> + of_property_read_u32(node, "cpu-offset", &aic->cpu_offset);
> +
> + pr_info("Initializing J-Core AIC at %p\n", aic->base);
> +
> + if (of_device_is_compatible(node, "jcore,aic1")) {
> + /* For aic1, need to enabled zero-priority-by-default irqs */
> + aic->nb.notifier_call = aic1_cpu_notify;
> + register_cpu_notifier(&aic->nb);
> + aic1_localenable(aic);
> + }
> +
> + aic->chip.name = node->name;
> + aic->chip.irq_mask = noop;
> + aic->chip.irq_unmask = noop;
> +
> + aic->domain = irq_domain_add_linear(node, 128, &aic_irqdomain_ops, aic);
> + irq_create_strict_mappings(aic->domain, 16, 16, 112);
> +
> + return 0;
> +}
> +
> +IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
> +IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);
thx,
Jason.
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 08/12] irqchip: add J-Core AIC driver
2016-07-15 16:19 ` Jason Cooper
@ 2016-07-15 17:02 ` Rich Felker
0 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-07-15 17:02 UTC (permalink / raw)
To: Jason Cooper; +Cc: linux-kernel, linux-sh, Marc Zyngier, Thomas Gleixner
On Fri, Jul 15, 2016 at 04:19:17PM +0000, Jason Cooper wrote:
> > + u32 cpu_offset;
> > + struct irq_chip chip;
> > + struct irq_domain *domain;
> > + struct notifier_block nb;
> > +} aic_data;
> > +
> > +static int aic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
> > +{
> > + struct aic_data *aic = d->host_data;
> > +
> > + irq_set_chip_data(irq, aic);
> > + irq_set_chip_and_handler(irq, &aic->chip, handle_simple_irq);
> > + irq_set_probe(irq);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct irq_domain_ops aic_irqdomain_ops = {
> > + .map = aic_irqdomain_map,
> > + .xlate = irq_domain_xlate_onecell,
> > +};
> > +
> > +static void noop(struct irq_data *data)
> > +{
> > +}
> > +
> > +static void aic1_localenable(struct aic_data *aic)
> > +{
> > + unsigned cpu = smp_processor_id();
> > + pr_info("Local AIC enable on cpu %u\n", cpu);
> > + writel(0xffffffff, aic->base + cpu * aic->cpu_offset + AIC1_INTPRI);
> > +}
> > +
> > +static int aic1_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
> > +{
> > + switch (action & ~CPU_TASKS_FROZEN) {
> > + case CPU_STARTING:
> > + aic1_localenable(container_of(self, struct aic_data, nb));
> > + break;
> > + }
> > + return NOTIFY_OK;
> > +}
>
> Please take a look at the series posted by Anna-Maria Gleixner for
> recent changes to the cpu hp state machine.
>
> https://lkml.kernel.org/r/20160713153333.416260485@linutronix.de
I saw this but was utterly confused about what's going on. Is the
general notifier system that doesn't need to be aware of specific
devices actually being replaced by a huge enum table of all possible
devices that need special treatment as cpu starting/dying?? Or do I
misunderstand what's going on?
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v3 03/12] of: add J-Core interrupt controller bindings
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (4 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 08/12] irqchip: add J-Core AIC driver Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 10:25 ` Mark Rutland
2016-05-25 5:43 ` [PATCH v3 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
` (6 subsequent siblings)
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Jason Cooper, Kumar Gala, Marc Zyngier,
Mark Rutland, Pawel Moll, Rob Herring, Thomas Gleixner
Signed-off-by: Rich Felker <dalias@libc.org>
---
.../bindings/interrupt-controller/jcore,aic.txt | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
new file mode 100644
index 0000000..5dc99b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -0,0 +1,29 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
+ with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+ the "aic2" core with 64 interrupts.
+
+- reg : Memory region for configuration.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+Optional properties:
+
+- cpu-offset : For SMP, the offset to the per-cpu memory region for
+ configuration, to be scaled by the cpu number.
+
+
+Example:
+
+aic: interrupt-controller@200 {
+ compatible = "jcore,aic2";
+ reg = < 0x200 0x10 >;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3 03/12] of: add J-Core interrupt controller bindings
2016-05-25 5:43 ` [PATCH v3 03/12] of: add J-Core interrupt controller bindings Rich Felker
@ 2016-05-25 10:25 ` Mark Rutland
2016-05-25 23:08 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Mark Rutland @ 2016-05-25 10:25 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Jason Cooper,
Kumar Gala, Marc Zyngier, Pawel Moll, Rob Herring,
Thomas Gleixner
On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> .../bindings/interrupt-controller/jcore,aic.txt | 29 ++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 0000000..5dc99b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,29 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> + the "aic2" core with 64 interrupts.
> +
> +- reg : Memory region for configuration.
> +
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 1.
> +
> +Optional properties:
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> + configuration, to be scaled by the cpu number.
I take is that "cpu number" means the "sequential, zero-based hardware
cpu id" defined in patch 2. I would recommend that you explicitly
mention that (e.g. here say "hardware cpu id" rather than "cpu number"),
so as to not have this confused with Linux logical IDs.
Thanks,
Mark.
> +
> +
> +Example:
> +
> +aic: interrupt-controller@200 {
> + compatible = "jcore,aic2";
> + reg = < 0x200 0x10 >;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +};
> --
> 2.8.1
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 03/12] of: add J-Core interrupt controller bindings
2016-05-25 10:25 ` Mark Rutland
@ 2016-05-25 23:08 ` Rich Felker
0 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-05-25 23:08 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Jason Cooper,
Kumar Gala, Marc Zyngier, Pawel Moll, Rob Herring,
Thomas Gleixner
On Wed, May 25, 2016 at 11:25:04AM +0100, Mark Rutland wrote:
> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> > Signed-off-by: Rich Felker <dalias@libc.org>
> > ---
> > .../bindings/interrupt-controller/jcore,aic.txt | 29 ++++++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 0000000..5dc99b9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,29 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> > + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > + the "aic2" core with 64 interrupts.
> > +
> > +- reg : Memory region for configuration.
> > +
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells : Specifies the number of cells needed to encode an
> > + interrupt source. The value shall be 1.
> > +
> > +Optional properties:
> > +
> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> > + configuration, to be scaled by the cpu number.
>
> I take is that "cpu number" means the "sequential, zero-based hardware
> cpu id" defined in patch 2. I would recommend that you explicitly
> mention that (e.g. here say "hardware cpu id" rather than "cpu number"),
> so as to not have this confused with Linux logical IDs.
OK. The current arch/sh SMP framework only has nominal support for hw
cpuid != logical cpuid; it's not actually used/usable right now. But
the DT binding spec should be clear on this anyway.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v3 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (5 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 03/12] of: add J-Core interrupt controller bindings Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
[not found] ` <3d6f6fd6d674942a6446b0a14d9877017c53eb2f.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-25 5:43 ` [PATCH v3 07/12] sh: add AT_HWCAP flag for J-Core cas.l instruction Rich Felker
` (5 subsequent siblings)
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rich Felker,
Rob Herring, Yoshinori Sato
Signed-off-by: Rich Felker <dalias@libc.org>
---
arch/sh/boot/dts/j2_mimas_v2.dts | 87 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100755 arch/sh/boot/dts/j2_mimas_v2.dts
diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts
new file mode 100755
index 0000000..4a66cda
--- /dev/null
+++ b/arch/sh/boot/dts/j2_mimas_v2.dts
@@ -0,0 +1,87 @@
+/dts-v1/;
+
+/ {
+ compatible = "jcore,j2-soc";
+ model = "J2 FPGA SoC on Mimas v2 board";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&aic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "jcore,j2";
+ reg = < 0 >;
+ clock-frequency = < 50000000 >;
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = < 0x10000000 0x4000000 >;
+ };
+
+ chosen {
+ stdout-path = "/soc@abcd0000/serial@100";
+ };
+
+ soc@abcd0000 {
+ compatible = "simple-bus";
+ ranges = <0 0xabcd0000 0x100000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aic: interrupt-controller@200 {
+ compatible = "jcore,aic1";
+ reg = < 0x200 0x10 >;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ cache-controller@c0 {
+ compatible = "jcore,cache";
+ reg = < 0xc0 4 >;
+ };
+
+ timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 >;
+ interrupts = < 0x48 >;
+ };
+
+ spi@40 {
+ compatible = "jcore,spi2";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi-max-frequency = <12500000>;
+
+ reg = < 0x40 0x8 >;
+
+ sdcard@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <12500000>;
+ voltage-ranges = <3200 3400>;
+ mode = <0>;
+ };
+ };
+
+ serial@100 {
+ clock-frequency = <125000000>;
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ current-speed = <19200>;
+ device_type = "serial";
+ interrupts = < 0x12 >;
+ port-number = <0>;
+ reg = < 0x100 0x10 >;
+ };
+ };
+};
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v3 07/12] sh: add AT_HWCAP flag for J-Core cas.l instruction
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (6 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 5:43 ` [PATCH v3 06/12] sh: add support for J-Core J2 processor Rich Felker
` (4 subsequent siblings)
12 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: linux-kernel, linux-sh; +Cc: Rich Felker, Yoshinori Sato
Signed-off-by: Rich Felker <dalias@libc.org>
---
arch/sh/include/uapi/asm/cpu-features.h | 1 +
arch/sh/kernel/cpu/sh2/probe.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/sh/include/uapi/asm/cpu-features.h b/arch/sh/include/uapi/asm/cpu-features.h
index 694abe4..2f1bc85 100644
--- a/arch/sh/include/uapi/asm/cpu-features.h
+++ b/arch/sh/include/uapi/asm/cpu-features.h
@@ -22,5 +22,6 @@
#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
+#define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */
#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 3dd8187..665fcfb 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -54,6 +54,8 @@ void __ref cpu_probe(void)
boot_cpu_data.dcache.entry_shift = 5;
boot_cpu_data.dcache.linesz = 32;
boot_cpu_data.dcache.flags = 0;
+
+ boot_cpu_data.flags |= CPU_HAS_CAS_L;
#else
/*
* SH-2 doesn't have separate caches
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v3 06/12] sh: add support for J-Core J2 processor
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (7 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 07/12] sh: add AT_HWCAP flag for J-Core cas.l instruction Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 5:43 ` [PATCH v3 04/12] of: add J-Core timer bindings Rich Felker
` (3 subsequent siblings)
12 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: linux-kernel, linux-sh; +Cc: Rich Felker, Yoshinori Sato
At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.
Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.
No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.
Signed-off-by: Rich Felker <dalias@libc.org>
---
Aside from adding commit message, this version of patch #6 in the
series only makes minor changes: spelling out SEI's name in a
copyright comment, and moving one asm insn that was placed on the
wrong side of an #ifdef (harmless but wrong).
arch/sh/Kconfig | 8 ++++++
arch/sh/Makefile | 1 +
arch/sh/include/asm/processor.h | 2 +-
arch/sh/kernel/cpu/init.c | 2 +-
arch/sh/kernel/cpu/proc.c | 1 +
arch/sh/kernel/cpu/sh2/entry.S | 5 ++++
arch/sh/kernel/cpu/sh2/probe.c | 34 +++++++++++++++++++++++-
arch/sh/mm/Makefile | 3 ++-
arch/sh/mm/cache-j2.c | 58 +++++++++++++++++++++++++++++++++++++++++
arch/sh/mm/cache.c | 6 ++++-
10 files changed, 115 insertions(+), 5 deletions(-)
create mode 100644 arch/sh/mm/cache-j2.c
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 4fa5894..efb0af4 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -182,6 +182,10 @@ config CPU_SH2A
select CPU_SH2
select UNCACHED_MAPPING
+config CPU_J2
+ bool
+ select CPU_SH2
+
config CPU_SH3
bool
select CPU_HAS_INTEVT
@@ -248,6 +252,10 @@ config CPU_SUBTYPE_SH7619
select CPU_SH2
select SYS_SUPPORTS_SH_CMT
+config CPU_SUBTYPE_J2
+ bool "Support J2 processor"
+ select CPU_J2
+
# SH-2A Processor Support
config CPU_SUBTYPE_SH7201
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 3b2c8b4..0047666 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -31,6 +31,7 @@ isa-y := $(isa-y)-up
endif
cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
+cflags-$(CONFIG_CPU_J2) := $(call cc-option,-mj2,)
cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \
$(call cc-option,-m2a-nofpu,) \
$(call cc-option,-m4-nofpu,)
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1506897..f9a0994 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -15,7 +15,7 @@
*/
enum cpu_type {
/* SH-2 types */
- CPU_SH7619,
+ CPU_SH7619, CPU_J2,
/* SH-2A types */
CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index bfd9e27..c8b3be1 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -106,7 +106,7 @@ void __attribute__ ((weak)) l2_cache_init(void)
/*
* Generic first-level cache init
*/
-#ifdef CONFIG_SUPERH32
+#if defined(CONFIG_SUPERH32) && !defined(CONFIG_CPU_J2)
static void cache_init(void)
{
unsigned long ccr, flags;
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
index 9e6624c..4df4b28 100644
--- a/arch/sh/kernel/cpu/proc.c
+++ b/arch/sh/kernel/cpu/proc.c
@@ -27,6 +27,7 @@ static const char *cpu_name[] = {
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
[CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
[CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
+ [CPU_J2] = "J2",
[CPU_SH_NONE] = "Unknown"
};
diff --git a/arch/sh/kernel/cpu/sh2/entry.S b/arch/sh/kernel/cpu/sh2/entry.S
index a150595..16bde0e 100644
--- a/arch/sh/kernel/cpu/sh2/entry.S
+++ b/arch/sh/kernel/cpu/sh2/entry.S
@@ -147,6 +147,11 @@ ENTRY(exception_handler)
mov #31,r8
cmp/hs r8,r9
bt trap_entry ! 64 > vec >= 31 is trap
+#ifdef CONFIG_CPU_J2
+ mov #16,r8
+ cmp/hs r8,r9
+ bt interrupt_entry ! 31 > vec >= 16 is interrupt
+#endif
mov.l 4f,r8
mov r9,r4
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 6c687ae..3dd8187 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -10,10 +10,27 @@
* for more details.
*/
#include <linux/init.h>
+#include <linux/of_fdt.h>
+#include <linux/smp.h>
+#include <linux/io.h>
#include <asm/processor.h>
#include <asm/cache.h>
-void cpu_probe(void)
+#if defined(CONFIG_CPU_J2)
+extern u32 j2_ccr_base;
+static int __init scan_cache(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ if (!of_flat_dt_is_compatible(node, "jcore,cache"))
+ return 0;
+
+ j2_ccr_base = of_flat_dt_translate_address(node);
+
+ return 1;
+}
+#endif
+
+void __ref cpu_probe(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
boot_cpu_data.type = CPU_SH7619;
@@ -24,10 +41,25 @@ void cpu_probe(void)
boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
boot_cpu_data.dcache.flags = 0;
#endif
+
+#if defined(CONFIG_CPU_J2)
+ unsigned cpu = hard_smp_processor_id();
+ if (cpu = 0) of_scan_flat_dt(scan_cache, NULL);
+ if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
+ if (cpu != 0) return;
+ boot_cpu_data.type = CPU_J2;
+ /* FIXME: cache properties should come from device tree. */
+ boot_cpu_data.dcache.ways = 1;
+ boot_cpu_data.dcache.sets = 256;
+ boot_cpu_data.dcache.entry_shift = 5;
+ boot_cpu_data.dcache.linesz = 32;
+ boot_cpu_data.dcache.flags = 0;
+#else
/*
* SH-2 doesn't have separate caches
*/
boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+#endif
boot_cpu_data.icache = boot_cpu_data.dcache;
boot_cpu_data.family = CPU_FAMILY_SH2;
}
diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile
index cee6b99..92c3bd9 100644
--- a/arch/sh/mm/Makefile
+++ b/arch/sh/mm/Makefile
@@ -4,7 +4,8 @@
obj-y := alignment.o cache.o init.o consistent.o mmap.o
-cacheops-$(CONFIG_CPU_SH2) := cache-sh2.o
+cacheops-$(CONFIG_CPU_J2) := cache-j2.o
+cacheops-$(CONFIG_CPU_SUBTYPE_SH7619) := cache-sh2.o
cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o
cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o
cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o
diff --git a/arch/sh/mm/cache-j2.c b/arch/sh/mm/cache-j2.c
new file mode 100644
index 0000000..11eb8d9
--- /dev/null
+++ b/arch/sh/mm/cache-j2.c
@@ -0,0 +1,58 @@
+/*
+ * arch/sh/mm/cache-j2.c
+ *
+ * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/cpumask.h>
+
+#include <asm/cache.h>
+#include <asm/addrspace.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+
+u32 j2_ccr_base;
+
+static void j2_flush_icache(void *args)
+{
+ unsigned cpu;
+ for_each_possible_cpu(cpu)
+ __raw_writel(0x80000103, j2_ccr_base + 4*cpu);
+}
+
+static void j2_flush_dcache(void *args)
+{
+ unsigned cpu;
+ for_each_possible_cpu(cpu)
+ __raw_writel(0x80000203, j2_ccr_base + 4*cpu);
+}
+
+static void j2_flush_both(void *args)
+{
+ unsigned cpu;
+ for_each_possible_cpu(cpu)
+ __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
+}
+
+void __init j2_cache_init(void)
+{
+ if (!j2_ccr_base)
+ return;
+
+ local_flush_cache_all = j2_flush_both;
+ local_flush_cache_mm = j2_flush_both;
+ local_flush_cache_dup_mm = j2_flush_both;
+ local_flush_cache_page = j2_flush_both;
+ local_flush_cache_range = j2_flush_both;
+ local_flush_dcache_page = j2_flush_dcache;
+ local_flush_icache_range = j2_flush_icache;
+ local_flush_icache_page = j2_flush_icache;
+ local_flush_cache_sigtramp = j2_flush_icache;
+
+ pr_info("Initial J2 CCR is %.8x\n", __raw_readl(j2_ccr_base));
+}
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index 776d664..70cc52f 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -309,7 +309,11 @@ void __init cpu_cache_init(void)
if (unlikely(cache_disabled))
goto skip;
- if (boot_cpu_data.family = CPU_FAMILY_SH2) {
+ if (boot_cpu_data.type = CPU_J2) {
+ extern void __weak j2_cache_init(void);
+
+ j2_cache_init();
+ } else if (boot_cpu_data.family = CPU_FAMILY_SH2) {
extern void __weak sh2_cache_init(void);
sh2_cache_init();
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v3 04/12] of: add J-Core timer bindings
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (8 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 06/12] sh: add support for J-Core J2 processor Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-06-01 13:58 ` Rob Herring
2016-05-25 5:43 ` [PATCH v3 02/12] of: add J-Core cpu bindings Rich Felker
` (2 subsequent siblings)
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
Signed-off-by: Rich Felker <dalias@libc.org>
---
.../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
new file mode 100644
index 0000000..96c6815
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
@@ -0,0 +1,28 @@
+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region for timer/clocksource registers.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+Optional properties:
+
+- cpu-offset: For SMP, the per-cpu offset to the local timer
+ programming memory range.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 >;
+ cpu-offset = < 0x300 >;
+ interrupts = < 0x48 >;
+};
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-05-25 5:43 ` [PATCH v3 04/12] of: add J-Core timer bindings Rich Felker
@ 2016-06-01 13:58 ` Rob Herring
2016-06-01 17:53 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2016-06-01 13:58 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
>
> diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> new file mode 100644
> index 0000000..96c6815
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> @@ -0,0 +1,28 @@
> +J-Core Programmable Interval Timer and Clocksource
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,pit".
> +
> +- reg: Memory region for timer/clocksource registers.
> +
> +- interrupts: An interrupt to assign for the timer. The actual pit
> + core is integrated with the aic and allows the timer interrupt
> + assignment to be programmed by software, but this property is
> + required in order to reserve an interrupt number that doesn't
> + conflict with other devices.
> +
> +Optional properties:
> +
> +- cpu-offset: For SMP, the per-cpu offset to the local timer
> + programming memory range.
> +
> +
> +Example:
> +
> +timer@200 {
> + compatible = "jcore,pit";
> + reg = < 0x200 0x30 >;
> + cpu-offset = < 0x300 >;
This is outside the reg range. Perhaps reg should include each range of
per cpu registers.
Rob
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-01 13:58 ` Rob Herring
@ 2016-06-01 17:53 ` Rich Felker
2016-06-01 21:53 ` Rich Felker
2016-06-01 22:36 ` Rob Herring
0 siblings, 2 replies; 52+ messages in thread
From: Rich Felker @ 2016-06-01 17:53 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Wed, Jun 01, 2016 at 08:58:52AM -0500, Rob Herring wrote:
> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> > Signed-off-by: Rich Felker <dalias@libc.org>
> > ---
> > .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
> >
> > diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> > new file mode 100644
> > index 0000000..96c6815
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> > @@ -0,0 +1,28 @@
> > +J-Core Programmable Interval Timer and Clocksource
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "jcore,pit".
> > +
> > +- reg: Memory region for timer/clocksource registers.
> > +
> > +- interrupts: An interrupt to assign for the timer. The actual pit
> > + core is integrated with the aic and allows the timer interrupt
> > + assignment to be programmed by software, but this property is
> > + required in order to reserve an interrupt number that doesn't
> > + conflict with other devices.
> > +
> > +Optional properties:
> > +
> > +- cpu-offset: For SMP, the per-cpu offset to the local timer
> > + programming memory range.
> > +
> > +
> > +Example:
> > +
> > +timer@200 {
> > + compatible = "jcore,pit";
> > + reg = < 0x200 0x30 >;
> > + cpu-offset = < 0x300 >;
>
> This is outside the reg range. Perhaps reg should include each range of
> per cpu registers.
In the hardware, each timer instance is mapped independently so
there's no fundamental reason they need to be mapped sufficiently
close that it would make sense for a single virtual mapping to cover
them all. This doesn't matter for nommu but it would with mmu in the
future. In the driver I've updated it to ioremap each percpu instance
separately (as its own memory range) using the cpu-offset applied to
the range obtained from "reg". Is this acceptable (in which case I
suppose the binding needs to be documented that "reg" just covers the
cpu0 instance's range)? Do you think it would be preferable to have
multiple "reg" ranges indexed by cpu instead of cpu-offset?
In theory it would even be possible to just require a DT node per
cpulocal timer, but I didn't see a good way to make the bindings
represent the relationship to cpus or to make the driver handle irqs
correctly for such a setup, so I'd need a viable proposal for how that
could be done to even consider such an approach.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-01 17:53 ` Rich Felker
@ 2016-06-01 21:53 ` Rich Felker
2016-06-01 22:36 ` Rob Herring
1 sibling, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-06-01 21:53 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Wed, Jun 01, 2016 at 01:53:07PM -0400, Rich Felker wrote:
> On Wed, Jun 01, 2016 at 08:58:52AM -0500, Rob Herring wrote:
> > On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> > > Signed-off-by: Rich Felker <dalias@libc.org>
> > > ---
> > > .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
> > > 1 file changed, 28 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> > > new file mode 100644
> > > index 0000000..96c6815
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> > > @@ -0,0 +1,28 @@
> > > +J-Core Programmable Interval Timer and Clocksource
> > > +
> > > +Required properties:
> > > +
> > > +- compatible: Must be "jcore,pit".
> > > +
> > > +- reg: Memory region for timer/clocksource registers.
> > > +
> > > +- interrupts: An interrupt to assign for the timer. The actual pit
> > > + core is integrated with the aic and allows the timer interrupt
> > > + assignment to be programmed by software, but this property is
> > > + required in order to reserve an interrupt number that doesn't
> > > + conflict with other devices.
> > > +
> > > +Optional properties:
> > > +
> > > +- cpu-offset: For SMP, the per-cpu offset to the local timer
> > > + programming memory range.
> > > +
> > > +
> > > +Example:
> > > +
> > > +timer@200 {
> > > + compatible = "jcore,pit";
> > > + reg = < 0x200 0x30 >;
> > > + cpu-offset = < 0x300 >;
> >
> > This is outside the reg range. Perhaps reg should include each range of
> > per cpu registers.
>
> In the hardware, each timer instance is mapped independently so
> there's no fundamental reason they need to be mapped sufficiently
> close that it would make sense for a single virtual mapping to cover
> them all. This doesn't matter for nommu but it would with mmu in the
> future. In the driver I've updated it to ioremap each percpu instance
> separately (as its own memory range) using the cpu-offset applied to
> the range obtained from "reg". Is this acceptable (in which case I
> suppose the binding needs to be documented that "reg" just covers the
> cpu0 instance's range)? Do you think it would be preferable to have
> multiple "reg" ranges indexed by cpu instead of cpu-offset?
>
> In theory it would even be possible to just require a DT node per
> cpulocal timer, but I didn't see a good way to make the bindings
> represent the relationship to cpus or to make the driver handle irqs
> correctly for such a setup, so I'd need a viable proposal for how that
> could be done to even consider such an approach.
As a bit more background: the current mappings at 0xabcd0200 and
0xabcd0500 seem to have been chosen to maintain address-level
compatibility with existing non-smp builds (0xabcd0200) while avoiding
stepping on unrelated nearby mmio ranges -- uarts 1 and 2 were at
0xabcd0300 and 0xabcd0400 on systems with multiple uarts. Eventually
these can all be moved arbitrarily and put in a more logical
arrangement once everything is using device tree, but for the time
being, compatibility with non-DT kernels is still needed.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-01 17:53 ` Rich Felker
2016-06-01 21:53 ` Rich Felker
@ 2016-06-01 22:36 ` Rob Herring
2016-06-02 1:34 ` Rich Felker
1 sibling, 1 reply; 52+ messages in thread
From: Rob Herring @ 2016-06-01 22:36 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Wed, Jun 1, 2016 at 12:53 PM, Rich Felker <dalias@libc.org> wrote:
> On Wed, Jun 01, 2016 at 08:58:52AM -0500, Rob Herring wrote:
>> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
>> > Signed-off-by: Rich Felker <dalias@libc.org>
>> > ---
>> > .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
>> > 1 file changed, 28 insertions(+)
>> > create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
>> > new file mode 100644
>> > index 0000000..96c6815
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
>> > @@ -0,0 +1,28 @@
>> > +J-Core Programmable Interval Timer and Clocksource
>> > +
>> > +Required properties:
>> > +
>> > +- compatible: Must be "jcore,pit".
>> > +
>> > +- reg: Memory region for timer/clocksource registers.
>> > +
>> > +- interrupts: An interrupt to assign for the timer. The actual pit
>> > + core is integrated with the aic and allows the timer interrupt
>> > + assignment to be programmed by software, but this property is
>> > + required in order to reserve an interrupt number that doesn't
>> > + conflict with other devices.
>> > +
>> > +Optional properties:
>> > +
>> > +- cpu-offset: For SMP, the per-cpu offset to the local timer
>> > + programming memory range.
>> > +
>> > +
>> > +Example:
>> > +
>> > +timer@200 {
>> > + compatible = "jcore,pit";
>> > + reg = < 0x200 0x30 >;
>> > + cpu-offset = < 0x300 >;
>>
>> This is outside the reg range. Perhaps reg should include each range of
>> per cpu registers.
>
> In the hardware, each timer instance is mapped independently so
> there's no fundamental reason they need to be mapped sufficiently
> close that it would make sense for a single virtual mapping to cover
> them all. This doesn't matter for nommu but it would with mmu in the
> future. In the driver I've updated it to ioremap each percpu instance
> separately (as its own memory range) using the cpu-offset applied to
> the range obtained from "reg". Is this acceptable (in which case I
> suppose the binding needs to be documented that "reg" just covers the
> cpu0 instance's range)? Do you think it would be preferable to have
> multiple "reg" ranges indexed by cpu instead of cpu-offset?
Yes. Either reg should cover the full range of addresses or you should
have multiple reg values with one for each cpu. I prefer the latter as
it doesn't create a custom property for expressing register addresses.
> In theory it would even be possible to just require a DT node per
> cpulocal timer, but I didn't see a good way to make the bindings
> represent the relationship to cpus or to make the driver handle irqs
> correctly for such a setup, so I'd need a viable proposal for how that
> could be done to even consider such an approach.
Yeah, there's not really a standard way to map per cpu blocks to cpus.
We could, but doesn't really seem necessary here.
For the irqs, percpu irqs doesn't help you?
Rob
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-01 22:36 ` Rob Herring
@ 2016-06-02 1:34 ` Rich Felker
2016-06-02 22:44 ` Rob Herring
0 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-06-02 1:34 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Wed, Jun 01, 2016 at 05:36:19PM -0500, Rob Herring wrote:
> On Wed, Jun 1, 2016 at 12:53 PM, Rich Felker <dalias@libc.org> wrote:
> > On Wed, Jun 01, 2016 at 08:58:52AM -0500, Rob Herring wrote:
> >> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> >> > Signed-off-by: Rich Felker <dalias@libc.org>
> >> > ---
> >> > .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
> >> > 1 file changed, 28 insertions(+)
> >> > create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> >> > new file mode 100644
> >> > index 0000000..96c6815
> >> > --- /dev/null
> >> > +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> >> > @@ -0,0 +1,28 @@
> >> > +J-Core Programmable Interval Timer and Clocksource
> >> > +
> >> > +Required properties:
> >> > +
> >> > +- compatible: Must be "jcore,pit".
> >> > +
> >> > +- reg: Memory region for timer/clocksource registers.
> >> > +
> >> > +- interrupts: An interrupt to assign for the timer. The actual pit
> >> > + core is integrated with the aic and allows the timer interrupt
> >> > + assignment to be programmed by software, but this property is
> >> > + required in order to reserve an interrupt number that doesn't
> >> > + conflict with other devices.
> >> > +
> >> > +Optional properties:
> >> > +
> >> > +- cpu-offset: For SMP, the per-cpu offset to the local timer
> >> > + programming memory range.
> >> > +
> >> > +
> >> > +Example:
> >> > +
> >> > +timer@200 {
> >> > + compatible = "jcore,pit";
> >> > + reg = < 0x200 0x30 >;
> >> > + cpu-offset = < 0x300 >;
> >>
> >> This is outside the reg range. Perhaps reg should include each range of
> >> per cpu registers.
> >
> > In the hardware, each timer instance is mapped independently so
> > there's no fundamental reason they need to be mapped sufficiently
> > close that it would make sense for a single virtual mapping to cover
> > them all. This doesn't matter for nommu but it would with mmu in the
> > future. In the driver I've updated it to ioremap each percpu instance
> > separately (as its own memory range) using the cpu-offset applied to
> > the range obtained from "reg". Is this acceptable (in which case I
> > suppose the binding needs to be documented that "reg" just covers the
> > cpu0 instance's range)? Do you think it would be preferable to have
> > multiple "reg" ranges indexed by cpu instead of cpu-offset?
>
> Yes. Either reg should cover the full range of addresses or you should
> have multiple reg values with one for each cpu. I prefer the latter as
> it doesn't create a custom property for expressing register addresses.
OK, let's lean towards going with the latter then. It's more flexible
and allows any placement of the maps; the offset per cpu does not have
to be constant. It also makes the driver code simpler since of_iomap
can be used directly rather than requiring of_address_to_resource,
physical address arithmetic arithmetic, and ioremap on the results. Is
there any precedent for using multiple reg ranges for percpu register
instances like this? Anything else they've been used for?
> > In theory it would even be possible to just require a DT node per
> > cpulocal timer, but I didn't see a good way to make the bindings
> > represent the relationship to cpus or to make the driver handle irqs
> > correctly for such a setup, so I'd need a viable proposal for how that
> > could be done to even consider such an approach.
>
> Yeah, there's not really a standard way to map per cpu blocks to cpus.
> We could, but doesn't really seem necessary here.
>
> For the irqs, percpu irqs doesn't help you?
What I mean is that, if there were a separate device node and driver
instance per cpu, they'd all want to register the same irq just to
handle it on their own cpu, so we'd have a lot of spurious handlers
running. The right way to model this, I think, would be as a virtual
irqchip that's the irq parent of all the timer nodes, and that
multiplexes the real irq to one virq per cpu (where the current cpu id
becomes the irq number in its irq domain). But that's a lot of virtual
infrastructure just for the sake of modelling each percpu timer as its
own DT node and I don't think it makes sense to do it that way.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-02 1:34 ` Rich Felker
@ 2016-06-02 22:44 ` Rob Herring
2016-06-23 21:16 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2016-06-02 22:44 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Wed, Jun 01, 2016 at 09:34:07PM -0400, Rich Felker wrote:
> On Wed, Jun 01, 2016 at 05:36:19PM -0500, Rob Herring wrote:
> > On Wed, Jun 1, 2016 at 12:53 PM, Rich Felker <dalias@libc.org> wrote:
> > > On Wed, Jun 01, 2016 at 08:58:52AM -0500, Rob Herring wrote:
> > >> On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> > >> > Signed-off-by: Rich Felker <dalias@libc.org>
> > >> > ---
> > >> > .../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
> > >> > 1 file changed, 28 insertions(+)
> > >> > create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> > >> > new file mode 100644
> > >> > index 0000000..96c6815
> > >> > --- /dev/null
> > >> > +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> > >> > @@ -0,0 +1,28 @@
> > >> > +J-Core Programmable Interval Timer and Clocksource
> > >> > +
> > >> > +Required properties:
> > >> > +
> > >> > +- compatible: Must be "jcore,pit".
> > >> > +
> > >> > +- reg: Memory region for timer/clocksource registers.
> > >> > +
> > >> > +- interrupts: An interrupt to assign for the timer. The actual pit
> > >> > + core is integrated with the aic and allows the timer interrupt
> > >> > + assignment to be programmed by software, but this property is
> > >> > + required in order to reserve an interrupt number that doesn't
> > >> > + conflict with other devices.
> > >> > +
> > >> > +Optional properties:
> > >> > +
> > >> > +- cpu-offset: For SMP, the per-cpu offset to the local timer
> > >> > + programming memory range.
> > >> > +
> > >> > +
> > >> > +Example:
> > >> > +
> > >> > +timer@200 {
> > >> > + compatible = "jcore,pit";
> > >> > + reg = < 0x200 0x30 >;
> > >> > + cpu-offset = < 0x300 >;
> > >>
> > >> This is outside the reg range. Perhaps reg should include each range of
> > >> per cpu registers.
> > >
> > > In the hardware, each timer instance is mapped independently so
> > > there's no fundamental reason they need to be mapped sufficiently
> > > close that it would make sense for a single virtual mapping to cover
> > > them all. This doesn't matter for nommu but it would with mmu in the
> > > future. In the driver I've updated it to ioremap each percpu instance
> > > separately (as its own memory range) using the cpu-offset applied to
> > > the range obtained from "reg". Is this acceptable (in which case I
> > > suppose the binding needs to be documented that "reg" just covers the
> > > cpu0 instance's range)? Do you think it would be preferable to have
> > > multiple "reg" ranges indexed by cpu instead of cpu-offset?
> >
> > Yes. Either reg should cover the full range of addresses or you should
> > have multiple reg values with one for each cpu. I prefer the latter as
> > it doesn't create a custom property for expressing register addresses.
>
> OK, let's lean towards going with the latter then. It's more flexible
> and allows any placement of the maps; the offset per cpu does not have
> to be constant. It also makes the driver code simpler since of_iomap
> can be used directly rather than requiring of_address_to_resource,
> physical address arithmetic arithmetic, and ioremap on the results. Is
> there any precedent for using multiple reg ranges for percpu register
> instances like this? Anything else they've been used for?
Maybe the memory mapped ARM arch timer. I'm not too sure off hand. It is
quite common for devices to have multiple reg addresses.
>
> > > In theory it would even be possible to just require a DT node per
> > > cpulocal timer, but I didn't see a good way to make the bindings
> > > represent the relationship to cpus or to make the driver handle irqs
> > > correctly for such a setup, so I'd need a viable proposal for how that
> > > could be done to even consider such an approach.
> >
> > Yeah, there's not really a standard way to map per cpu blocks to cpus.
> > We could, but doesn't really seem necessary here.
> >
> > For the irqs, percpu irqs doesn't help you?
>
> What I mean is that, if there were a separate device node and driver
> instance per cpu, they'd all want to register the same irq just to
> handle it on their own cpu, so we'd have a lot of spurious handlers
> running. The right way to model this, I think, would be as a virtual
> irqchip that's the irq parent of all the timer nodes, and that
> multiplexes the real irq to one virq per cpu (where the current cpu id
> becomes the irq number in its irq domain). But that's a lot of virtual
> infrastructure just for the sake of modelling each percpu timer as its
> own DT node and I don't think it makes sense to do it that way.
I would have thought your interrupt controller did all this. On the ARM
GIC for example, you have the same irq number but there is a per cpu
interface and really N (= # cpus) physical irq lines.
Rob
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-02 22:44 ` Rob Herring
@ 2016-06-23 21:16 ` Rich Felker
2016-07-14 22:18 ` Rich Felker
0 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-06-23 21:16 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, SH-Linux,
Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Thu, Jun 02, 2016 at 05:44:25PM -0500, Rob Herring wrote:
> > > > In theory it would even be possible to just require a DT node per
> > > > cpulocal timer, but I didn't see a good way to make the bindings
> > > > represent the relationship to cpus or to make the driver handle irqs
> > > > correctly for such a setup, so I'd need a viable proposal for how that
> > > > could be done to even consider such an approach.
> > >
> > > Yeah, there's not really a standard way to map per cpu blocks to cpus.
> > > We could, but doesn't really seem necessary here.
> > >
> > > For the irqs, percpu irqs doesn't help you?
> >
> > What I mean is that, if there were a separate device node and driver
> > instance per cpu, they'd all want to register the same irq just to
> > handle it on their own cpu, so we'd have a lot of spurious handlers
> > running. The right way to model this, I think, would be as a virtual
> > irqchip that's the irq parent of all the timer nodes, and that
> > multiplexes the real irq to one virq per cpu (where the current cpu id
> > becomes the irq number in its irq domain). But that's a lot of virtual
> > infrastructure just for the sake of modelling each percpu timer as its
> > own DT node and I don't think it makes sense to do it that way.
>
> I would have thought your interrupt controller did all this. On the ARM
> GIC for example, you have the same irq number but there is a per cpu
> interface and really N (= # cpus) physical irq lines.
I've looked at the ARM GIC code and bindings and I don't see where the
per-cpu interrupt interfaces are modelled with multiple interrupt
controller nodes or irq domains. It looks to me like it just uses a
single interrupt controller/domain with percpu irq. Does that match
your understanding?
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH v3 04/12] of: add J-Core timer bindings
2016-06-23 21:16 ` Rich Felker
@ 2016-07-14 22:18 ` Rich Felker
0 siblings, 0 replies; 52+ messages in thread
From: Rich Felker @ 2016-07-14 22:18 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Thu, Jun 23, 2016 at 05:16:08PM -0400, Rich Felker wrote:
> On Thu, Jun 02, 2016 at 05:44:25PM -0500, Rob Herring wrote:
> > > > > In theory it would even be possible to just require a DT node per
> > > > > cpulocal timer, but I didn't see a good way to make the bindings
> > > > > represent the relationship to cpus or to make the driver handle irqs
> > > > > correctly for such a setup, so I'd need a viable proposal for how that
> > > > > could be done to even consider such an approach.
> > > >
> > > > Yeah, there's not really a standard way to map per cpu blocks to cpus.
> > > > We could, but doesn't really seem necessary here.
> > > >
> > > > For the irqs, percpu irqs doesn't help you?
> > >
> > > What I mean is that, if there were a separate device node and driver
> > > instance per cpu, they'd all want to register the same irq just to
> > > handle it on their own cpu, so we'd have a lot of spurious handlers
> > > running. The right way to model this, I think, would be as a virtual
> > > irqchip that's the irq parent of all the timer nodes, and that
> > > multiplexes the real irq to one virq per cpu (where the current cpu id
> > > becomes the irq number in its irq domain). But that's a lot of virtual
> > > infrastructure just for the sake of modelling each percpu timer as its
> > > own DT node and I don't think it makes sense to do it that way.
> >
> > I would have thought your interrupt controller did all this. On the ARM
> > GIC for example, you have the same irq number but there is a per cpu
> > interface and really N (= # cpus) physical irq lines.
>
> I've looked at the ARM GIC code and bindings and I don't see where the
> per-cpu interrupt interfaces are modelled with multiple interrupt
> controller nodes or irq domains. It looks to me like it just uses a
> single interrupt controller/domain with percpu irq. Does that match
> your understanding?
Ping.
I want to submit this again for the upcoming merge window and need to
know whether you still want me to pursue different approaches.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v3 02/12] of: add J-Core cpu bindings
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (9 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 04/12] of: add J-Core timer bindings Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
[not found] ` <39ad5c69533ef537e6ab0426efc057f9064ee581.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-25 5:43 ` [PATCH v3 05/12] of: add J-Core SPI master bindings Rich Felker
[not found] ` <cover.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
Signed-off-by: Rich Felker <dalias@libc.org>
---
Documentation/devicetree/bindings/jcore/cpus.txt | 92 ++++++++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
new file mode 100644
index 0000000..9d77ec1
--- /dev/null
+++ b/Documentation/devicetree/bindings/jcore/cpus.txt
@@ -0,0 +1,92 @@
+=========+J-Core cpu bindings
+=========+
+The J-Core processors are open source CPU cores that can be built as FPGA
+soft cores or ASICs. The device tree is also responsible for describing the
+cache controls and, for SMP configurations, all details of the SMP method,
+as documented below.
+
+
+---------------------
+Top-level "cpus" node
+---------------------
+
+Required properties:
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+Optional properties:
+
+- enable-method: Required only for SMP systems. If present, must be
+ "jcore,spin-table".
+
+
+--------------------
+Individual cpu nodes
+--------------------
+
+Required properties:
+
+- device_type: Must be "cpu".
+
+- compatible: Must be "jcore,j2".
+
+- reg: Must be 0 on uniprocessor systems, or the sequential, zero-based
+ hardware cpu id on SMP systems.
+
+Optional properties:
+
+- clock-frequency: Clock frequency of the cpu in Hz.
+
+- cpu-release-addr: Necessary only for secondary processors on SMP systems
+ using the "jcore,spin-table" enable method. If present, must consist of
+ two cells containing physical addresses. The first cell contains an
+ address which, when written, unblocks the secondary cpu. The second cell
+ contains an address from which the cpu will read its initial program
+ counter when unblocked.
+
+
+---------------------
+Cache controller node
+---------------------
+
+Required properties:
+
+- compatible: Must be "jcore,cache".
+
+- reg: A memory range for the cache controller registers.
+
+
+--------
+IPI node
+--------
+
+Device trees for SMP systems must have an IPI node representing the mechanism
+used for inter-processor interrupt generation.
+
+Required properties:
+
+- compatible: Must be "jcore,ipi-controller".
+
+- reg: A memory range used to IPI generation.
+
+- interrupts: An irq on which IPI will be received.
+
+
+----------
+CPUID node
+----------
+
+Device trees for SMP systems must have a CPUID node representing the mechanism
+used to identify the current processor on which execution is taking place.
+
+Required properties:
+
+- compatible: Must be "jcore,cpuid-mmio".
+
+- reg: A memory range containing a single 32-bit mmio register which produces
+ the current cpu id (matching the "reg" property of the cpu performing the
+ read) when read.
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH v3 05/12] of: add J-Core SPI master bindings
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (10 preceding siblings ...)
2016-05-25 5:43 ` [PATCH v3 02/12] of: add J-Core cpu bindings Rich Felker
@ 2016-05-25 5:43 ` Rich Felker
2016-05-25 19:04 ` Rob Herring
[not found] ` <cover.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
12 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 5:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-spi, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
Signed-off-by: Rich Felker <dalias@libc.org>
---
.../devicetree/bindings/spi/jcore,spi.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
diff --git a/Documentation/devicetree/bindings/spi/jcore,spi.txt b/Documentation/devicetree/bindings/spi/jcore,spi.txt
new file mode 100644
index 0000000..7bff8c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/jcore,spi.txt
@@ -0,0 +1,23 @@
+J-Core SPI master
+
+Required properties:
+
+- compatible: Must be "jcore,spi2".
+
+- reg: Memory region for registers.
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+See spi-bus.txt for additional properties not specific to this device.
+
+Example:
+
+spi@40 {
+ compatible = "jcore,spi2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0x40 0x8 >;
+ spi-max-frequency = <12500000>;
+}
--
2.8.1
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH v3 05/12] of: add J-Core SPI master bindings
2016-05-25 5:43 ` [PATCH v3 05/12] of: add J-Core SPI master bindings Rich Felker
@ 2016-05-25 19:04 ` Rob Herring
0 siblings, 0 replies; 52+ messages in thread
From: Rob Herring @ 2016-05-25 19:04 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree, linux-kernel, linux-spi, linux-sh, Ian Campbell,
Kumar Gala, Mark Rutland, Pawel Moll
On Wed, May 25, 2016 at 05:43:03AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> .../devicetree/bindings/spi/jcore,spi.txt | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 52+ messages in thread
[parent not found: <cover.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>]
* Re: [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support
[not found] ` <cover.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
@ 2016-05-25 7:22 ` Geert Uytterhoeven
2016-05-25 9:54 ` Mark Brown
1 sibling, 0 replies; 52+ messages in thread
From: Geert Uytterhoeven @ 2016-05-25 7:22 UTC (permalink / raw)
To: Rich Felker
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Linux-sh list, linux-spi,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Daniel Lezcano,
Mark Brown
Hi Rich,
On Wed, May 25, 2016 at 7:43 AM, Rich Felker <dalias@libc.org> wrote:
> As arch/sh co-maintainer my intent is to include as much as possible
> in my pull request for the linux-sh tree. If there are parts outside
> of arch/sh that can be included in this, please let me know. I'm not
> clear yet on what the right path to upstream is for the clocksource
> and irq drivers that are currently only useful/interesting for one
> arch, or for the DT binding patches. Even if some drivers are delayed
Drivers outside arch/sh/ should go through the respective maintainer's tree,
unless that maintainer allows you to take it by giving his Acked-by.
The same for DT bindings for such drivers.
> going upstream, I would really like to get DT bindings acked and
> ideally merged, because we want to go ahead with moving the DTB into
> J2 boot rom where it belongs, and that should only happen with stable
> bindings.
Please also add a changelog, so people who reviewed your previous series
before know what to skip and what to focus on.
Please add collected Acked-by and Reviewed-by tags when reposting.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support
[not found] ` <cover.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-25 7:22 ` [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Geert Uytterhoeven
@ 2016-05-25 9:54 ` Mark Brown
2016-05-25 22:24 ` Rich Felker
1 sibling, 1 reply; 52+ messages in thread
From: Mark Brown @ 2016-05-25 9:54 UTC (permalink / raw)
To: Rich Felker
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA, linux-spi-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Thomas Gleixner, Jason Cooper,
Marc Zyngier, Daniel Lezcano
[-- Attachment #1: Type: text/plain, Size: 1292 bytes --]
On Wed, May 25, 2016 at 05:43:02AM +0000, Rich Felker wrote:
> As arch/sh co-maintainer my intent is to include as much as possible
> in my pull request for the linux-sh tree. If there are parts outside
> of arch/sh that can be included in this, please let me know. I'm not
Do *not* include the SPI driver, you shouldn't be including any drivers
unless it's been explicitly discussed with the subsystem maintainers.
Quite aside from the fact that like Geert says drivers are expected to
go through the subsystem trees to repeat what I said last time it wasn't
posted until after the merge window and we're now a few days before the
end of the merge window and a new version is being posted. The
turnaround times you are demanding on review are unreasonable - people
get busy, have holidays and so on - and you really need to pay attention
to what people are telling you about the process or you're just going to
annoy people.
> arch, or for the DT binding patches. Even if some drivers are delayed
> going upstream, I would really like to get DT bindings acked and
> ideally merged, because we want to go ahead with moving the DTB into
> J2 boot rom where it belongs, and that should only happen with stable
If you want people to review DT bindings you're going to need to submit
them.
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^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support
2016-05-25 9:54 ` Mark Brown
@ 2016-05-25 22:24 ` Rich Felker
[not found] ` <20160525222441.GS21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
0 siblings, 1 reply; 52+ messages in thread
From: Rich Felker @ 2016-05-25 22:24 UTC (permalink / raw)
To: Mark Brown
Cc: linux-kernel, linux-sh, linux-spi, devicetree, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Daniel Lezcano
On Wed, May 25, 2016 at 10:54:44AM +0100, Mark Brown wrote:
> On Wed, May 25, 2016 at 05:43:02AM +0000, Rich Felker wrote:
>
> > As arch/sh co-maintainer my intent is to include as much as possible
> > in my pull request for the linux-sh tree. If there are parts outside
> > of arch/sh that can be included in this, please let me know. I'm not
>
> Do *not* include the SPI driver, you shouldn't be including any drivers
> unless it's been explicitly discussed with the subsystem maintainers.
See the "please let me know". I thought this was plenty clear that I
was asking for permission for including things outside of arch/sh, and
that short of getting an ack, the default permission is no. You also
snipped the part of my message that mentioned the specific subsystems
I was asking about (which were non-SPI because you already made quite
a point about not taking the SPI driver):
> > clear yet on what the right path to upstream is for the clocksource
> > and irq drivers that are currently only useful/interesting for one
> > arch, or for the DT binding patches. Even if some drivers are delayed
> > [...]
> Quite aside from the fact that like Geert says drivers are expected to
> go through the subsystem trees to repeat what I said last time it wasn't
> posted until after the merge window and we're now a few days before the
> end of the merge window and a new version is being posted. The
> turnaround times you are demanding on review are unreasonable - people
> get busy, have holidays and so on - and you really need to pay attention
> to what people are telling you about the process or you're just going to
> annoy people.
If you can't review and ack the code on short notice, that's fine;
just say so. There's no need to be overerly hostile about it. I've
gotten arch/sh patches during the merge window before and I try to be
polite with the contributor and ask if there's something seriously
broken that would be improved by my making an effort to check it at
the last minute, or it if can happily wait until next time.
Being that the driver in question here is for a new platform that was
not previously supported upstream and has zero chance of breaking
anything else, and that its inclusion would be a big plus for users of
the platform, I don't see any reason for you making such a big deal
out of it unless enforcing policy for its own sake makes you feel
good, but I have better things to do than argue about it.
> > arch, or for the DT binding patches. Even if some drivers are delayed
> > going upstream, I would really like to get DT bindings acked and
> > ideally merged, because we want to go ahead with moving the DTB into
> > J2 boot rom where it belongs, and that should only happen with stable
>
> If you want people to review DT bindings you're going to need to submit
> them.
I have, twice now, and I Cc'd the the linux-spi list too on v3 for the
spi binding. Rob Herring acked it.
Rich
^ permalink raw reply [flat|nested] 52+ messages in thread