From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Ball Date: Wed, 19 Sep 2012 06:25:41 +0000 Subject: Re: [PATCH] mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ Message-Id: List-Id: References: <505932E9.8050202@kmckk.co.jp> In-Reply-To: <505932E9.8050202@kmckk.co.jp> (Tetsuyuki Kobayashi's message of "Wed, 19 Sep 2012 11:50:17 +0900") MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Tetsuyuki Kobayashi Cc: Guennadi Liakhovetski , linux-mmc@vger.kernel.org, yusuke.goda.sx@renesas.com, Kuninori Morimoto , Paul Mundt , Magnus Damm , linux-sh@vger.kernel.org, Kuninori Morimoto Hi, On Tue, Sep 18 2012, Tetsuyuki Kobayashi wrote: > (2012/09/19 8:10), Guennadi Liakhovetski wrote: >> Upon completion of a MMC_WRITE_MULTIPLE_BLOCK command MMCIF issues an IRQ >> with the DTRANE bit set and often with one or several of CMD12 bits set. >> If those interrupts are not acknowledged, an additional interrupt can be >> produced and will be delivered later, possibly, when the transaction has >> already been completed. To prevent this from happening, CMD12 completion >> interrupt sources have to be cleared too upon reception of an DTRANE IRQ. >> >> Signed-off-by: Guennadi Liakhovetski >> --- >> >> Tested on kzm9g and mackerel. Kobayashi-san, this fixes spurious >> interrupts, that you are observing. > > I verified on kzm9g. > This works with > [PATCH] mmc: sh-mmcif: avoid Oops on spurious interrupts > > Tested-by: Tetsuyuki Kobayashi Thanks, pushed to mmc-next for 3.7. - Chris. -- Chris Ball One Laptop Per Child