* Re: [PATCH][RESEND] ARM: mach-shmobile: sh7372 generic suspend/resume support
From: Magnus Damm @ 2011-08-26 9:47 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110826051205.24370.44903.sendpatchset@rxone.opensource.se>
On Fri, Aug 26, 2011 at 6:23 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Fri, Aug 26, 2011 at 05:44:04PM +0900, Magnus Damm wrote:
>> Good question. This was posted before the 3.1-rc merge window, but
>> didn't make it into mainline for some unknown
>> reason. I'm all for merging things sooner than later if possible, but
>> I understand if 3.1-rc is out of the question at this point.
>>
>> If you are offering to queue this up for the 3.2 merge window then I
>> am instead suggesting that Rafael picks this up in his PM tree because
>> there are other PM related patches that build on top of this one.
>
> If Rafael wants to pick it up, that's fine.
Let's see what he says about that.
>> While at it, for the 3.1 release, would it be possible to update the
>> mach-types list in mainline? We have patches for the Kota2 board that
>> depend on the mach-type update.
>
> I dropped my mach-types update (which was required to fix a build error -
> because a platform was introduced into mainline without its entry in
> mach-types) as the update was causing a number of problems with other
> platforms and drivers in mainline.
Ouch.
> I'm not sure what the long term future of mach-types is, as it's become
> quite a burden to manually update it each time due to the amount of crap
> now contained in there, and it seems automated filtering results in
> breakage.
Honestly, I think your mach-types list and the patch tracker have
served their purpose for a long time. They make totally sense to
handle the kind of work load and of diverse hardware platform support
that you have been dealing with over the years. These days I suspect
there are other solutions available that may make it easier for you.
> I think the whole interface to it needs to be revised so that it is
> purely read-only, and editing is done via human interaction adding a
> level of manual approval to the system. It's the only way I can think
> of stopping the 'ARM', 'IMX', etc like entries from being added, along
> with ensuring that the machine_is_xxx() and MACH_TYPE_xxx() names always
> match.
I guess you prefer to keep the information separate from the Linux kernel?
If you don't mind, then wouldn't it be possible to move over the
information to some more verbose form of the mach-types file and store
it in the kernel tree and use regular git to manage it? That's what I
would do.
Another option is to extend your web interface and separate addition
of new entries from modification of already existing ones. Perhaps new
entries can be merged at any time in -rc but modification needs to
happen early in the cycle.
Cheers,
/ magnus
^ permalink raw reply
* Re: [PATCH][RESEND] ARM: mach-shmobile: sh7372 generic
From: Russell King - ARM Linux @ 2011-08-26 9:23 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110826051205.24370.44903.sendpatchset@rxone.opensource.se>
On Fri, Aug 26, 2011 at 05:44:04PM +0900, Magnus Damm wrote:
> Good question. This was posted before the 3.1-rc merge window, but
> didn't make it into mainline for some unknown
> reason. I'm all for merging things sooner than later if possible, but
> I understand if 3.1-rc is out of the question at this point.
>
> If you are offering to queue this up for the 3.2 merge window then I
> am instead suggesting that Rafael picks this up in his PM tree because
> there are other PM related patches that build on top of this one.
If Rafael wants to pick it up, that's fine.
> While at it, for the 3.1 release, would it be possible to update the
> mach-types list in mainline? We have patches for the Kota2 board that
> depend on the mach-type update.
I dropped my mach-types update (which was required to fix a build error -
because a platform was introduced into mainline without its entry in
mach-types) as the update was causing a number of problems with other
platforms and drivers in mainline.
I'm not sure what the long term future of mach-types is, as it's become
quite a burden to manually update it each time due to the amount of crap
now contained in there, and it seems automated filtering results in
breakage.
I think the whole interface to it needs to be revised so that it is
purely read-only, and editing is done via human interaction adding a
level of manual approval to the system. It's the only way I can think
of stopping the 'ARM', 'IMX', etc like entries from being added, along
with ensuring that the machine_is_xxx() and MACH_TYPE_xxx() names always
match.
^ permalink raw reply
* Re: [PATCH v8 4/4] ARM: shmobile: ag5evm, ap4: Named SDHI IRQ sources
From: Guennadi Liakhovetski @ 2011-08-26 9:22 UTC (permalink / raw)
To: Simon Horman; +Cc: linux-mmc, linux-sh, Chris Ball, Paul Mundt, Magnus Damm
In-Reply-To: <20110826091407.GB5380@verge.net.au>
On Fri, 26 Aug 2011, Simon Horman wrote:
> On Fri, Aug 26, 2011 at 10:44:16AM +0200, Guennadi Liakhovetski wrote:
> > On Thu, 25 Aug 2011, Simon Horman wrote:
> >
> > > This allows specific (non-multiplexed) IRQ handlers to be used.
> >
> > Could you also prepare a similar patch for g4evm and ap4evb? No need to
> > change this one, just prepare another one, please.
>
> Sure, though I do not have access to those boards to test
> (as far as I know).
Ok, I've got an ap4evb, so, I'll prepare that patch myself.
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* Re: [PATCH v8 4/4] ARM: shmobile: ag5evm, ap4: Named SDHI IRQ sources
From: Simon Horman @ 2011-08-26 9:14 UTC (permalink / raw)
To: Guennadi Liakhovetski
Cc: linux-mmc, linux-sh, Chris Ball, Paul Mundt, Magnus Damm
In-Reply-To: <Pine.LNX.4.64.1108261042450.25272@axis700.grange>
On Fri, Aug 26, 2011 at 10:44:16AM +0200, Guennadi Liakhovetski wrote:
> On Thu, 25 Aug 2011, Simon Horman wrote:
>
> > This allows specific (non-multiplexed) IRQ handlers to be used.
>
> Could you also prepare a similar patch for g4evm and ap4evb? No need to
> change this one, just prepare another one, please.
Sure, though I do not have access to those boards to test
(as far as I know).
^ permalink raw reply
* Re: [PATCH 3/4 v9] mmc: sdhi: Allow named IRQs to use specific
From: Simon Horman @ 2011-08-26 9:13 UTC (permalink / raw)
To: Guennadi Liakhovetski
Cc: linux-mmc, linux-sh, Chris Ball, Paul Mundt, Magnus Damm
In-Reply-To: <Pine.LNX.4.64.1108261022320.25272@axis700.grange>
On Fri, Aug 26, 2011 at 10:42:39AM +0200, Guennadi Liakhovetski wrote:
> From: Simon Horman <horms@verge.net.au>
>
> Allow named IRQs to use corresponding specific handlers. If named IRQs are
> used, at least an "sdcard" IRQ has to be specified by the platform. If
> names are not used, an arbitrary number of IRQs can be provided by the
> platform, in which case the generic ISR will be used for each of them.
>
> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> Acked-by: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
> [g.liakhovetski@gmx.de: style and typo corrections, platform data check]
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> ---
>
> Simon, this is what I propose to commit. I fixed a typo, wrong multi-line
> comment style and indentation spaces in your patch. Besides, I added a
> check to require the SDCARD IRQ if named IRQs are used. It is a common
> practice to verify platform data availability and at least some basic
> correctness and completeness. This check is trivial and adds extra
> robustness to the driver. Please, have a look, whether you agree with my
> version.
Hi Guennadi,
thanks, this looks fine to me.
I would prefer slightly if SDCARD wasn't required.
But I think that is a discussion that we can have
if/when a use-case arises.
^ permalink raw reply
* Re: [PATCH v8 4/4] ARM: shmobile: ag5evm, ap4: Named SDHI IRQ sources
From: Guennadi Liakhovetski @ 2011-08-26 8:44 UTC (permalink / raw)
To: Simon Horman; +Cc: linux-mmc, linux-sh, Chris Ball, Paul Mundt, Magnus Damm
In-Reply-To: <1314235648-8959-5-git-send-email-horms@verge.net.au>
On Thu, 25 Aug 2011, Simon Horman wrote:
> This allows specific (non-multiplexed) IRQ handlers to be used.
Could you also prepare a similar patch for g4evm and ap4evb? No need to
change this one, just prepare another one, please.
Thanks
Guennadi
>
> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> Cc: Paul Mundt <lethal@linux-sh.org>
> Acked-by: Magnus Damm <magnus.damm@gmail.com>
> Signed-off-by: Simon Horman <horms@verge.net.au>
>
> ---
>
> Requires
> "mmc: sdhi: Allow specific IRQ sources to use corresponding handlers."
>
> v7
> * Rework to use named IRQs
>
> v4
> * Update for corrected ordering of SH_MOBILE_SDHI_IRQ_SDCARD and
> SH_MOBILE_SDHI_IRQ_CARD_DETECT
>
> v2
> * Initial release
> ---
> arch/arm/mach-shmobile/board-ag5evm.c | 6 ++++++
> arch/arm/mach-shmobile/board-mackerel.c | 6 ++++++
> 2 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
> index ce5c251..e100cad 100644
> --- a/arch/arm/mach-shmobile/board-ag5evm.c
> +++ b/arch/arm/mach-shmobile/board-ag5evm.c
> @@ -353,14 +353,17 @@ static struct resource sdhi0_resources[] = {
> .flags = IORESOURCE_MEM,
> },
> [1] = {
> + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
> .start = gic_spi(83),
> .flags = IORESOURCE_IRQ,
> },
> [2] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDCARD,
> .start = gic_spi(84),
> .flags = IORESOURCE_IRQ,
> },
> [3] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDIO,
> .start = gic_spi(85),
> .flags = IORESOURCE_IRQ,
> },
> @@ -396,14 +399,17 @@ static struct resource sdhi1_resources[] = {
> .flags = IORESOURCE_MEM,
> },
> [1] = {
> + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
> .start = gic_spi(87),
> .flags = IORESOURCE_IRQ,
> },
> [2] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDCARD,
> .start = gic_spi(88),
> .flags = IORESOURCE_IRQ,
> },
> [3] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDIO,
> .start = gic_spi(89),
> .flags = IORESOURCE_IRQ,
> },
> diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
> index d41c01f..492274f 100644
> --- a/arch/arm/mach-shmobile/board-mackerel.c
> +++ b/arch/arm/mach-shmobile/board-mackerel.c
> @@ -1066,14 +1066,17 @@ static struct resource sdhi1_resources[] = {
> .flags = IORESOURCE_MEM,
> },
> [1] = {
> + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
> .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
> .flags = IORESOURCE_IRQ,
> },
> [2] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDCARD,
> .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
> .flags = IORESOURCE_IRQ,
> },
> [3] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDIO,
> .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
> .flags = IORESOURCE_IRQ,
> },
> @@ -1117,14 +1120,17 @@ static struct resource sdhi2_resources[] = {
> .flags = IORESOURCE_MEM,
> },
> [1] = {
> + .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
> .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
> .flags = IORESOURCE_IRQ,
> },
> [2] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDCARD,
> .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
> .flags = IORESOURCE_IRQ,
> },
> [3] = {
> + .name = SH_MOBILE_SDHI_IRQ_SDIO,
> .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
> .flags = IORESOURCE_IRQ,
> },
> --
> 1.7.5.4
>
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* Re: [PATCH][RESEND] ARM: mach-shmobile: sh7372 generic suspend/resume support
From: Magnus Damm @ 2011-08-26 8:44 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110826051205.24370.44903.sendpatchset@rxone.opensource.se>
On Fri, Aug 26, 2011 at 5:25 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> Who are you wanting to merge your patch?
>
> To: linux-sh@vger.kernel.org
> Cc: rjw@sisk.pl, Magnus Damm <magnus.damm@gmail.com>, lethal@linux-sh.org,
> linux@arm.linux.org.uk
>
> Generally, the person who you want to apply the patch goes into the
> To: line - so I'm interpreting your message as you want someone on
> linux-sh to merge your patch - I'm presuming Paul rather than me.
> Is that correct?
Thanks for your reply!
Good question. This was posted before the 3.1-rc merge window, but
didn't make it into mainline for some unknown
reason. I'm all for merging things sooner than later if possible, but
I understand if 3.1-rc is out of the question at this point.
If you are offering to queue this up for the 3.2 merge window then I
am instead suggesting that Rafael picks this up in his PM tree because
there are other PM related patches that build on top of this one.
While at it, for the 3.1 release, would it be possible to update the
mach-types list in mainline? We have patches for the Kota2 board that
depend on the mach-type update.
Thanks!
/ magnus
^ permalink raw reply
* [PATCH 3/4 v9] mmc: sdhi: Allow named IRQs to use specific handlers
From: Guennadi Liakhovetski @ 2011-08-26 8:42 UTC (permalink / raw)
To: Simon Horman; +Cc: linux-mmc, linux-sh, Chris Ball, Paul Mundt, Magnus Damm
In-Reply-To: <1314235648-8959-4-git-send-email-horms@verge.net.au>
From: Simon Horman <horms@verge.net.au>
Allow named IRQs to use corresponding specific handlers. If named IRQs are
used, at least an "sdcard" IRQ has to be specified by the platform. If
names are not used, an arbitrary number of IRQs can be provided by the
platform, in which case the generic ISR will be used for each of them.
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
[g.liakhovetski@gmx.de: style and typo corrections, platform data check]
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
---
Simon, this is what I propose to commit. I fixed a typo, wrong multi-line
comment style and indentation spaces in your patch. Besides, I added a
check to require the SDCARD IRQ if named IRQs are used. It is a common
practice to verify platform data availability and at least some basic
correctness and completeness. This check is trivial and adds extra
robustness to the driver. Please, have a look, whether you agree with my
version.
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index 774f643..d9013ad 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -96,7 +96,8 @@ static int __devinit sh_mobile_sdhi_probe(struct platform_device *pdev)
struct sh_mobile_sdhi_info *p = pdev->dev.platform_data;
struct tmio_mmc_host *host;
char clk_name[8];
- int i, irq, ret;
+ int irq, ret, i = 0;
+ bool multiplexed_isr = true;
priv = kzalloc(sizeof(struct sh_mobile_sdhi), GFP_KERNEL);
if (priv = NULL) {
@@ -153,27 +154,60 @@ static int __devinit sh_mobile_sdhi_probe(struct platform_device *pdev)
if (ret < 0)
goto eprobe;
- for (i = 0; i < 3; i++) {
- irq = platform_get_irq(pdev, i);
- if (irq < 0) {
- if (i) {
- continue;
- } else {
- ret = irq;
- goto eirq;
- }
- }
- ret = request_irq(irq, tmio_mmc_irq, 0,
+ /*
+ * Allow one or more specific (named) ISRs or
+ * one or more multiplexed (un-named) ISRs.
+ */
+
+ irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_CARD_DETECT);
+ if (irq >= 0) {
+ multiplexed_isr = false;
+ ret = request_irq(irq, tmio_mmc_card_detect_irq, 0,
+ dev_name(&pdev->dev), host);
+ if (ret)
+ goto eirq_card_detect;
+ }
+
+ irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_SDIO);
+ if (irq >= 0) {
+ multiplexed_isr = false;
+ ret = request_irq(irq, tmio_mmc_sdio_irq, 0,
+ dev_name(&pdev->dev), host);
+ if (ret)
+ goto eirq_sdio;
+ }
+
+ irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_SDCARD);
+ if (irq >= 0) {
+ multiplexed_isr = false;
+ ret = request_irq(irq, tmio_mmc_sdcard_irq, 0,
dev_name(&pdev->dev), host);
- if (ret) {
- while (i--) {
- irq = platform_get_irq(pdev, i);
- if (irq >= 0)
- free_irq(irq, host);
- }
- goto eirq;
+ if (ret)
+ goto eirq_sdcard;
+ } else if (!multiplexed_isr) {
+ dev_err(&pdev->dev,
+ "Principal SD-card IRQ is missing among named interrupts\n");
+ ret = irq;
+ goto eirq_sdcard;
+ }
+
+ if (multiplexed_isr) {
+ while (1) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ break;
+ i++;
+ ret = request_irq(irq, tmio_mmc_irq, 0,
+ dev_name(&pdev->dev), host);
+ if (ret)
+ goto eirq_multiplexed;
}
+
+ /* There must be at least one IRQ source */
+ if (!i)
+ goto eirq_multiplexed;
}
+
dev_info(&pdev->dev, "%s base at 0x%08lx clock rate %u MHz\n",
mmc_hostname(host->mmc), (unsigned long)
(platform_get_resource(pdev,IORESOURCE_MEM, 0)->start),
@@ -181,7 +215,20 @@ static int __devinit sh_mobile_sdhi_probe(struct platform_device *pdev)
return ret;
-eirq:
+eirq_multiplexed:
+ while (i--) {
+ irq = platform_get_irq(pdev, i);
+ free_irq(irq, host);
+ }
+eirq_sdcard:
+ irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_SDIO);
+ if (irq >= 0)
+ free_irq(irq, host);
+eirq_sdio:
+ irq = platform_get_irq_byname(pdev, SH_MOBILE_SDHI_IRQ_CARD_DETECT);
+ if (irq >= 0)
+ free_irq(irq, host);
+eirq_card_detect:
tmio_mmc_host_remove(host);
eprobe:
clk_disable(priv->clk);
@@ -197,16 +244,17 @@ static int sh_mobile_sdhi_remove(struct platform_device *pdev)
struct tmio_mmc_host *host = mmc_priv(mmc);
struct sh_mobile_sdhi *priv = container_of(host->pdata, struct sh_mobile_sdhi, mmc_data);
struct sh_mobile_sdhi_info *p = pdev->dev.platform_data;
- int i, irq;
+ int i = 0, irq;
p->pdata = NULL;
tmio_mmc_host_remove(host);
- for (i = 0; i < 3; i++) {
- irq = platform_get_irq(pdev, i);
- if (irq >= 0)
- free_irq(irq, host);
+ while (1) {
+ irq = platform_get_irq(pdev, i++);
+ if (irq < 0)
+ break;
+ free_irq(irq, host);
}
clk_disable(priv->clk);
diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h
index bd50b36..71b8054 100644
--- a/include/linux/mmc/sh_mobile_sdhi.h
+++ b/include/linux/mmc/sh_mobile_sdhi.h
@@ -6,6 +6,10 @@
struct platform_device;
struct tmio_mmc_data;
+#define SH_MOBILE_SDHI_IRQ_CARD_DETECT "card_detect"
+#define SH_MOBILE_SDHI_IRQ_SDCARD "sdcard"
+#define SH_MOBILE_SDHI_IRQ_SDIO "sdio"
+
struct sh_mobile_sdhi_info {
int dma_slave_tx;
int dma_slave_rx;
^ permalink raw reply related
* Re: [PATCH][RESEND] ARM: mach-shmobile: sh7372 generic
From: Russell King - ARM Linux @ 2011-08-26 8:25 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110826051205.24370.44903.sendpatchset@rxone.opensource.se>
Who are you wanting to merge your patch?
To: linux-sh@vger.kernel.org
Cc: rjw@sisk.pl, Magnus Damm <magnus.damm@gmail.com>, lethal@linux-sh.org,
linux@arm.linux.org.uk
Generally, the person who you want to apply the patch goes into the
To: line - so I'm interpreting your message as you want someone on
linux-sh to merge your patch - I'm presuming Paul rather than me.
Is that correct?
On Fri, Aug 26, 2011 at 02:12:05PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm@opensource.se>
>
> Convert the sh7372 Core Standby code to make use
> of the new generic ARM cpu suspend/resume code.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> ---
>
> arch/arm/mach-shmobile/include/mach/common.h | 3
> arch/arm/mach-shmobile/pm-sh7372.c | 38 +---
> arch/arm/mach-shmobile/sleep-sh7372.S | 230 --------------------------
> 3 files changed, 24 insertions(+), 247 deletions(-)
>
> --- 0001/arch/arm/mach-shmobile/include/mach/common.h
> +++ work/arch/arm/mach-shmobile/include/mach/common.h 2011-07-06 18:11:38.000000000 +0900
> @@ -35,8 +35,7 @@ extern void sh7372_add_standard_devices(
> extern void sh7372_clock_init(void);
> extern void sh7372_pinmux_init(void);
> extern void sh7372_pm_init(void);
> -extern void sh7372_cpu_suspend(void);
> -extern void sh7372_cpu_resume(void);
> +extern void sh7372_resume_core_standby(void);
> extern struct clk sh7372_extal1_clk;
> extern struct clk sh7372_extal2_clk;
>
> --- 0001/arch/arm/mach-shmobile/pm-sh7372.c
> +++ work/arch/arm/mach-shmobile/pm-sh7372.c 2011-07-06 18:34:40.000000000 +0900
> @@ -18,6 +18,7 @@
> #include <asm/system.h>
> #include <asm/io.h>
> #include <asm/tlbflush.h>
> +#include <asm/suspend.h>
> #include <mach/common.h>
>
> #define SMFRAM 0xe6a70000
> @@ -25,30 +26,25 @@
> #define SBAR 0xe6180020
> #define APARMBAREA 0xe6f10020
>
> -static void sh7372_enter_core_standby(void)
> +static int sh7372_do_idle_core_standby(unsigned long unused)
> {
> - void __iomem *smfram = (void __iomem *)SMFRAM;
> -
> - __raw_writel(0, APARMBAREA); /* translate 4k */
> - __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
> - __raw_writel(0x10, SYSTBCR); /* enable core standby */
> -
> - __raw_writel(0, smfram + 0x3c); /* clear page table address */
> -
> - sh7372_cpu_suspend();
> - cpu_init();
> -
> - /* if page table address is non-NULL then we have been powered down */
> - if (__raw_readl(smfram + 0x3c)) {
> - __raw_writel(__raw_readl(smfram + 0x40),
> - __va(__raw_readl(smfram + 0x3c)));
> + cpu_do_idle(); /* WFI when SYSTBCR = 0x10 -> Core Standby */
> + return 0;
> +}
>
> - flush_tlb_all();
> - set_cr(__raw_readl(smfram + 0x38));
> - }
> +static void sh7372_enter_core_standby(void)
> +{
> + /* set reset vector, translate 4k */
> + __raw_writel(__pa(sh7372_resume_core_standby), SBAR);
> + __raw_writel(0, APARMBAREA);
> +
> + /* enter sleep mode with SYSTBCR to 0x10 */
> + __raw_writel(0x10, SYSTBCR);
> + cpu_suspend(0, sh7372_do_idle_core_standby);
> + __raw_writel(0, SYSTBCR);
>
> - __raw_writel(0, SYSTBCR); /* disable core standby */
> - __raw_writel(0, SBAR); /* disable reset vector translation */
> + /* disable reset vector translation */
> + __raw_writel(0, SBAR);
> }
>
> #ifdef CONFIG_CPU_IDLE
> --- 0001/arch/arm/mach-shmobile/sleep-sh7372.S
> +++ work/arch/arm/mach-shmobile/sleep-sh7372.S 2011-07-06 18:32:44.000000000 +0900
> @@ -30,231 +30,13 @@
> */
>
> #include <linux/linkage.h>
> +#include <linux/init.h>
> +#include <asm/memory.h>
> #include <asm/assembler.h>
>
> -#define SMFRAM 0xe6a70000
> -
> - .align
> -kernel_flush:
> - .word v7_flush_dcache_all
> -
> - .align 3
> -ENTRY(sh7372_cpu_suspend)
> - stmfd sp!, {r0-r12, lr} @ save registers on stack
> -
> - ldr r8, =SMFRAM
> -
> - mov r4, sp @ Store sp
> - mrs r5, spsr @ Store spsr
> - mov r6, lr @ Store lr
> - stmia r8!, {r4-r6}
> -
> - mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
> - mrc p15, 0, r5, c2, c0, 0 @ TTBR0
> - mrc p15, 0, r6, c2, c0, 1 @ TTBR1
> - mrc p15, 0, r7, c2, c0, 2 @ TTBCR
> - stmia r8!, {r4-r7}
> -
> - mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
> - mrc p15, 0, r5, c10, c2, 0 @ PRRR
> - mrc p15, 0, r6, c10, c2, 1 @ NMRR
> - stmia r8!,{r4-r6}
> -
> - mrc p15, 0, r4, c13, c0, 1 @ Context ID
> - mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
> - mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
> - mrs r7, cpsr @ Store current cpsr
> - stmia r8!, {r4-r7}
> -
> - mrc p15, 0, r4, c1, c0, 0 @ save control register
> - stmia r8!, {r4}
> -
> - /*
> - * jump out to kernel flush routine
> - * - reuse that code is better
> - * - it executes in a cached space so is faster than refetch per-block
> - * - should be faster and will change with kernel
> - * - 'might' have to copy address, load and jump to it
> - * Flush all data from the L1 data cache before disabling
> - * SCTLR.C bit.
> - */
> - ldr r1, kernel_flush
> - mov lr, pc
> - bx r1
> -
> - /*
> - * Clear the SCTLR.C bit to prevent further data cache
> - * allocation. Clearing SCTLR.C would make all the data accesses
> - * strongly ordered and would not hit the cache.
> - */
> - mrc p15, 0, r0, c1, c0, 0
> - bic r0, r0, #(1 << 2) @ Disable the C bit
> - mcr p15, 0, r0, c1, c0, 0
> - isb
> -
> - /*
> - * Invalidate L1 data cache. Even though only invalidate is
> - * necessary exported flush API is used here. Doing clean
> - * on already clean cache would be almost NOP.
> - */
> - ldr r1, kernel_flush
> - blx r1
> - /*
> - * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
> - * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
> - * This sequence switches back to ARM. Note that .align may insert a
> - * nop: bx pc needs to be word-aligned in order to work.
> - */
> - THUMB( .thumb )
> - THUMB( .align )
> - THUMB( bx pc )
> - THUMB( nop )
> - .arm
> -
> - /* Data memory barrier and Data sync barrier */
> - dsb
> - dmb
> -
> -/*
> - * =================> - * = WFI instruction => Enter idle =
> - * =================> - */
> - wfi @ wait for interrupt
> -
> -/*
> - * =================> - * = Resume path for non-OFF modes =
> - * =================> - */
> - mrc p15, 0, r0, c1, c0, 0
> - tst r0, #(1 << 2) @ Check C bit enabled?
> - orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
> - mcreq p15, 0, r0, c1, c0, 0
> - isb
> -
> -/*
> - * =================> - * = Exit point from non-OFF modes =
> - * =================> - */
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> -
> - .pool
> -
> .align 12
> .text
> - .global sh7372_cpu_resume
> -sh7372_cpu_resume:
> -
> - mov r1, #0
> - /*
> - * Invalidate all instruction caches to PoU
> - * and flush branch target cache
> - */
> - mcr p15, 0, r1, c7, c5, 0
> -
> - ldr r3, =SMFRAM
> -
> - ldmia r3!, {r4-r6}
> - mov sp, r4 @ Restore sp
> - msr spsr_cxsf, r5 @ Restore spsr
> - mov lr, r6 @ Restore lr
> -
> - ldmia r3!, {r4-r7}
> - mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
> - mcr p15, 0, r5, c2, c0, 0 @ TTBR0
> - mcr p15, 0, r6, c2, c0, 1 @ TTBR1
> - mcr p15, 0, r7, c2, c0, 2 @ TTBCR
> -
> - ldmia r3!,{r4-r6}
> - mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
> - mcr p15, 0, r5, c10, c2, 0 @ PRRR
> - mcr p15, 0, r6, c10, c2, 1 @ NMRR
> -
> - ldmia r3!,{r4-r7}
> - mcr p15, 0, r4, c13, c0, 1 @ Context ID
> - mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
> - mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
> - msr cpsr, r7 @ store cpsr
> -
> - /* Starting to enable MMU here */
> - mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
> - /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
> - and r7, #0x7
> - cmp r7, #0x0
> - beq usettbr0
> -ttbr_error:
> - /*
> - * More work needs to be done to support N[0:2] value other than 0
> - * So looping here so that the error can be detected
> - */
> - b ttbr_error
> -
> - .align
> -cache_pred_disable_mask:
> - .word 0xFFFFE7FB
> -ttbrbit_mask:
> - .word 0xFFFFC000
> -table_index_mask:
> - .word 0xFFF00000
> -table_entry:
> - .word 0x00000C02
> -usettbr0:
> -
> - mrc p15, 0, r2, c2, c0, 0
> - ldr r5, ttbrbit_mask
> - and r2, r5
> - mov r4, pc
> - ldr r5, table_index_mask
> - and r4, r5 @ r4 = 31 to 20 bits of pc
> - /* Extract the value to be written to table entry */
> - ldr r6, table_entry
> - /* r6 has the value to be written to table entry */
> - add r6, r6, r4
> - /* Getting the address of table entry to modify */
> - lsr r4, #18
> - /* r2 has the location which needs to be modified */
> - add r2, r4
> - ldr r4, [r2]
> - str r6, [r2] /* modify the table entry */
> -
> - mov r7, r6
> - mov r5, r2
> - mov r6, r4
> - /* r5 = original page table address */
> - /* r6 = original page table data */
> -
> - mov r0, #0
> - mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
> - mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
> - mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
> - mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
> -
> - /*
> - * Restore control register. This enables the MMU.
> - * The caches and prediction are not enabled here, they
> - * will be enabled after restoring the MMU table entry.
> - */
> - ldmia r3!, {r4}
> - stmia r3!, {r5} /* save original page table address */
> - stmia r3!, {r6} /* save original page table data */
> - stmia r3!, {r7} /* save modified page table data */
> -
> - ldr r2, cache_pred_disable_mask
> - and r4, r2
> - mcr p15, 0, r4, c1, c0, 0
> - dsb
> - isb
> -
> - ldr r0, =restoremmu_on
> - bx r0
> -
> -/*
> - * ===============
> - * = Exit point from OFF mode =
> - * ===============
> - */
> -restoremmu_on:
> -
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> + .global sh7372_resume_core_standby
> +sh7372_resume_core_standby:
> + ldr pc, 1f
> +1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
^ permalink raw reply
* Re: Can not compile Ecovec board
From: Paul Mundt @ 2011-08-26 8:14 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87aaaxou97.wl%kuninori.morimoto.gx@renesas.com>
On Fri, Aug 26, 2011 at 03:18:26PM +0900, Nobuhiro Iwamatsu wrote:
> 2011/8/26 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>:
> > 2011/8/26 Magnus Damm <magnus.damm@gmail.com>:
> >> On Fri, Aug 26, 2011 at 1:30 PM, Nobuhiro Iwamatsu <iwamatsu@nigauri.org> wrote:
> >>> This was already revised in linux-next tree.
> >>
> >> That's great, but shouldn't build fixes be solved for the RC kernels
> >> if possible?
> >>
> >> People really need to learn how to separate build fixes from new
> >> development, otherwise everything will turn to shit.
> >>
> >
> > The commitment to revise this problem seems to be taken in with
> > signed-off of Paul by repository of Paul.
> > I think that It will be up to Paul whether this is taken-in in rc3.
> > Paul, do you think about this?
> >
> Sorry, commit is not in Paul's repository.
> This is in Paul Gortmaker's tree.
>
I've had the same fix in my tree for some time, so I'm not sure what
you're looking at. It'll be included with the next batch of updates for
the next -rc, as usual.
^ permalink raw reply
* [PATCH] ARM: mach-shmobile: clock-sh73a0: tidyup CKSCR main clock selecter
From: Kuninori Morimoto @ 2011-08-26 7:27 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <w3pmxozyxra.wl%kuninori.morimoto.gx@renesas.com>
MAINCKSEL is [29:28], not [27:24]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
arch/arm/mach-shmobile/clock-sh73a0.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7da8af6..84fd33c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -365,7 +365,7 @@ void __init sh73a0_clock_init(void)
__raw_writel(0x108, SD2CKCR);
/* detect main clock parent */
- switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
+ switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
case 0:
main_clk.parent = &sh73a0_extal1_clk;
break;
--
1.7.4.1
^ permalink raw reply related
* [PATCH 03/03] ARM: mach-shmobile: sh7372 A4R support
From: Magnus Damm @ 2011-08-26 6:43 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
This patch adds sh7372 A4R power domain support.
The sh7372 A3SP hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.
One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/board-ap4evb.c | 1
arch/arm/mach-shmobile/board-mackerel.c | 1
arch/arm/mach-shmobile/include/mach/sh7372.h | 4 +
arch/arm/mach-shmobile/intc-sh7372.c | 52 ++++++++++++++++++++++
arch/arm/mach-shmobile/pm-sh7372.c | 59 +++++++++++++++++++++++---
arch/arm/mach-shmobile/setup-sh7372.c | 7 +++
6 files changed, 118 insertions(+), 6 deletions(-)
--- 0012/arch/arm/mach-shmobile/board-ap4evb.c
+++ work/arch/arm/mach-shmobile/board-ap4evb.c 2011-08-26 12:45:47.000000000 +0900
@@ -1411,6 +1411,7 @@ static void __init ap4evb_init(void)
sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
hdmi_init_pm_clock();
fsi_init_pm_clock();
--- 0012/arch/arm/mach-shmobile/board-mackerel.c
+++ work/arch/arm/mach-shmobile/board-mackerel.c 2011-08-26 12:45:47.000000000 +0900
@@ -1596,6 +1596,7 @@ static void __init mackerel_init(void)
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
#endif
sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
hdmi_init_pm_clock();
sh7372_pm_init();
--- 0012/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ work/arch/arm/mach-shmobile/include/mach/sh7372.h 2011-08-26 12:46:51.000000000 +0900
@@ -491,6 +491,7 @@ static inline struct sh7372_pm_domain *t
extern struct sh7372_pm_domain sh7372_a4lc;
extern struct sh7372_pm_domain sh7372_a4mp;
extern struct sh7372_pm_domain sh7372_d4;
+extern struct sh7372_pm_domain sh7372_a4r;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
extern struct sh7372_pm_domain sh7372_a3sp;
@@ -504,4 +505,7 @@ extern void sh7372_add_device_to_domain(
#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
#endif /* CONFIG_PM */
+extern void sh7372_intcs_suspend(void);
+extern void sh7372_intcs_resume(void);
+
#endif /* __ASM_SH7372_H__ */
--- 0001/arch/arm/mach-shmobile/intc-sh7372.c
+++ work/arch/arm/mach-shmobile/intc-sh7372.c 2011-08-26 12:45:47.000000000 +0900
@@ -607,9 +607,16 @@ static void intcs_demux(unsigned int irq
generic_handle_irq(intcs_evt2irq(evtcodeas));
}
+static void __iomem *intcs_ffd2;
+static void __iomem *intcs_ffd5;
+
void __init sh7372_init_irq(void)
{
- void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+ void __iomem *intevtsa;
+
+ intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
+ intevtsa = intcs_ffd2 + 0x100;
+ intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
register_intc_controller(&intca_desc);
register_intc_controller(&intcs_desc);
@@ -618,3 +625,46 @@ void __init sh7372_init_irq(void)
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
}
+
+static unsigned short ffd2[0x200];
+static unsigned short ffd5[0x100];
+
+void sh7372_intcs_suspend(void)
+{
+ int k;
+
+ for (k = 0x00; k <= 0x30; k += 4)
+ ffd2[k] = __raw_readw(intcs_ffd2 + k);
+
+ for (k = 0x80; k <= 0xb0; k += 4)
+ ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+ for (k = 0x180; k <= 0x188; k += 4)
+ ffd2[k] = __raw_readb(intcs_ffd2 + k);
+
+ for (k = 0x00; k <= 0x3c; k += 4)
+ ffd5[k] = __raw_readw(intcs_ffd5 + k);
+
+ for (k = 0x80; k <= 0x9c; k += 4)
+ ffd5[k] = __raw_readb(intcs_ffd5 + k);
+}
+
+void sh7372_intcs_resume(void)
+{
+ int k;
+
+ for (k = 0x00; k <= 0x30; k += 4)
+ __raw_writew(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x80; k <= 0xb0; k += 4)
+ __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x180; k <= 0x188; k += 4)
+ __raw_writeb(ffd2[k], intcs_ffd2 + k);
+
+ for (k = 0x00; k <= 0x3c; k += 4)
+ __raw_writew(ffd5[k], intcs_ffd5 + k);
+
+ for (k = 0x80; k <= 0x9c; k += 4)
+ __raw_writeb(ffd5[k], intcs_ffd5 + k);
+}
--- 0012/arch/arm/mach-shmobile/pm-sh7372.c
+++ work/arch/arm/mach-shmobile/pm-sh7372.c 2011-08-26 12:47:24.000000000 +0900
@@ -44,6 +44,7 @@
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
#define SBAR 0xe6180020
+#define WUPRMSK 0xe6180028
#define WUPSMSK 0xe618002c
#define WUPSMSK2 0xe6180048
#define PSTR 0xe6180080
@@ -152,8 +153,21 @@ static int pd_power_down_a3rv(struct gen
return ret;
}
+static int pd_power_up_a4lc(struct generic_pm_domain *genpd)
+{
+ int ret = pd_power_up(genpd);
+
+ /* force A4R to activate INTCS that may be needed by LCDCs */
+ pm_genpd_poweron(&sh7372_a4r.genpd);
+
+ return ret;
+}
+
static int pd_power_down_a4lc(struct generic_pm_domain *genpd)
{
+ /* try to power down A4R since LCDCs now are off */
+ genpd_queue_power_off_work(&sh7372_a4r.genpd);
+
/* only power down A4LC if A3RV is off */
if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift)))
return pd_power_down(genpd);
@@ -161,6 +175,28 @@ static int pd_power_down_a4lc(struct gen
return -EBUSY;
}
+static int pd_power_up_a4r(struct generic_pm_domain *genpd)
+{
+ int ret = pd_power_up(genpd);
+
+ sh7372_intcs_resume();
+
+ return ret;
+}
+
+static int pd_power_down_a4r(struct generic_pm_domain *genpd)
+{
+ unsigned long lcdc_bits = (1 << 0) | (1 << 17);
+
+ /* refuse A4R power down if LCDCs are operating - they need INTCS */
+ if ((__raw_readl(MSTPSR1) & lcdc_bits) != lcdc_bits)
+ return -EBUSY;
+
+ sh7372_intcs_suspend();
+ __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
+
+ return pd_power_down(genpd);
+}
static bool pd_active_wakeup(struct device *dev)
{
return true;
@@ -175,17 +211,26 @@ void sh7372_init_pm_domain(struct sh7372
genpd->start_device = pm_clk_resume;
genpd->active_wakeup = pd_active_wakeup;
+ /* default power up/down functions */
+ genpd->power_off = pd_power_down;
+ genpd->power_on = pd_power_up;
+
+ /* execute default power on */
+ genpd->power_on(&sh7372_pd->genpd);
+
if (sh7372_pd = &sh7372_a4lc) {
genpd->power_off = pd_power_down_a4lc;
- genpd->power_on = pd_power_up;
+ genpd->power_on = pd_power_up_a4lc;
+ } else if (sh7372_pd = &sh7372_a4r) {
+ genpd->power_off = pd_power_down_a4r;
+ genpd->power_on = pd_power_up_a4r;
} else if (sh7372_pd = &sh7372_a3rv) {
genpd->power_off = pd_power_down_a3rv;
genpd->power_on = pd_power_up_a3rv;
- } else {
- genpd->power_off = pd_power_down;
- genpd->power_on = pd_power_up;
}
- genpd->power_on(&sh7372_pd->genpd);
+
+ if ((sh7372_pd = &sh7372_a3rv) || (sh7372_pd = &sh7372_a3ri))
+ pm_genpd_add_subdomain(&sh7372_a4r.genpd, &sh7372_pd->genpd);
}
void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
@@ -212,6 +257,10 @@ struct sh7372_pm_domain sh7372_d4 = {
.bit_shift = 3,
};
+struct sh7372_pm_domain sh7372_a4r = {
+ .bit_shift = 5,
+};
+
struct sh7372_pm_domain sh7372_a3rv = {
.bit_shift = 6,
};
--- 0012/arch/arm/mach-shmobile/setup-sh7372.c
+++ work/arch/arm/mach-shmobile/setup-sh7372.c 2011-08-26 12:45:47.000000000 +0900
@@ -990,6 +990,7 @@ void __init sh7372_add_standard_devices(
sh7372_init_pm_domain(&sh7372_a4lc);
sh7372_init_pm_domain(&sh7372_a4mp);
sh7372_init_pm_domain(&sh7372_d4);
+ sh7372_init_pm_domain(&sh7372_a4r);
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a3sg);
@@ -1017,6 +1018,12 @@ void __init sh7372_add_standard_devices(
sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
+ sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
}
void __init sh7372_add_early_devices(void)
^ permalink raw reply
* [PATCH 02/03] ARM: mach-shmobile: sh7372 A3SP support
From: Magnus Damm @ 2011-08-26 6:43 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110630094710.10442.59532.sendpatchset@t400s>
From: Magnus Damm <damm@opensource.se>
This patch adds sh7372 A3SP power domain support.
The sh7372 A3SP hardware power domain contains a
wide range of I/O devices. The list of I/O devices
include SCIF serial ports, DMA Engine hardware,
SD and MMC controller hardware, USB controllers
and I2C master controllers.
This patch adds the A3SP low level code which
powers the hardware power domain on and off. It
also ties in platform devices to the pm domain
support code.
It is worth noting that the serial console is
hooked up to SCIFA0 on most sh7372 boards, and
the SCIFA0 port is included in the A3SP hardware
power domain. For this reason we cannot output
debug messages from the low level power control
code in the case of A3SP.
This patch seems to work quite fine except for
Suspend-to-RAM that is broken with this patch
applied. QoS support is needed in drivers before
we can enable the A3SP power control on the fly.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Depends on USB-DMAC patches by Morimoto-san.
arch/arm/mach-shmobile/board-ap4evb.c | 4 ++++
arch/arm/mach-shmobile/board-mackerel.c | 8 ++++++++
arch/arm/mach-shmobile/include/mach/sh7372.h | 1 +
arch/arm/mach-shmobile/pm-sh7372.c | 19 +++++++++++++++----
arch/arm/mach-shmobile/setup-sh7372.c | 14 ++++++++++++++
5 files changed, 42 insertions(+), 4 deletions(-)
--- 0006/arch/arm/mach-shmobile/board-ap4evb.c
+++ work/arch/arm/mach-shmobile/board-ap4evb.c 2011-08-26 12:44:29.000000000 +0900
@@ -1408,6 +1408,10 @@ static void __init ap4evb_init(void)
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+
hdmi_init_pm_clock();
fsi_init_pm_clock();
sh7372_pm_init();
--- 0006/arch/arm/mach-shmobile/board-mackerel.c
+++ work/arch/arm/mach-shmobile/board-mackerel.c 2011-08-26 12:44:29.000000000 +0900
@@ -1588,6 +1588,14 @@ static void __init mackerel_init(void)
sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+#endif
+ sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
hdmi_init_pm_clock();
sh7372_pm_init();
--- 0004/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ work/arch/arm/mach-shmobile/include/mach/sh7372.h 2011-08-26 12:44:29.000000000 +0900
@@ -493,6 +493,7 @@ extern struct sh7372_pm_domain sh7372_a4
extern struct sh7372_pm_domain sh7372_d4;
extern struct sh7372_pm_domain sh7372_a3rv;
extern struct sh7372_pm_domain sh7372_a3ri;
+extern struct sh7372_pm_domain sh7372_a3sp;
extern struct sh7372_pm_domain sh7372_a3sg;
extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
--- 0011/arch/arm/mach-shmobile/pm-sh7372.c
+++ work/arch/arm/mach-shmobile/pm-sh7372.c 2011-08-26 12:44:29.000000000 +0900
@@ -92,8 +92,10 @@ static int pd_power_down(struct generic_
}
}
- pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+ /* we cannot output debug message for A3SP */
+ if (genpd != &sh7372_a3sp.genpd)
+ pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
+ mask, __raw_readl(PSTR));
return 0;
}
@@ -122,8 +124,10 @@ static int pd_power_up(struct generic_pm
ret = -EIO;
out:
- pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
- mask, __raw_readl(PSTR));
+ /* we cannot output debug message for A3SP */
+ if (genpd != &sh7372_a3sp.genpd)
+ pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
+ mask, __raw_readl(PSTR));
return ret;
}
@@ -216,6 +220,10 @@ struct sh7372_pm_domain sh7372_a3ri = {
.bit_shift = 8,
};
+struct sh7372_pm_domain sh7372_a3sp = {
+ .bit_shift = 11,
+};
+
struct sh7372_pm_domain sh7372_a3sg = {
.bit_shift = 13,
};
@@ -450,6 +458,9 @@ void __init sh7372_pm_init(void)
__raw_writel(0x0000a501, DBGREG9);
__raw_writel(0x00000000, DBGREG1);
+ /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
+ __raw_writel(0, PDNSEL);
+
sh7372_suspend_init();
sh7372_cpuidle_init();
}
--- 0004/arch/arm/mach-shmobile/setup-sh7372.c
+++ work/arch/arm/mach-shmobile/setup-sh7372.c 2011-08-26 12:44:29.000000000 +0900
@@ -993,6 +993,7 @@ void __init sh7372_add_standard_devices(
sh7372_init_pm_domain(&sh7372_a3rv);
sh7372_init_pm_domain(&sh7372_a3ri);
sh7372_init_pm_domain(&sh7372_a3sg);
+ sh7372_init_pm_domain(&sh7372_a3sp);
platform_add_devices(sh7372_early_devices,
ARRAY_SIZE(sh7372_early_devices));
@@ -1003,6 +1004,19 @@ void __init sh7372_add_standard_devices(
sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
+ sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
}
void __init sh7372_add_early_devices(void)
^ permalink raw reply
* [PATCH 01/03] ARM: mach-shmobile: sh7372 A3SM support
From: Magnus Damm @ 2011-08-26 6:43 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
This patch adds sh7372 A3SM power domain support.
The sh7372 A3SM hardware power domain contains the
ARM Cortex-A8 CPU Core including L2 cache. This
sleep mode can be seen as a one step deeper sleep
mode from the already existing Core Standby mode.
To wake up from A3SM sleep only a few wakeup sources
are supported - so the regular INTC controller will
not be able to help us unfortunately.
The code in this patch will enter A3SM sleep via the
regular Suspend-to-RAM interface in the case of only
wakeups supported by A3SM are enabled. If unsupported
wakeups are enabled then Core Standby will be used
instead.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
To be able to enter A3SM you need to apply MSTP patches
for MSIOF, CMT and USB-DMAC. You may also have to
disable the serial console on the kernel command line.
arch/arm/mach-shmobile/include/mach/common.h | 3
arch/arm/mach-shmobile/pm-sh7372.c | 209 +++++++++++++++++++++++++-
arch/arm/mach-shmobile/sleep-sh7372.S | 55 ++++++
3 files changed, 256 insertions(+), 11 deletions(-)
--- 0002/arch/arm/mach-shmobile/include/mach/common.h
+++ work/arch/arm/mach-shmobile/include/mach/common.h 2011-08-26 13:02:46.000000000 +0900
@@ -35,7 +35,8 @@ extern void sh7372_add_standard_devices(
extern void sh7372_clock_init(void);
extern void sh7372_pinmux_init(void);
extern void sh7372_pm_init(void);
-extern void sh7372_resume_core_standby(void);
+extern void sh7372_resume_core_standby_a3sm(void);
+extern int sh7372_do_idle_a3sm(unsigned long unused);
extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
--- 0002/arch/arm/mach-shmobile/pm-sh7372.c
+++ work/arch/arm/mach-shmobile/pm-sh7372.c 2011-08-26 13:03:38.000000000 +0900
@@ -18,6 +18,8 @@
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/bitrev.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/tlbflush.h>
@@ -25,14 +27,48 @@
#include <mach/common.h>
#include <mach/sh7372.h>
-#define SMFRAM 0xe6a70000
+/* DBG */
+#define DBGREG1 0xe6100020
+#define DBGREG9 0xe6100040
+
+/* CPGA */
#define SYSTBCR 0xe6150024
-#define SBAR 0xe6180020
-#define APARMBAREA 0xe6f10020
+#define MSTPSR0 0xe6150030
+#define MSTPSR1 0xe6150038
+#define MSTPSR2 0xe6150040
+#define MSTPSR3 0xe6150048
+#define MSTPSR4 0xe615004c
+#define PLLC01STPCR 0xe61500c8
+/* SYSC */
#define SPDCR 0xe6180008
#define SWUCR 0xe6180014
+#define SBAR 0xe6180020
+#define WUPSMSK 0xe618002c
+#define WUPSMSK2 0xe6180048
#define PSTR 0xe6180080
+#define WUPSFAC 0xe6180098
+#define IRQCR 0xe618022c
+#define IRQCR2 0xe6180238
+#define IRQCR3 0xe6180244
+#define IRQCR4 0xe6180248
+#define PDNSEL 0xe6180254
+
+/* INTC */
+#define ICR1A 0xe6900000
+#define ICR2A 0xe6900004
+#define ICR3A 0xe6900008
+#define ICR4A 0xe690000c
+#define INTMSK00A 0xe6900040
+#define INTMSK10A 0xe6900044
+#define INTMSK20A 0xe6900048
+#define INTMSK30A 0xe690004c
+
+/* MFIS */
+#define SMFRAM 0xe6a70000
+
+/* AP-System Core */
+#define APARMBAREA 0xe6f10020
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
@@ -195,7 +231,7 @@ static int sh7372_do_idle_core_standby(u
static void sh7372_enter_core_standby(void)
{
/* set reset vector, translate 4k */
- __raw_writel(__pa(sh7372_resume_core_standby), SBAR);
+ __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
__raw_writel(0, APARMBAREA);
/* enter sleep mode with SYSTBCR to 0x10 */
@@ -207,7 +243,151 @@ static void sh7372_enter_core_standby(vo
__raw_writel(0, SBAR);
}
+static void sh7372_enter_a3sm_common(int pllc0_on)
+{
+ /* set reset vector, translate 4k */
+ __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
+ __raw_writel(0, APARMBAREA);
+
+ if (pllc0_on)
+ __raw_writel(0, PLLC01STPCR);
+ else
+ __raw_writel(1 << 28, PLLC01STPCR);
+
+ __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */
+ __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
+ cpu_suspend(0, sh7372_do_idle_a3sm);
+ __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
+
+ /* disable reset vector translation */
+ __raw_writel(0, SBAR);
+}
+
+static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p)
+{
+ unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
+ unsigned long msk, msk2;
+
+ /* check active clocks to determine potential wakeup sources */
+
+ mstpsr0 = __raw_readl(MSTPSR0);
+ if ((mstpsr0 & 0x00000003) != 0x00000003) {
+ pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
+ return 0;
+ }
+
+ mstpsr1 = __raw_readl(MSTPSR1);
+ if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
+ pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
+ return 0;
+ }
+
+ mstpsr2 = __raw_readl(MSTPSR2);
+ if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
+ pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
+ return 0;
+ }
+
+ mstpsr3 = __raw_readl(MSTPSR3);
+ if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
+ pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
+ return 0;
+ }
+
+ mstpsr4 = __raw_readl(MSTPSR4);
+ if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
+ pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
+ return 0;
+ }
+
+ msk = 0;
+ msk2 = 0;
+
+ /* make bitmaps of limited number of wakeup sources */
+
+ if ((mstpsr2 & (1 << 23)) = 0) /* SPU2 */
+ msk |= 1 << 31;
+
+ if ((mstpsr2 & (1 << 12)) = 0) /* MFI_MFIM */
+ msk |= 1 << 21;
+
+ if ((mstpsr4 & (1 << 3)) = 0) /* KEYSC */
+ msk |= 1 << 2;
+
+ if ((mstpsr1 & (1 << 24)) = 0) /* CMT0 */
+ msk |= 1 << 1;
+
+ if ((mstpsr3 & (1 << 29)) = 0) /* CMT1 */
+ msk |= 1 << 1;
+
+ if ((mstpsr4 & (1 << 0)) = 0) /* CMT2 */
+ msk |= 1 << 1;
+
+ if ((mstpsr2 & (1 << 13)) = 0) /* MFI_MFIS */
+ msk2 |= 1 << 17;
+
+ *mskp = msk;
+ *msk2p = msk2;
+
+ return 1;
+}
+
+static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
+{
+ u16 tmp, irqcr1, irqcr2;
+ int k;
+
+ irqcr1 = 0;
+ irqcr2 = 0;
+
+ /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
+ for (k = 0; k <= 7; k++) {
+ tmp = (icr >> ((7 - k) * 4)) & 0xf;
+ irqcr1 |= (tmp & 0x03) << (k * 2);
+ irqcr2 |= (tmp >> 2) << (k * 2);
+ }
+
+ *irqcr1p = irqcr1;
+ *irqcr2p = irqcr2;
+}
+
+static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
+{
+ u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
+ unsigned long tmp;
+
+ /* read IRQ0A -> IRQ15A mask */
+ tmp = bitrev8(__raw_readb(INTMSK00A));
+ tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
+
+ /* setup WUPSMSK from clocks and external IRQ mask */
+ msk = (~msk & 0xc030000f) | (tmp << 4);
+ __raw_writel(msk, WUPSMSK);
+
+ /* propage level/edge trigger for external IRQ 0->15 */
+ sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
+ sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
+ __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
+ __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
+
+ /* read IRQ16A -> IRQ31A mask */
+ tmp = bitrev8(__raw_readb(INTMSK20A));
+ tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
+
+ /* setup WUPSMSK2 from clocks and external IRQ mask */
+ msk2 = (~msk2 & 0x00030000) | tmp;
+ __raw_writel(msk2, WUPSMSK2);
+
+ /* propage level/edge trigger for external IRQ 16->31 */
+ sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
+ sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
+ __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
+ __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
+}
+
+
#ifdef CONFIG_CPU_IDLE
+
static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
{
struct cpuidle_state *state;
@@ -235,9 +415,25 @@ static void sh7372_cpuidle_init(void) {}
#endif
#ifdef CONFIG_SUSPEND
+
static int sh7372_enter_suspend(suspend_state_t suspend_state)
{
- sh7372_enter_core_standby();
+ unsigned long msk, msk2;
+
+ /* check active clocks to determine potential wakeup sources */
+ if (sh7372_a3sm_valid(&msk, &msk2)) {
+
+ /* convert INTC mask and sense to SYSC mask and sense */
+ sh7372_setup_a3sm(msk, msk2);
+
+ /* enter A3SM sleep with PLLC0 off */
+ pr_debug("entering A3SM\n");
+ sh7372_enter_a3sm_common(0);
+ } else {
+ /* default to Core Standby that supports all wakeup sources */
+ pr_debug("entering Core Standby\n");
+ sh7372_enter_core_standby();
+ }
return 0;
}
@@ -249,9 +445,6 @@ static void sh7372_suspend_init(void)
static void sh7372_suspend_init(void) {}
#endif
-#define DBGREG1 0xe6100020
-#define DBGREG9 0xe6100040
-
void __init sh7372_pm_init(void)
{
/* enable DBG hardware block to kick SYSC */
--- 0002/arch/arm/mach-shmobile/sleep-sh7372.S
+++ work/arch/arm/mach-shmobile/sleep-sh7372.S 2011-08-26 13:19:38.000000000 +0900
@@ -36,7 +36,58 @@
.align 12
.text
- .global sh7372_resume_core_standby
-sh7372_resume_core_standby:
+ .global sh7372_resume_core_standby_a3sm
+sh7372_resume_core_standby_a3sm:
ldr pc, 1f
1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
+
+ .global sh7372_do_idle_a3sm
+sh7372_do_idle_a3sm:
+ /*
+ * Clear the SCTLR.C bit to prevent further data cache
+ * allocation. Clearing SCTLR.C would make all the data accesses
+ * strongly ordered and would not hit the cache.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #(1 << 2) @ Disable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ /* disable L2 cache in the aux control register */
+ mrc p15, 0, r10, c1, c0, 1
+ bic r10, r10, #2
+ mcr p15, 0, r10, c1, c0, 1
+
+ /*
+ * Invalidate data cache again.
+ */
+ ldr r1, kernel_flush
+ blx r1
+ /*
+ * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+ * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+ * This sequence switches back to ARM. Note that .align may insert a
+ * nop: bx pc needs to be word-aligned in order to work.
+ */
+ THUMB( .thumb )
+ THUMB( .align )
+ THUMB( bx pc )
+ THUMB( nop )
+ .arm
+
+ /* Data memory barrier and Data sync barrier */
+ dsb
+ dmb
+
+#define SPDCR 0xe6180008
+#define A3SM (1 << 12)
+
+ /* A3SM power down */
+ ldr r0, =SPDCR
+ ldr r1, £SM
+ str r1, [r0]
+1:
+ b 1b
+
+kernel_flush:
+ .word v7_flush_dcache_all
^ permalink raw reply
* [PATCH 00/03] ARM: mach-shmobile: sh7372 power domain update
From: Magnus Damm @ 2011-08-26 6:43 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <20110630094653.10442.68817.sendpatchset@t400s>
ARM: mach-shmobile: sh7372 power domain update
[PATCH 01/03] ARM: mach-shmobile: sh7372 A3SM support
[PATCH 02/03] ARM: mach-shmobile: sh7372 A3SP support
[PATCH 03/03] ARM: mach-shmobile: sh7372 A4R support
These patches add support for the A3SM, A3SP and A4R
power domains included in the sh7372 SoC. More work
in needed with QoS for I/O devices and CPUIdle with
A3SM together with future A4S power domain support.
Testing needed, especiall WRT to Suspend-to-RAM!
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/board-ap4evb.c | 5
arch/arm/mach-shmobile/board-mackerel.c | 9
arch/arm/mach-shmobile/include/mach/common.h | 3
arch/arm/mach-shmobile/include/mach/sh7372.h | 5
arch/arm/mach-shmobile/intc-sh7372.c | 52 ++++
arch/arm/mach-shmobile/pm-sh7372.c | 287 ++++++++++++++++++++++++--
arch/arm/mach-shmobile/setup-sh7372.c | 21 +
arch/arm/mach-shmobile/sleep-sh7372.S | 55 ++++
8 files changed, 416 insertions(+), 21 deletions(-)
^ permalink raw reply
* Re: Can not compile Ecovec board
From: Nobuhiro Iwamatsu @ 2011-08-26 6:18 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87aaaxou97.wl%kuninori.morimoto.gx@renesas.com>
2011/8/26 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>:
> 2011/8/26 Magnus Damm <magnus.damm@gmail.com>:
>> On Fri, Aug 26, 2011 at 1:30 PM, Nobuhiro Iwamatsu <iwamatsu@nigauri.org> wrote:
>>> This was already revised in linux-next tree.
>>
>> That's great, but shouldn't build fixes be solved for the RC kernels
>> if possible?
>>
>> People really need to learn how to separate build fixes from new
>> development, otherwise everything will turn to shit.
>>
>
> The commitment to revise this problem seems to be taken in with
> signed-off of Paul by repository of Paul.
> I think that It will be up to Paul whether this is taken-in in rc3.
> Paul, do you think about this?
>
Sorry, commit is not in Paul's repository.
This is in Paul Gortmaker's tree.
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
^ permalink raw reply
* Re: Can not compile Ecovec board
From: Nobuhiro Iwamatsu @ 2011-08-26 6:05 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87aaaxou97.wl%kuninori.morimoto.gx@renesas.com>
2011/8/26 Magnus Damm <magnus.damm@gmail.com>:
> On Fri, Aug 26, 2011 at 1:30 PM, Nobuhiro Iwamatsu <iwamatsu@nigauri.org> wrote:
>> This was already revised in linux-next tree.
>
> That's great, but shouldn't build fixes be solved for the RC kernels
> if possible?
>
> People really need to learn how to separate build fixes from new
> development, otherwise everything will turn to shit.
>
The commitment to revise this problem seems to be taken in with
signed-off of Paul by repository of Paul.
I think that It will be up to Paul whether this is taken-in in rc3.
Paul, do you think about this?
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
^ permalink raw reply
* [PATCH] ARM: mach-shmobile: sh7372 CMT3 and CMT4 clock support
From: Magnus Damm @ 2011-08-26 5:28 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Add clock control support for sh7372 CMT hardware blocks.
No upstream sh7372 boards are making use of CMT3 + CMT4,
but the sh7372 hardware happens to come out of reset with
all CMT MSTP clocks _enabled_, so to save power we need
to implement a fix in software to shut down unused clocks.
This patch relies on the recently merged
794d78f drivers: sh: late disabling of clocks V2
to make sure the unused clocks get disabled as expected.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
This patch is needed by upcoming A3SM sleep mode support
code that can only enter deep sleep in case most clocks
are disabled - including these CMT clocks.
arch/arm/mach-shmobile/clock-sh7372.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
--- 0008/arch/arm/mach-shmobile/clock-sh7372.c
+++ work/arch/arm/mach-shmobile/clock-sh7372.c 2011-08-26 13:50:55.000000000 +0900
@@ -512,7 +512,8 @@ enum { MSTP001, MSTP000,
MSTP218, MSTP217, MSTP216, MSTP214, MSTP208,
MSTP207, MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
- MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406, MSTP403,
+ MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
+ MSTP405, MSTP404, MSTP403,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
@@ -563,6 +564,8 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
[MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
+ [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
+ [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
};
@@ -663,6 +666,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
+ CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
+ CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
^ permalink raw reply
* [PATCH] ARM: mach-shmobile: sh7372 MSIOF clock support
From: Magnus Damm @ 2011-08-26 5:25 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Add clock control support for sh7372 MSIOF hardware blocks.
No upstream sh7372 boards are making use of MSIOF0->2,
but the sh7372 hardware happens to come out of reset with
all MSIOF MSTP clocks _enabled_, so to save power we need
to implement a fix in software to shut down unused clocks.
This patch relies on the recently merged
794d78f drivers: sh: late disabling of clocks V2
to make sure the unused clocks get disabled as expected.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
This patch is needed by upcoming A3SM sleep mode support
code that can only enter deep sleep in case most clocks
are disabled - including these MSIOF clocks.
arch/arm/mach-shmobile/clock-sh7372.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
--- 0007/arch/arm/mach-shmobile/clock-sh7372.c
+++ work/arch/arm/mach-shmobile/clock-sh7372.c 2011-08-26 13:34:25.000000000 +0900
@@ -503,14 +503,14 @@ static struct clk *late_main_clks[] = {
&sh7372_fsidivb_clk,
};
-enum { MSTP001,
+enum { MSTP001, MSTP000,
MSTP131, MSTP130,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
MSTP118, MSTP117, MSTP116, MSTP113,
MSTP106, MSTP101, MSTP100,
MSTP223,
- MSTP214, MSTP218, MSTP217, MSTP216,
- MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+ MSTP218, MSTP217, MSTP216, MSTP214, MSTP208,
+ MSTP207, MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406, MSTP403,
MSTP_NR };
@@ -520,6 +520,7 @@ enum { MSTP001,
static struct clk mstp_clks[MSTP_NR] = {
[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
+ [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
@@ -539,8 +540,10 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
[MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
[MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
+ [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+ [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
@@ -611,6 +614,7 @@ static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
+ CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
@@ -632,8 +636,10 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
+ CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
+ CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
^ permalink raw reply
* Re: Can not compile Ecovec board
From: Kuninori Morimoto @ 2011-08-26 5:24 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87aaaxou97.wl%kuninori.morimoto.gx@renesas.com>
Hi again
> I checked linux-next and solution patches.
> It are in current paul/sh-latest branch I think.
>
> If I hand merge it to linus/master branch, I could build.
>
> Is this merge timing issue ?
paul/sh-fixes-for-linus was good branch for linus/master
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* Re: Can not compile Ecovec board
From: Kuninori Morimoto @ 2011-08-26 5:12 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87aaaxou97.wl%kuninori.morimoto.gx@renesas.com>
Hi Magnus, Iwamatsu-san, and SH-ML
> > This was already revised in linux-next tree.
>
> That's great, but shouldn't build fixes be solved for the RC kernels
> if possible?
>
> People really need to learn how to separate build fixes from new
> development, otherwise everything will turn to shit.
Thank you for your help
I checked linux-next and solution patches.
It are in current paul/sh-latest branch I think.
If I hand merge it to linus/master branch, I could build.
Is this merge timing issue ?
Best regards
---
Kuninori Morimoto
^ permalink raw reply
* [PATCH][RESEND] ARM: mach-shmobile: sh7372 generic suspend/resume support
From: Magnus Damm @ 2011-08-26 5:12 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Convert the sh7372 Core Standby code to make use
of the new generic ARM cpu suspend/resume code.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/include/mach/common.h | 3
arch/arm/mach-shmobile/pm-sh7372.c | 38 +---
arch/arm/mach-shmobile/sleep-sh7372.S | 230 --------------------------
3 files changed, 24 insertions(+), 247 deletions(-)
--- 0001/arch/arm/mach-shmobile/include/mach/common.h
+++ work/arch/arm/mach-shmobile/include/mach/common.h 2011-07-06 18:11:38.000000000 +0900
@@ -35,8 +35,7 @@ extern void sh7372_add_standard_devices(
extern void sh7372_clock_init(void);
extern void sh7372_pinmux_init(void);
extern void sh7372_pm_init(void);
-extern void sh7372_cpu_suspend(void);
-extern void sh7372_cpu_resume(void);
+extern void sh7372_resume_core_standby(void);
extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
--- 0001/arch/arm/mach-shmobile/pm-sh7372.c
+++ work/arch/arm/mach-shmobile/pm-sh7372.c 2011-07-06 18:34:40.000000000 +0900
@@ -18,6 +18,7 @@
#include <asm/system.h>
#include <asm/io.h>
#include <asm/tlbflush.h>
+#include <asm/suspend.h>
#include <mach/common.h>
#define SMFRAM 0xe6a70000
@@ -25,30 +26,25 @@
#define SBAR 0xe6180020
#define APARMBAREA 0xe6f10020
-static void sh7372_enter_core_standby(void)
+static int sh7372_do_idle_core_standby(unsigned long unused)
{
- void __iomem *smfram = (void __iomem *)SMFRAM;
-
- __raw_writel(0, APARMBAREA); /* translate 4k */
- __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
- __raw_writel(0x10, SYSTBCR); /* enable core standby */
-
- __raw_writel(0, smfram + 0x3c); /* clear page table address */
-
- sh7372_cpu_suspend();
- cpu_init();
-
- /* if page table address is non-NULL then we have been powered down */
- if (__raw_readl(smfram + 0x3c)) {
- __raw_writel(__raw_readl(smfram + 0x40),
- __va(__raw_readl(smfram + 0x3c)));
+ cpu_do_idle(); /* WFI when SYSTBCR = 0x10 -> Core Standby */
+ return 0;
+}
- flush_tlb_all();
- set_cr(__raw_readl(smfram + 0x38));
- }
+static void sh7372_enter_core_standby(void)
+{
+ /* set reset vector, translate 4k */
+ __raw_writel(__pa(sh7372_resume_core_standby), SBAR);
+ __raw_writel(0, APARMBAREA);
+
+ /* enter sleep mode with SYSTBCR to 0x10 */
+ __raw_writel(0x10, SYSTBCR);
+ cpu_suspend(0, sh7372_do_idle_core_standby);
+ __raw_writel(0, SYSTBCR);
- __raw_writel(0, SYSTBCR); /* disable core standby */
- __raw_writel(0, SBAR); /* disable reset vector translation */
+ /* disable reset vector translation */
+ __raw_writel(0, SBAR);
}
#ifdef CONFIG_CPU_IDLE
--- 0001/arch/arm/mach-shmobile/sleep-sh7372.S
+++ work/arch/arm/mach-shmobile/sleep-sh7372.S 2011-07-06 18:32:44.000000000 +0900
@@ -30,231 +30,13 @@
*/
#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
#include <asm/assembler.h>
-#define SMFRAM 0xe6a70000
-
- .align
-kernel_flush:
- .word v7_flush_dcache_all
-
- .align 3
-ENTRY(sh7372_cpu_suspend)
- stmfd sp!, {r0-r12, lr} @ save registers on stack
-
- ldr r8, =SMFRAM
-
- mov r4, sp @ Store sp
- mrs r5, spsr @ Store spsr
- mov r6, lr @ Store lr
- stmia r8!, {r4-r6}
-
- mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
- mrc p15, 0, r5, c2, c0, 0 @ TTBR0
- mrc p15, 0, r6, c2, c0, 1 @ TTBR1
- mrc p15, 0, r7, c2, c0, 2 @ TTBCR
- stmia r8!, {r4-r7}
-
- mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
- mrc p15, 0, r5, c10, c2, 0 @ PRRR
- mrc p15, 0, r6, c10, c2, 1 @ NMRR
- stmia r8!,{r4-r6}
-
- mrc p15, 0, r4, c13, c0, 1 @ Context ID
- mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
- mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
- mrs r7, cpsr @ Store current cpsr
- stmia r8!, {r4-r7}
-
- mrc p15, 0, r4, c1, c0, 0 @ save control register
- stmia r8!, {r4}
-
- /*
- * jump out to kernel flush routine
- * - reuse that code is better
- * - it executes in a cached space so is faster than refetch per-block
- * - should be faster and will change with kernel
- * - 'might' have to copy address, load and jump to it
- * Flush all data from the L1 data cache before disabling
- * SCTLR.C bit.
- */
- ldr r1, kernel_flush
- mov lr, pc
- bx r1
-
- /*
- * Clear the SCTLR.C bit to prevent further data cache
- * allocation. Clearing SCTLR.C would make all the data accesses
- * strongly ordered and would not hit the cache.
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #(1 << 2) @ Disable the C bit
- mcr p15, 0, r0, c1, c0, 0
- isb
-
- /*
- * Invalidate L1 data cache. Even though only invalidate is
- * necessary exported flush API is used here. Doing clean
- * on already clean cache would be almost NOP.
- */
- ldr r1, kernel_flush
- blx r1
- /*
- * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
- * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
- * This sequence switches back to ARM. Note that .align may insert a
- * nop: bx pc needs to be word-aligned in order to work.
- */
- THUMB( .thumb )
- THUMB( .align )
- THUMB( bx pc )
- THUMB( nop )
- .arm
-
- /* Data memory barrier and Data sync barrier */
- dsb
- dmb
-
-/*
- * =================- * = WFI instruction => Enter idle =
- * =================- */
- wfi @ wait for interrupt
-
-/*
- * =================- * = Resume path for non-OFF modes =
- * =================- */
- mrc p15, 0, r0, c1, c0, 0
- tst r0, #(1 << 2) @ Check C bit enabled?
- orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
- mcreq p15, 0, r0, c1, c0, 0
- isb
-
-/*
- * =================- * = Exit point from non-OFF modes =
- * =================- */
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
-
- .pool
-
.align 12
.text
- .global sh7372_cpu_resume
-sh7372_cpu_resume:
-
- mov r1, #0
- /*
- * Invalidate all instruction caches to PoU
- * and flush branch target cache
- */
- mcr p15, 0, r1, c7, c5, 0
-
- ldr r3, =SMFRAM
-
- ldmia r3!, {r4-r6}
- mov sp, r4 @ Restore sp
- msr spsr_cxsf, r5 @ Restore spsr
- mov lr, r6 @ Restore lr
-
- ldmia r3!, {r4-r7}
- mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
- mcr p15, 0, r5, c2, c0, 0 @ TTBR0
- mcr p15, 0, r6, c2, c0, 1 @ TTBR1
- mcr p15, 0, r7, c2, c0, 2 @ TTBCR
-
- ldmia r3!,{r4-r6}
- mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
- mcr p15, 0, r5, c10, c2, 0 @ PRRR
- mcr p15, 0, r6, c10, c2, 1 @ NMRR
-
- ldmia r3!,{r4-r7}
- mcr p15, 0, r4, c13, c0, 1 @ Context ID
- mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
- mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
- msr cpsr, r7 @ store cpsr
-
- /* Starting to enable MMU here */
- mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
- /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
- and r7, #0x7
- cmp r7, #0x0
- beq usettbr0
-ttbr_error:
- /*
- * More work needs to be done to support N[0:2] value other than 0
- * So looping here so that the error can be detected
- */
- b ttbr_error
-
- .align
-cache_pred_disable_mask:
- .word 0xFFFFE7FB
-ttbrbit_mask:
- .word 0xFFFFC000
-table_index_mask:
- .word 0xFFF00000
-table_entry:
- .word 0x00000C02
-usettbr0:
-
- mrc p15, 0, r2, c2, c0, 0
- ldr r5, ttbrbit_mask
- and r2, r5
- mov r4, pc
- ldr r5, table_index_mask
- and r4, r5 @ r4 = 31 to 20 bits of pc
- /* Extract the value to be written to table entry */
- ldr r6, table_entry
- /* r6 has the value to be written to table entry */
- add r6, r6, r4
- /* Getting the address of table entry to modify */
- lsr r4, #18
- /* r2 has the location which needs to be modified */
- add r2, r4
- ldr r4, [r2]
- str r6, [r2] /* modify the table entry */
-
- mov r7, r6
- mov r5, r2
- mov r6, r4
- /* r5 = original page table address */
- /* r6 = original page table data */
-
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
- mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
- mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
- mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
-
- /*
- * Restore control register. This enables the MMU.
- * The caches and prediction are not enabled here, they
- * will be enabled after restoring the MMU table entry.
- */
- ldmia r3!, {r4}
- stmia r3!, {r5} /* save original page table address */
- stmia r3!, {r6} /* save original page table data */
- stmia r3!, {r7} /* save modified page table data */
-
- ldr r2, cache_pred_disable_mask
- and r4, r2
- mcr p15, 0, r4, c1, c0, 0
- dsb
- isb
-
- ldr r0, =restoremmu_on
- bx r0
-
-/*
- * ===============
- * = Exit point from OFF mode =
- * ===============
- */
-restoremmu_on:
-
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
+ .global sh7372_resume_core_standby
+sh7372_resume_core_standby:
+ ldr pc, 1f
+1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
^ permalink raw reply
* [PATCH] sh: Fix implicit declaration of function numa_node_id
From: Nobuhiro Iwamatsu @ 2011-08-26 5:05 UTC (permalink / raw)
To: linux-sh
CC arch/sh/kernel/topology.o
arch/sh/kernel/topology.c: In function ‘topology_init’:
arch/sh/kernel/topology.c:77: error: implicit declaration of function ‘numa_node_id’
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
---
arch/sh/kernel/topology.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/sh/kernel/topology.c b/arch/sh/kernel/topology.c
index ab37955..3297150 100644
--- a/arch/sh/kernel/topology.c
+++ b/arch/sh/kernel/topology.c
@@ -7,6 +7,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/init.h>
@@ -14,6 +15,7 @@
#include <linux/node.h>
#include <linux/nodemask.h>
#include <linux/export.h>
+#include <linux/topology.h>
static DEFINE_PER_CPU(struct cpu, cpu_devices);
--
1.7.5.4
^ permalink raw reply related
* Re: Can not compile Ecovec board
From: Magnus Damm @ 2011-08-26 4:51 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87aaaxou97.wl%kuninori.morimoto.gx@renesas.com>
On Fri, Aug 26, 2011 at 1:30 PM, Nobuhiro Iwamatsu <iwamatsu@nigauri.org> wrote:
> This was already revised in linux-next tree.
That's great, but shouldn't build fixes be solved for the RC kernels
if possible?
People really need to learn how to separate build fixes from new
development, otherwise everything will turn to shit.
Thanks,
/ magnus
^ permalink raw reply
* [PATCH][RESEND] ARM: mach-shmobile: AG5EVM/Kota2 external Ethernet fix
From: Magnus Damm @ 2011-08-26 4:49 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Keep the ZB clock enabled on sh73a0 to allow the BSC
to access external peripherals hooked up to CS signals.
This is needed to unbreak Ethernet support on sh73a0 boards
such as AG5EVM and Kota2 together with the following patch:
794d78f drivers: sh: late disabling of clocks V2
Signed-off-by: Magnus Damm <damm@opensource.se>
---
Rafael, since this patch is Runtime PM clock related, can you
please merge this with your other 3.1-rc fixes?
Without this patch sh73a0-based boards cannot use Ethernet.
arch/arm/mach-shmobile/clock-sh73a0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- 0001/arch/arm/mach-shmobile/clock-sh73a0.c
+++ work/arch/arm/mach-shmobile/clock-sh73a0.c 2011-08-22 14:31:42.000000000 +0900
@@ -243,7 +243,7 @@ static struct clk div6_clks[DIV6_NR] = {
[DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
[DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
[DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
- [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
+ [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT),
[DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
[DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
[DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
^ permalink raw reply
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