Re: SMP questions

["Earle R. Nietzel" <nietzel@rhinobox.org>]

On Thu, 2003-06-19 at 18:55, Shreyas Kejariwal wrote:
> Thanks Robert.
> 
> Getting back to Q3, as you mentioned, it uses shared bus. So that makes it
> hardware specific.  However, I read that Posix threads can achieve the same
> w/o sharing the bus. Is that correct?
> 
> Can anyone point which dual/SMP processors share memory bus ?
> 

There are some systems that have TLC that are shared between a group fo
processors. This how the Unisys ES7000 system works. It has a 32MB TLC
shared between each group of 4 processors. This allows SMP to scale
better.

Unisys has it where you can assign a group (4 processors) to a
particular process which will make sure that a hit occurs in the TLC and
improves performance for that particular process.

Another tweak they allow is to assign I/O devices to a group so that
I/O's are occuring in the same processor group as well.

> 
> Shreyas
> 
> 
> 
> --
> 
> -----------------------------------------------
> Shreyas Kejariwal
> Perigee LLC
> Tel: 315-453 7842 x 42
> 
> 
> 
> "Robert M. Hyatt" <hyatt@cis.uab.edu> wrote in message
> news:Pine.LNX.4.44.0306191057030.5678-100000@crafty.cis.uab.edu...
> > On Wed, 18 Jun 2003, Shreyas Kejariwal wrote:
> >
> > > Hi everyone,
> > >
> > > I am new to this arena and I have few questions so please help me answer
> > > them.
> > >
> > > 1. Looks like most of the new systems employ SMPs. But do we still have
> > > ASMPs systems ?
> >
> >
> > If you mean "asymmetric multiprocessing" the answer is generally "no".
> > That has pretty much disappeared.  If you mean something like clusters
> > and so forth, then they are going strong but require different
> > programming approaches.
> >
> >
> > >
> > > 2. How can we control the tasks, threads to run on a particular
> processor ?
> >
> > Why would you want to?  This is something the operating system should
> > handle correctly.
> >
> >
> > > Is there a way we can specify ? Take the scenario where there are two
> > > multi-threaded applications. I want all the threads of the App1 to run
> on
> > > Processor, P1 and the threads of the App2 on Processor, P2. Not like
> some
> > > threads of App1 would run on P2 depending on the scheduler.
> > >
> >
> >
> > Most systems support some sort of "processor affinity" stuff, but it is
> > a bad idea in general.  Leave the O/S stuff to the O/S.  It _really_
> > does know better...
> >
> >
> >
> > > 3. How can processors access each other's memory / addr space?
> > >
> >
> > Both processors are connected to the memory sub-system with a common
> > bus.
> >
> >
> >
> > > 4. Digging into the scheduler code, I found that we can either set
> scheduler
> > > policy to be either Round Robin or FIFO. Are there other schedulers
> > > available which use different policy.
> > >
> >
> > What scheduler are you looking at?
> >
> >
> >
> > > 5. I read about Shared and Non-shared Cache. How does L2 gets shared.
> Its on
> > > the die. So does that mean that you have to buy a shared cache board ?
> > >
> >
> > L2 isn't shared on Intel platforms. Each processor has its own L2 cache
> > on chip.  Otherwise, it is shared just like memory is shared, with a
> > common bus connecting it to more than one processor.
> >
> >
> >
> >
> > > I apologize if some of the questions are stupid and outside the scope of
> > > this forum.
> > >
> > > Moreover, pointers to web-resources would be helpful.
> > >
> > > Thanks,
> > > Shreyas
> > >
> > >
> > >
> > >
> > >
> > > -
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> > >
> >
> > --
> > Robert Hyatt                    Computer and Information Sciences
> > hyatt@cis.uab.edu               University of Alabama at Birmingham
> > (205) 934-2213                  115A Campbell Hall, UAB Station
> > (205) 934-5473 FAX              Birmingham, AL 35294-1170
> >
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> 
> 
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-- 
Earle R. Nietzel <nietzel@rhinobox.org>