From mboxrd@z Thu Jan 1 00:00:00 1970 From: Erik Mouw Subject: Re: interrupt processing Date: Mon, 2 Jul 2007 17:55:41 +0200 Message-ID: <20070702155541.GG6356@gateway.home> References: Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="8S1fMsFYqgBC+BN/" Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-smp-owner@vger.kernel.org List-Id: To: Matthew Faulkner Cc: linux-smp@vger.kernel.org --8S1fMsFYqgBC+BN/ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jun 15, 2007 at 03:46:39PM +0100, Matthew Faulkner wrote: > Probably a very simple question, but can anyone tell me how the kernel > decides which CPU (or core) a hardware interrupt gets handled by? It programs the APIC. IRQs can be handled by a random CPU, by a set of CPUs, or by a single CPU. You can have some influence on the APIC IRQ routing by writing /proc/irq//smp_affinity . Erik --=20 They're all fools. Don't worry. Darwin may be slow, but he'll eventually get them. -- Matthew Lammers in alt.sysadmin.recovery --8S1fMsFYqgBC+BN/ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) iD8DBQFGiR/9/PlVHJtIto0RAh1iAJ43Ypuls603z/uTZ9YtYyCCSJ7hXwCeM2hu Jxf4RsAwwQftVtJHMefEgmU= =FoB/ -----END PGP SIGNATURE----- --8S1fMsFYqgBC+BN/--