From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-snps-arc@lists.infradead.org
Subject: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS
Date: Tue, 19 Dec 2017 11:11:42 -0800 [thread overview]
Message-ID: <20171219191142.GC7997@codeaurora.org> (raw)
In-Reply-To: <20171209135918.16720-1-Eugeniy.Paltsev@synopsys.com>
On 12/09, Eugeniy Paltsev wrote:
> Set initial core pll output frequency on HSDK and AXS103 via
> "assigned-clock-rates" property in device tree.
> It will be applied at the core pll driver probing.
>
> Eugeniy Paltsev (4):
> ARC: [plat-hsdk]: Set initial core pll output frequency
> ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
> ARC: [plat-axs103]: Set initial core pll output frequency
> ARC: [plat-axs103] refactor the quad core DT quirk code
>
Patches look good to me.
Acked-by: Stephen Boyd <sboyd at codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-12-19 19:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-09 13:59 [PATCH 0/4] ARC: Set initial core pll output frequency via DTS Eugeniy Paltsev
2017-12-09 13:59 ` [PATCH 1/4] ARC: [plat-hsdk]: Set initial core pll output frequency Eugeniy Paltsev
2017-12-09 13:59 ` [PATCH 2/4] ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code Eugeniy Paltsev
2017-12-09 13:59 ` [PATCH 3/4] ARC: [plat-axs103]: Set initial core pll output frequency Eugeniy Paltsev
2017-12-09 13:59 ` [PATCH 4/4] ARC: [plat-axs103] refactor the quad core DT quirk code Eugeniy Paltsev
2017-12-15 21:46 ` [PATCH 0/4] ARC: Set initial core pll output frequency via DTS Vineet Gupta
2017-12-19 19:11 ` Stephen Boyd [this message]
-- strict thread matches above, loose matches on Subject: below --
2017-11-27 18:56 Eugeniy Paltsev
2017-12-06 22:02 ` Vineet Gupta
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