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Wed, 30 Sep 2020 13:46:48 -0700 (PDT) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 11/14] arc: Add gdbstub and XML for debugging support Date: Wed, 30 Sep 2020 21:46:01 +0100 Message-Id: <20200930204604.20663-12-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200930204604.20663-1-cupertinomiranda@gmail.com> References: <20200930204604.20663-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_164650_340033_1EA250C5 X-CRM114-Status: GOOD ( 12.00 ) X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+linux-snps-arc=archiver.kernel.org@lists.infradead.org From: Shahab Vahedi Register layout for the target and the mechanisms to read and set them. Signed-off-by: Shahab Vahedi --- gdb-xml/arc-aux-minimal.xml | 32 +++ gdb-xml/arc-aux-other.xml | 235 ++++++++++++++++++++ gdb-xml/arc-core-v2.xml | 45 ++++ target/arc/gdbstub.c | 421 ++++++++++++++++++++++++++++++++++++ 4 files changed, 733 insertions(+) create mode 100644 gdb-xml/arc-aux-minimal.xml create mode 100644 gdb-xml/arc-aux-other.xml create mode 100644 gdb-xml/arc-core-v2.xml create mode 100644 target/arc/gdbstub.c diff --git a/gdb-xml/arc-aux-minimal.xml b/gdb-xml/arc-aux-minimal.xml new file mode 100644 index 0000000000..7809c97a8d --- /dev/null +++ b/gdb-xml/arc-aux-minimal.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/arc-aux-other.xml b/gdb-xml/arc-aux-other.xml new file mode 100644 index 0000000000..86b114af98 --- /dev/null +++ b/gdb-xml/arc-aux-other.xml @@ -0,0 +1,235 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/arc-core-v2.xml b/gdb-xml/arc-core-v2.xml new file mode 100644 index 0000000000..550dae3411 --- /dev/null +++ b/gdb-xml/arc-core-v2.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c new file mode 100644 index 0000000000..574e8fdf4b --- /dev/null +++ b/target/arc/gdbstub.c @@ -0,0 +1,421 @@ + +/* + * QEMU ARC CPU + * + * Copyright (c) 2016 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "arc-common.h" +#include "target/arc/regs.h" +#include "internals.h" +#include "irq.h" + +/* gets the register address for a particular processor */ +#define REG_ADDR(reg, processor_type) \ + arc_aux_reg_address_for((reg), (processor_type)) + +int arc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + uint32_t regval = 0; + + switch (n) { + case 0 ... 31: + regval = env->r[n]; + break; + case GDB_REG_58: + regval = env->r[58]; + break; + case GDB_REG_59: + regval = env->r[59]; + break; + case GDB_REG_60: + regval = env->r[60]; + break; + case GDB_REG_63: + regval = env->r[63]; + break; + default: + assert(!"Unsupported register is being read."); + } + + return gdb_get_reg32(mem_buf, regval); +} + +int arc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARCCPU *cpu = ARC_CPU(cs); + CPUARCState *env = &cpu->env; + uint32_t regval = ldl_p(mem_buf); + + switch (n) { + case 0 ... 31: + env->r[n] = regval; + break; + case GDB_REG_58: + env->r[58] = regval; + break; + case GDB_REG_59: + env->r[59] = regval; + break; + case GDB_REG_60: + env->r[60] = regval; + break; + case GDB_REG_63: + env->r[63] = regval; + break; + default: + assert(!"Unsupported register is being written."); + } + + return 4; +} + + +static int +arc_aux_minimal_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = 0; + + switch (regnum) { + case GDB_AUX_MIN_REG_PC: + regval = env->pc & 0xfffffffe; + break; + case GDB_AUX_MIN_REG_LPS: + regval = helper_lr(env, REG_ADDR(AUX_ID_lp_start, processor)); + break; + case GDB_AUX_MIN_REG_LPE: + regval = helper_lr(env, REG_ADDR(AUX_ID_lp_end, processor)); + break; + case GDB_AUX_MIN_REG_STATUS: + regval = pack_status32(&env->stat); + break; + default: + assert(!"Unsupported minimal auxiliary register is being read."); + } + return gdb_get_reg32(mem_buf, regval); +} + + +static int +arc_aux_minimal_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = ldl_p(mem_buf); + switch (regnum) { + case GDB_AUX_MIN_REG_PC: + env->pc = regval & 0xfffffffe; + break; + case GDB_AUX_MIN_REG_LPS: + helper_sr(env, regval, REG_ADDR(AUX_ID_lp_start, processor)); + break; + case GDB_AUX_MIN_REG_LPE: + helper_sr(env, regval, REG_ADDR(AUX_ID_lp_end, processor)); + break; + case GDB_AUX_MIN_REG_STATUS: + unpack_status32(&env->stat, regval); + break; + default: + assert(!"Unsupported minimal auxiliary register is being written."); + } + return 4; +} + + +static int +arc_aux_other_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = 0; + switch (regnum) { + case GDB_AUX_OTHER_REG_TIMER_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_timer_build, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_build, processor)); + break; + case GDB_AUX_OTHER_REG_MPY_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpy_build, processor)); + break; + case GDB_AUX_OTHER_REG_VECBASE_BUILD: + regval = env->vecbase_build; + break; + case GDB_AUX_OTHER_REG_ISA_CONFIG: + regval = env->isa_config; + break; + case GDB_AUX_OTHER_REG_TIMER_CNT0: + regval = helper_lr(env, REG_ADDR(AUX_ID_count0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL0: + regval = helper_lr(env, REG_ADDR(AUX_ID_control0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM0: + regval = helper_lr(env, REG_ADDR(AUX_ID_limit0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CNT1: + regval = helper_lr(env, REG_ADDR(AUX_ID_count1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL1: + regval = helper_lr(env, REG_ADDR(AUX_ID_control1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM1: + regval = helper_lr(env, REG_ADDR(AUX_ID_limit1, processor)); + break; + case GDB_AUX_OTHER_REG_PID: + regval = helper_lr(env, REG_ADDR(AUX_ID_pid, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD0: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbpd0, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD1: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbpd1, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_INDEX: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbindex, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_CMD: + regval = helper_lr(env, REG_ADDR(AUX_ID_tlbcommand, processor)); + break; + /* MPU */ + case GDB_AUX_OTHER_REG_MPU_BUILD: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpu_build, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_EN: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpuen, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_ECR: + regval = helper_lr(env, REG_ADDR(AUX_ID_mpuic, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_BASE0; + regval = helper_lr(env, REG_ADDR(AUX_ID_mpurdb0 + index, processor)); + break; + } + case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_PERM0; + regval = helper_lr(env, REG_ADDR(AUX_ID_mpurdp0 + index, processor)); + break; + } + /* exceptions */ + case GDB_AUX_OTHER_REG_ERSTATUS: + regval = helper_lr(env, REG_ADDR(AUX_ID_erstatus, processor)); + break; + case GDB_AUX_OTHER_REG_ERBTA: + regval = helper_lr(env, REG_ADDR(AUX_ID_erbta, processor)); + break; + case GDB_AUX_OTHER_REG_ECR: + regval = helper_lr(env, REG_ADDR(AUX_ID_ecr, processor)); + break; + case GDB_AUX_OTHER_REG_ERET: + regval = helper_lr(env, REG_ADDR(AUX_ID_eret, processor)); + break; + case GDB_AUX_OTHER_REG_EFA: + regval = helper_lr(env, REG_ADDR(AUX_ID_efa, processor)); + break; + /* interrupt */ + case GDB_AUX_OTHER_REG_ICAUSE: + regval = helper_lr(env, REG_ADDR(AUX_ID_icause, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_CTRL: + regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_ctrl, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ACT: + regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_act, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: + regval = env->irq_priority_pending; + break; + case GDB_AUX_OTHER_REG_IRQ_HINT: + regval = helper_lr(env, REG_ADDR(AUX_ID_aux_irq_hint, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_SELECT: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_select, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ENABLE: + regval = env->irq_bank[env->irq_select & 0xff].enable; + break; + case GDB_AUX_OTHER_REG_IRQ_TRIGGER: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_trigger, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_STATUS: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_status, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PULSE: + regval = 0; /* write only for clearing the pulse triggered interrupt */ + break; + case GDB_AUX_OTHER_REG_IRQ_PENDING: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_pending, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO: + regval = helper_lr(env, REG_ADDR(AUX_ID_irq_priority, processor)); + break; + case GDB_AUX_OTHER_REG_BTA: + regval = helper_lr(env, REG_ADDR(AUX_ID_bta, processor)); + break; + default: + assert(!"Unsupported other auxiliary register is being read."); + } + return gdb_get_reg32(mem_buf, regval); +} + + +static int +arc_aux_other_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor = ARC_OPCODE_ARCv2HS; + uint32_t regval = ldl_p(mem_buf); + switch (regnum) { + case GDB_AUX_OTHER_REG_TIMER_BUILD: + case GDB_AUX_OTHER_REG_IRQ_BUILD: + case GDB_AUX_OTHER_REG_MPY_BUILD: + case GDB_AUX_OTHER_REG_VECBASE_BUILD: + case GDB_AUX_OTHER_REG_ISA_CONFIG: + case GDB_AUX_OTHER_REG_MPU_BUILD: + case GDB_AUX_OTHER_REG_MPU_ECR: + case GDB_AUX_OTHER_REG_ICAUSE: + case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: + case GDB_AUX_OTHER_REG_IRQ_STATUS: + case GDB_AUX_OTHER_REG_IRQ_PENDING: + /* builds/configs/exceptions/irqs cannot be changed */ + break; + case GDB_AUX_OTHER_REG_TIMER_CNT0: + helper_sr(env, regval, REG_ADDR(AUX_ID_count0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL0: + helper_sr(env, regval, REG_ADDR(AUX_ID_control0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM0: + helper_sr(env, regval, REG_ADDR(AUX_ID_limit0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CNT1: + helper_sr(env, regval, REG_ADDR(AUX_ID_count1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL1: + helper_sr(env, regval, REG_ADDR(AUX_ID_control1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM1: + helper_sr(env, regval, REG_ADDR(AUX_ID_limit1, processor)); + break; + case GDB_AUX_OTHER_REG_PID: + helper_sr(env, regval, REG_ADDR(AUX_ID_pid, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD0: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd0, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD1: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd1, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_INDEX: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbindex, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_CMD: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbcommand, processor)); + break; + /* MPU */ + case GDB_AUX_OTHER_REG_MPU_EN: + helper_sr(env, regval, REG_ADDR(AUX_ID_mpuen, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_BASE0; + helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdb0 + index, processor)); + break; + } + case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { + const uint8_t index = regnum - GDB_AUX_OTHER_REG_MPU_PERM0; + helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdp0 + index, processor)); + break; + } + /* exceptions */ + case GDB_AUX_OTHER_REG_ERSTATUS: + helper_sr(env, regval, REG_ADDR(AUX_ID_erstatus, processor)); + break; + case GDB_AUX_OTHER_REG_ERBTA: + helper_sr(env, regval, REG_ADDR(AUX_ID_erbta, processor)); + break; + case GDB_AUX_OTHER_REG_ECR: + helper_sr(env, regval, REG_ADDR(AUX_ID_ecr, processor)); + break; + case GDB_AUX_OTHER_REG_ERET: + helper_sr(env, regval, REG_ADDR(AUX_ID_eret, processor)); + break; + case GDB_AUX_OTHER_REG_EFA: + helper_sr(env, regval, REG_ADDR(AUX_ID_efa, processor)); + break; + /* interrupt */ + case GDB_AUX_OTHER_REG_IRQ_CTRL: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_ctrl, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ACT: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_act, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_HINT: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_hint, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_SELECT: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_select, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ENABLE: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_enable, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_TRIGGER: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_trigger, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PULSE: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_pulse_cancel, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_priority, processor)); + break; + case GDB_AUX_OTHER_REG_BTA: + helper_sr(env, regval, REG_ADDR(AUX_ID_bta, processor)); + break; + default: + assert(!"Unsupported other auxiliary register is being written."); + } + return 4; +} + + +void arc_cpu_register_gdb_regs_for_features(ARCCPU *cpu) +{ + CPUState *cs = CPU(cpu); + + gdb_register_coprocessor(cs, + arc_aux_minimal_gdb_get_reg, /* getter */ + arc_aux_minimal_gdb_set_reg, /* setter */ + GDB_AUX_MIN_REG_LAST, /* number of registers */ + "arc-aux-minimal.xml", /* feature file */ + 0); /* position in g packet */ + + gdb_register_coprocessor(cs, + arc_aux_other_gdb_get_reg, + arc_aux_other_gdb_set_reg, + GDB_AUX_OTHER_REG_LAST, + "arc-aux-other.xml", + 0); +} + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/ +/* vim: set ts=4 sw=4 et: */ -- 2.20.1 _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc