From: Vineet Gupta <vgupta@kernel.org>
To: Matthew Wilcox <willy@infradead.org>, linux-snps-arc@lists.infradead.org
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Subject: Re: How many colours does the ARC cache have?
Date: Wed, 15 Feb 2023 20:59:18 -0800 [thread overview]
Message-ID: <4ebe9300-c694-5a49-7180-ca6c14ec11b6@kernel.org> (raw)
In-Reply-To: <Y+Z5nuY/PaINgW0v@casper.infradead.org>
On 2/10/23 09:06, Matthew Wilcox wrote:
> I see a discrepancy here ...
>
> arch/arc/include/asm/shmparam.h:
> /* Handle upto 2 cache bins */
> #define SHMLBA (2 * PAGE_SIZE)
>
> arch/arc/include/asm/cacheflush.h:
> #define CACHE_COLORS_NUM 4
The initial aliasing dcache support assumed 2 colors but was later
bumped to 4, w/o making the adjustment in shmparam.h
> (there are some other problems with the arc cache flushing code;
The VIPT aliasing config (which is pretty much dead and unused) or
regular parts ?
> I'm working on patches to address them, but those are things I understand a
> little better. I know nothing about the ARC architecture itself)
Legacy ARC700 cpus had VIPT D$. The cache size was configurable by Soc
builder and the specific geometry could yield an aliasing configuration
(e.g. standard page size 8K, 4 way set associative D$: so D$ > 32K were
aliasing and needed CONFIG_ARC_CACHE_VIPT_ALIASING). Although there was
ever only 1 customer who taped out an aliasing cache config.
The newer ARC HS cores have PIPT D$ and thus don't need the aliasing
support.
FWIW we could rip out all the VIPT aliasing code as I don't think it is
needed anymore. @Alexey can you confirm ?
-Vineet
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next prev parent reply other threads:[~2023-02-16 4:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 17:06 How many colours does the ARC cache have? Matthew Wilcox
2023-02-16 4:59 ` Vineet Gupta [this message]
2023-02-18 19:03 ` Matthew Wilcox
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