[RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver

Stephen Boyd
2016-04-20T01:54:51Z

On 04/19, Jose Abreu wrote:
>
> @Stephen: can you give some input so that I can submit a v6?
>

I don't prefer putting the second register in the same DT node,
but that's really up to the DT reviewers to approve such a
design. The current binding has been acked by Rob right?

Assuming the new binding is acked/reviewed then that solution is
fine.

Otherwise, I still prefer two DTS files for the two different FPGA
versions. At the least, please use ioremap for any pointers that
you readl/writel here.

Beyond that, we should have a fixed rate source clk somewhere in
the software view of the clk tree, because that reflects reality.
Hardcoding the parent rate in the structure works, but doesn't
properly express the clk tree.

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