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Tue, 22 Apr 2025 00:28:38 -0700 From: "Sheetal ." To: , CC: , , , , , , Sheetal Subject: [PATCH 04/10] ASoC: tegra: ASRC: Update ARAM address Date: Tue, 22 Apr 2025 07:27:59 +0000 Message-ID: <20250422072805.501152-5-sheetal@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250422072805.501152-1-sheetal@nvidia.com> References: <20250422072805.501152-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE9:EE_|MW4PR12MB7432:EE_ X-MS-Office365-Filtering-Correlation-Id: 027d6553-deda-4f7e-f204-08dd816f5603 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uk6qPzCpRVoSDn560mL/qMXP2ynzxigN9OGfdSknZa0BJjs5D5xFV1S/49bz?= =?us-ascii?Q?eAnJaNGfvpdR11oBHKMSePkD+XgdywuxKgvijOIO8WgH0YmrR3KEMswDv7wR?= =?us-ascii?Q?GPDUkgwy9hy+pRdCd9DSpdTkngtaY74tv4GSE214MaQKi/efWD2rKVmTfMFG?= =?us-ascii?Q?Bi5HhXmv359rLmZ1OXdu3yrZG+hNWDeH6P99ssI3n4WhZOIg6KVIbnS7z3Xw?= =?us-ascii?Q?sE/0PRKd9YCBhX0Bwxp4kMKQunuImOeBuFklejjex2NXlG0r74OHE2mlTUmN?= =?us-ascii?Q?D9rW6SrXe58I+4+eerKg6d3HAjleJtkcGaUlayuBWleLhvw1ygGhd19P66nU?= =?us-ascii?Q?Zxp0wqyMu/lfRcGL16Ga7tl1EmTxTXhMscH0fgbWGGhLYYjZ/gxUNoxxpctN?= =?us-ascii?Q?m+5hdTKl+wT30Fl+6p+tqOSUYkFry0qwh7VM2VdRYRG/x0T/gfcn+chRbe2U?= =?us-ascii?Q?gho0+WM1GMaD7k1Iy5ccN9BqvKn2lHAAOBh9xqfb1JMB6GVj6GCKJs8IaZt5?= =?us-ascii?Q?pNSWiDFBWkNInnCWE2qUgEtuEjTTXO6r/f0bdf7u+EWMkVX8U87KUsl7ENkB?= =?us-ascii?Q?uAUhSoBmVq93a/lQP1t0Dc16zsGtF3wkg0FhvKaf+BFu32YOKEfz/YDXxdgK?= =?us-ascii?Q?R96xUMySIr70xbQ203p2k6HhMJOOhjA9mYYA5dXc8GY0zx5zPyg7vlMlh/Mu?= =?us-ascii?Q?+QJxBKiIOIJgm8MgtAAFVwi4GM77xkDqs3t0SIr5QLh0bB3vzEyw0bzZypML?= =?us-ascii?Q?eZfv9/MbA6bfxvDUZC96cJyr7MJoGvH5SNqe1Dc9hAhIOB464cGk5O8aRys3?= =?us-ascii?Q?JH7DtWq47TbyJ2+kbIg0cr7vCeSJienXax2t138/be/3ps9Gn8iTizwODQvO?= =?us-ascii?Q?0aV/2xFPLxGByPVAh1Wk/ON4t36PA7HzMikoTPsZcSehOY9vTOvCBxtWvgLa?= =?us-ascii?Q?nFDGCd4EvTsCIxud88YQuMUeCyvNladENc2eC0goZKA32P5dvdnkfs9Wu1iu?= =?us-ascii?Q?MTAYUJLONaqT1Bl0ZYwAAoH83fQtgRouah+fywOLqJSvB+6TbLljLg9jN1A8?= =?us-ascii?Q?DUBZJQsNLTg9m/Y/PtarZkZe1YCavO0yE74cI1gEFlBDQUI9Z7EMEppM3GkF?= =?us-ascii?Q?eLuSFDXkVU1Yyex1F+adSyjevZucCVQAEbDB7/qSoZkxybSKbyqx14iHz3kn?= =?us-ascii?Q?s5EIfSmZdcewprh6wsQcfFOiAveylok/FxAxh1GHsVb1stRXB9E+JdPfhXIG?= =?us-ascii?Q?5C0F7tEiNKtZNA79ETNXS6O1TAN9Cs5RyNdFzZFh3lpgnYdOF+uUEFd1dYca?= =?us-ascii?Q?FE4fjgOq8NiQ01Wb7k8dne5NETD4qrLX7cAoRgRtmG22ii/E6AHDx4ln6C3+?= =?us-ascii?Q?QUKGdUX22rcPK2+f75E7VOEU+UDc/MmBaCIHO/NZ/4PDW20OvBhTc4sMZ+QB?= =?us-ascii?Q?xXehLLJFJEiPvMc8UaOJUPYjNwiitDvjWBlYJJLSTO8MD+LQFoDp9BUgESG0?= =?us-ascii?Q?J2JvU5pLgY1HXyBOc/RXeIKsohS9xX9imGG/?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2025 07:28:53.9836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 027d6553-deda-4f7e-f204-08dd816f5603 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7432 From: Sheetal The ARAM address for Tegra264 has been updated. To maintain backward compatibility given its chip-specific nature, it's now included in the soc_data. Signed-off-by: Sheetal --- sound/soc/tegra/tegra186_asrc.c | 18 ++++++++++++++---- sound/soc/tegra/tegra186_asrc.h | 12 ++++++++---- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/sound/soc/tegra/tegra186_asrc.c b/sound/soc/tegra/tegra186_asrc.c index 5c67e1f01d9b..851509ae07f5 100644 --- a/sound/soc/tegra/tegra186_asrc.c +++ b/sound/soc/tegra/tegra186_asrc.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved. // // tegra186_asrc.c - Tegra186 ASRC driver -// -// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. #include #include @@ -99,7 +98,7 @@ static int tegra186_asrc_runtime_resume(struct device *dev) * sync is done after this to restore other settings. */ regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, - TEGRA186_ASRC_ARAM_START_ADDR); + asrc->soc_data->aram_start_addr); regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, TEGRA186_ASRC_GLOBAL_EN); @@ -954,8 +953,17 @@ static const struct regmap_config tegra186_asrc_regmap_config = { .cache_type = REGCACHE_FLAT, }; +static const struct tegra_asrc_soc_data soc_data_tegra186 = { + .aram_start_addr = TEGRA186_ASRC_ARAM_START_ADDR, +}; + +static const struct tegra_asrc_soc_data soc_data_tegra264 = { + .aram_start_addr = TEGRA264_ASRC_ARAM_START_ADDR, +}; + static const struct of_device_id tegra186_asrc_of_match[] = { - { .compatible = "nvidia,tegra186-asrc" }, + { .compatible = "nvidia,tegra186-asrc", .data = &soc_data_tegra186 }, + { .compatible = "nvidia,tegra264-asrc", .data = &soc_data_tegra264 }, {}, }; MODULE_DEVICE_TABLE(of, tegra186_asrc_of_match); @@ -985,6 +993,8 @@ static int tegra186_asrc_platform_probe(struct platform_device *pdev) return PTR_ERR(asrc->regmap); } + asrc->soc_data = of_device_get_match_data(&pdev->dev); + regcache_cache_only(asrc->regmap, true); regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG, diff --git a/sound/soc/tegra/tegra186_asrc.h b/sound/soc/tegra/tegra186_asrc.h index 094fcc723c02..0c98e26d5e72 100644 --- a/sound/soc/tegra/tegra186_asrc.h +++ b/sound/soc/tegra/tegra186_asrc.h @@ -1,9 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* +/* SPDX-License-Identifier: GPL-2.0-only + * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION. All rights reserved. * tegra186_asrc.h - Definitions for Tegra186 ASRC driver * - * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. - * */ #ifndef __TEGRA186_ASRC_H__ @@ -94,6 +92,7 @@ #define TEGRA186_ASRC_RATIO_SOURCE_SW 0x1 #define TEGRA186_ASRC_ARAM_START_ADDR 0x3f800000 +#define TEGRA264_ASRC_ARAM_START_ADDR 0x8a080000 struct tegra186_asrc_lane { unsigned int int_part; @@ -104,7 +103,12 @@ struct tegra186_asrc_lane { unsigned int output_thresh; }; +struct tegra_asrc_soc_data { + unsigned int aram_start_addr; +}; + struct tegra186_asrc { + const struct tegra_asrc_soc_data *soc_data; struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX]; struct regmap *regmap; }; -- 2.17.1