From: Julien Massot <julien.massot@collabora.com>
To: kernel@collabora.com, Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Ikjoon Jang <ikjn@chromium.org>,
Enric Balletbo i Serra <eballetbo@kernel.org>,
Chen-Yu Tsai <wenst@chromium.org>,
Weiyi Lu <weiyi.lu@mediatek.com>,
Eugen Hristev <eugen.hristev@linaro.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Julien Massot <jmassot@collabora.com>,
Sean Wang <sean.wang@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-sound@vger.kernel.org,
linux-gpio@vger.kernel.org,
Julien Massot <julien.massot@collabora.com>
Subject: [PATCH 4/9] ASoc: dt-binding: Convert mt8183-afe-pcm binding to YAML
Date: Fri, 01 Aug 2025 13:18:06 +0200 [thread overview]
Message-ID: <20250801-mtk-dtb-warnings-v1-4-6ba4e432427b@collabora.com> (raw)
In-Reply-To: <20250801-mtk-dtb-warnings-v1-0-6ba4e432427b@collabora.com>
Convert the MediaTek MT8183 AFE PCM Device Tree binding from the old
.txt format to YAML schema format to improve validation.
While converting, also document all clock inputs used by the AFE block.
Signed-off-by: Julien Massot <julien.massot@collabora.com>
---
.../devicetree/bindings/sound/mt8183-afe-pcm.txt | 42 ----
.../devicetree/bindings/sound/mt8183-afe-pcm.yaml | 225 +++++++++++++++++++++
2 files changed, 225 insertions(+), 42 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
deleted file mode 100644
index 1f1cba4152ceecbe61d0db0b972f98df7d5d91ac..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Mediatek AFE PCM controller for mt8183
-
-Required properties:
-- compatible = "mediatek,mt68183-audio";
-- reg: register location and size
-- interrupts: should contain AFE interrupt
-- resets: Must contain an entry for each entry in reset-names
- See ../reset/reset.txt for details.
-- reset-names: should have these reset names:
- "audiosys";
-- power-domains: should define the power domain
-- clocks: Must contain an entry for each entry in clock-names
-- clock-names: should have these clock names:
- "infra_sys_audio_clk",
- "mtkaif_26m_clk",
- "top_mux_audio",
- "top_mux_aud_intbus",
- "top_sys_pll3_d4",
- "top_clk26m_clk";
-
-Example:
-
- afe: mt8183-afe-pcm@11220000 {
- compatible = "mediatek,mt8183-audio";
- reg = <0 0x11220000 0 0x1000>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
- resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
- reset-names = "audiosys";
- power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>;
- clocks = <&infrasys CLK_INFRA_AUDIO>,
- <&infrasys CLK_INFRA_AUDIO_26M_BCLK>,
- <&topckgen CLK_TOP_MUX_AUDIO>,
- <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
- <&topckgen CLK_TOP_SYSPLL_D2_D4>,
- <&clk26m>;
- clock-names = "infra_sys_audio_clk",
- "mtkaif_26m_clk",
- "top_mux_audio",
- "top_mux_aud_intbus",
- "top_sys_pll_d2_d4",
- "top_clk26m_clk";
- };
diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..0f6ab43fa99e55a7572d962f61537c8ab31dcdb0
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.yaml
@@ -0,0 +1,225 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mt8183-afe-pcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek AFE PCM controller for mt8183
+
+maintainers:
+ - Julien Massot <jmassot@collabora.com>
+
+properties:
+ compatible:
+ const: mediatek,mt8183-audio
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: audiosys
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AFE clock
+ - description: ADDA DAC clock
+ - description: ADDA DAC pre-distortion clock
+ - description: ADDA ADC clock
+ - description: ADDA6 ADC clock
+ - description: Audio low-jitter 22.5792m clock
+ - description: Audio low-jitter 24.576m clock
+ - description: Audio PLL1 tuner clock
+ - description: Audio PLL2 tuner clock
+ - description: I2S1 bit clock
+ - description: I2S2 bit clock
+ - description: I2S3 bit clock
+ - description: I2S4 bit clock
+ - description: Audio Time-Division Multiplexing interface clock
+ - description: Powerdown Audio test model clock
+ - description: Audio infra sys clock
+ - description: Audio infra 26M clock
+ - description: Mux for audio clock
+ - description: Mux for audio internal bus clock
+ - description: Mux main divider by 4
+ - description: Primary audio mux
+ - description: Primary audio PLL
+ - description: Secondary audio mux
+ - description: Secondary audio PLL
+ - description: Primary audio en-generator clock
+ - description: Primary PLL divider by 4 for IEC
+ - description: Secondary audio en-generator clock
+ - description: Secondary PLL divider by 8 for IEC
+ - description: Mux selector for I2S port 0
+ - description: Mux selector for I2S port 1
+ - description: Mux selector for I2S port 2
+ - description: Mux selector for I2S port 3
+ - description: Mux selector for I2S port 4
+ - description: Mux selector for I2S port 5
+ - description: APLL1 and APLL2 divider for I2S port 0
+ - description: APLL1 and APLL2 divider for I2S port 1
+ - description: APLL1 and APLL2 divider for I2S port 2
+ - description: APLL1 and APLL2 divider for I2S port 3
+ - description: APLL1 and APLL2 divider for I2S port 4
+ - description: APLL1 and APLL2 divider for IEC
+ - description: 26MHz clock for audio subsystem
+
+ clock-names:
+ items:
+ - const: aud_afe_clk
+ - const: aud_dac_clk
+ - const: aud_dac_predis_clk
+ - const: aud_adc_clk
+ - const: aud_adc_adda6_clk
+ - const: aud_apll22m_clk
+ - const: aud_apll24m_clk
+ - const: aud_apll1_tuner_clk
+ - const: aud_apll2_tuner_clk
+ - const: aud_i2s1_bclk_sw
+ - const: aud_i2s2_bclk_sw
+ - const: aud_i2s3_bclk_sw
+ - const: aud_i2s4_bclk_sw
+ - const: aud_tdm_clk
+ - const: aud_tml_clk
+ - const: aud_infra_clk
+ - const: mtkaif_26m_clk
+ - const: top_mux_audio
+ - const: top_mux_aud_intbus
+ - const: top_syspll_d2_d4
+ - const: top_mux_aud_1
+ - const: top_apll1_ck
+ - const: top_mux_aud_2
+ - const: top_apll2_ck
+ - const: top_mux_aud_eng1
+ - const: top_apll1_d8
+ - const: top_mux_aud_eng2
+ - const: top_apll2_d8
+ - const: top_i2s0_m_sel
+ - const: top_i2s1_m_sel
+ - const: top_i2s2_m_sel
+ - const: top_i2s3_m_sel
+ - const: top_i2s4_m_sel
+ - const: top_i2s5_m_sel
+ - const: top_apll12_div0
+ - const: top_apll12_div1
+ - const: top_apll12_div2
+ - const: top_apll12_div3
+ - const: top_apll12_div4
+ - const: top_apll12_divb
+ - const: top_clk26m_clk
+
+required:
+ - compatible
+ - interrupts
+ - resets
+ - reset-names
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/reset/mt8183-resets.h>
+
+ afe: mt8183-afe-pcm {
+ compatible = "mediatek,mt8183-audio";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ power-domains = <&spm MT8183_POWER_DOMAIN_AUDIO>;
+ clocks = <&audiosys CLK_AUDIO_AFE>,
+ <&audiosys CLK_AUDIO_DAC>,
+ <&audiosys CLK_AUDIO_DAC_PREDIS>,
+ <&audiosys CLK_AUDIO_ADC>,
+ <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
+ <&audiosys CLK_AUDIO_22M>,
+ <&audiosys CLK_AUDIO_24M>,
+ <&audiosys CLK_AUDIO_APLL_TUNER>,
+ <&audiosys CLK_AUDIO_APLL2_TUNER>,
+ <&audiosys CLK_AUDIO_I2S1>,
+ <&audiosys CLK_AUDIO_I2S2>,
+ <&audiosys CLK_AUDIO_I2S3>,
+ <&audiosys CLK_AUDIO_I2S4>,
+ <&audiosys CLK_AUDIO_TDM>,
+ <&audiosys CLK_AUDIO_TML>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_AUDIO>,
+ <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&topckgen CLK_TOP_SYSPLL_D2_D4>,
+ <&topckgen CLK_TOP_MUX_AUD_1>,
+ <&topckgen CLK_TOP_APLL1_CK>,
+ <&topckgen CLK_TOP_MUX_AUD_2>,
+ <&topckgen CLK_TOP_APLL2_CK>,
+ <&topckgen CLK_TOP_MUX_AUD_ENG1>,
+ <&topckgen CLK_TOP_APLL1_D8>,
+ <&topckgen CLK_TOP_MUX_AUD_ENG2>,
+ <&topckgen CLK_TOP_APLL2_D8>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S0>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S1>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S2>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S3>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S4>,
+ <&topckgen CLK_TOP_MUX_APLL_I2S5>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adc_adda6_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_i2s1_bclk_sw",
+ "aud_i2s2_bclk_sw",
+ "aud_i2s3_bclk_sw",
+ "aud_i2s4_bclk_sw",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_aud_intbus",
+ "top_syspll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_clk26m_clk";
+ };
+
+...
--
2.50.1
next prev parent reply other threads:[~2025-08-01 11:18 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-01 11:18 [PATCH 0/9] MediaTek devicetree/bindings warnings sanitization second round Julien Massot
2025-08-01 11:18 ` [PATCH 1/9] dt-bindings: clock: mediatek: Add power-domains property Julien Massot
2025-08-01 17:19 ` Rob Herring (Arm)
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-20 13:27 ` Julien Massot
2025-08-01 11:18 ` [PATCH 2/9] dt-bindings: arm: mediatek: Support mt8183-audiosys binding variant Julien Massot
2025-08-01 17:21 ` Rob Herring
2025-08-20 13:28 ` Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-20 13:30 ` Julien Massot
2025-08-01 11:18 ` [PATCH 3/9] arm64: dts: mt8183: Rename nodes to match audiosys binding schema Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-01 11:18 ` Julien Massot [this message]
2025-08-01 17:26 ` [PATCH 4/9] ASoc: dt-binding: Convert mt8183-afe-pcm binding to YAML Rob Herring
2025-08-20 13:32 ` Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-01 11:18 ` [PATCH 5/9] dt-bindings: sound: Convert MT8183 DA7219 sound card bindings " Julien Massot
2025-08-01 17:28 ` Rob Herring
2025-08-20 13:33 ` Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-01 11:18 ` [PATCH 6/9] ASoC: dt-binding: Convert MediaTek mt8183-mt6358 " Julien Massot
2025-08-01 17:29 ` Rob Herring
2025-08-20 13:34 ` Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-01 11:18 ` [PATCH 7/9] dt-bindings: pinctrl: mediatek: mt8183: Allow gpio-line-names Julien Massot
2025-08-01 17:30 ` Rob Herring (Arm)
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-18 15:16 ` Linus Walleij
2025-08-01 11:18 ` [PATCH 8/9] arm64: dts: mediatek: mt8183-kukui: Fix pull-down/up-adv values Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-06 6:38 ` Chen-Yu Tsai
2025-08-18 15:22 ` Linus Walleij
2025-08-19 5:27 ` Chen-Yu Tsai
2025-08-19 5:29 ` Chen-Yu Tsai
2025-08-19 9:12 ` Julien Massot
2025-08-01 11:18 ` [PATCH 9/9] arm64: dts: mediatek: mt8183-pumkin: " Julien Massot
2025-08-04 7:59 ` AngeloGioacchino Del Regno
2025-08-01 13:26 ` [PATCH 0/9] MediaTek devicetree/bindings warnings sanitization second round Rob Herring (Arm)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250801-mtk-dtb-warnings-v1-4-6ba4e432427b@collabora.com \
--to=julien.massot@collabora.com \
--cc=angelogioacchino.delregno@collabora.com \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=eballetbo@kernel.org \
--cc=eugen.hristev@linaro.org \
--cc=ikjn@chromium.org \
--cc=jmassot@collabora.com \
--cc=kernel@collabora.com \
--cc=krzk+dt@kernel.org \
--cc=lgirdwood@gmail.com \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-sound@vger.kernel.org \
--cc=matthias.bgg@gmail.com \
--cc=mturquette@baylibre.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=sean.wang@kernel.org \
--cc=weiyi.lu@mediatek.com \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).