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Thu, 11 Sep 2025 10:57:22 -0500 Received: from DLEE205.ent.ti.com (157.170.170.85) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 11 Sep 2025 10:57:21 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE205.ent.ti.com (157.170.170.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 11 Sep 2025 10:57:21 -0500 Received: from LTPW0EX92E.dhcp.ti.com (ltpw0ex92e.dhcp.ti.com [10.82.30.14]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58BFvFFI2366393; Thu, 11 Sep 2025 10:57:16 -0500 From: Niranjan H Y To: CC: , , , , , , , , , , , , , , , Niranjan H Y Subject: [PATCH v4 1/6] ASoC: ops: improve snd_soc_get_volsw Date: Thu, 11 Sep 2025 21:26:58 +0530 Message-ID: <20250911155704.2236-1-niranjan.hy@ti.com> X-Mailer: git-send-email 2.33.0.windows.2 Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea * add error handling in case register read fails * add support for clamping the values if the register value read is greater than max value Signed-off-by: Niranjan H Y --- sound/soc/soc-ops.c | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/sound/soc/soc-ops.c b/sound/soc/soc-ops.c index a629e0eac..59e91741b 100644 --- a/sound/soc/soc-ops.c +++ b/sound/soc/soc-ops.c @@ -111,10 +111,14 @@ int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, EXPORT_SYMBOL_GPL(snd_soc_put_enum_double); static int soc_mixer_reg_to_ctl(struct soc_mixer_control *mc, unsigned int reg_val, - unsigned int mask, unsigned int shift, int max) + unsigned int mask, unsigned int shift, int max, + bool clamp) { int val = (reg_val >> shift) & mask; + if (clamp) + val = clamp(val, 0, mc->max); + if (mc->sign_bit) val = sign_extend32(val, mc->sign_bit); @@ -245,29 +249,44 @@ static int soc_put_volsw(struct snd_kcontrol *kcontrol, static int soc_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol, - struct soc_mixer_control *mc, int mask, int max) + struct soc_mixer_control *mc, int mask, int max, + bool clamp) { struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); unsigned int reg_val; - int val; + int val, ret = 0; reg_val = snd_soc_component_read(component, mc->reg); - val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->shift, max); + val = reg_val; + if (val < 0) { + ret = val; + goto get_volsw_done; + } + + val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->shift, max, clamp); ucontrol->value.integer.value[0] = val; if (snd_soc_volsw_is_stereo(mc)) { if (mc->reg == mc->rreg) { - val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->rshift, max); + val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->rshift, + max, clamp); } else { reg_val = snd_soc_component_read(component, mc->rreg); - val = soc_mixer_reg_to_ctl(mc, reg_val, mask, mc->shift, max); + val = reg_val; + if (val < 0) { + ret = val; + goto get_volsw_done; + } + val = soc_mixer_reg_to_ctl(mc, reg_val, mask, + mc->shift, max, clamp); } ucontrol->value.integer.value[1] = val; } - return 0; +get_volsw_done: + return ret; } /** @@ -330,7 +349,8 @@ int snd_soc_get_volsw(struct snd_kcontrol *kcontrol, (struct soc_mixer_control *)kcontrol->private_value; unsigned int mask = soc_mixer_mask(mc); - return soc_get_volsw(kcontrol, ucontrol, mc, mask, mc->max - mc->min); + return soc_get_volsw(kcontrol, ucontrol, mc, mask, + mc->max - mc->min, false); } EXPORT_SYMBOL_GPL(snd_soc_get_volsw); @@ -372,7 +392,7 @@ int snd_soc_get_volsw_sx(struct snd_kcontrol *kcontrol, (struct soc_mixer_control *)kcontrol->private_value; unsigned int mask = soc_mixer_sx_mask(mc); - return soc_get_volsw(kcontrol, ucontrol, mc, mask, mc->max); + return soc_get_volsw(kcontrol, ucontrol, mc, mask, mc->max, false); } EXPORT_SYMBOL_GPL(snd_soc_get_volsw_sx); -- 2.45.2