Re: [PATCH 3/3] ASoC: renesas: fsi: Fix hang by enabling SPU clock

Kuninori Morimoto
2026-04-08T06:33:44Z

Hi Bui, Geert

> > Hmm... fsi_dai_trigger() seems strange.
> > It seems (A) stops clock, and (B) sets register after that.
> > Is this the reason why you get error ? I think (A) and (B) should be
> > reversed. The balance between SNDRV_PCM_TRIGGER_START, and with
> > __fsi_suspend() are also not good.
> > If so, can you use hw_start/stop() ?
>
> Thank you for the guidance. After reordering the sequence and moving the
> SPU power control to fsi_hw_start/shutdown, the system hang is now resolved.

Nice !

> By the way, I’d like to discuss the fsidiv clock handling.
> In the legacy implementation, it was handled here:
> https://elixir.bootlin.com/linux/v7.0-rc7/source/drivers/sh/clk/cpg.c.
> Currently, this has not been ported to the Common Clock Framework (CCF) for
> R8A7740, and it resides in a different register range from the core CPG.
> For v2, would you prefer that I implement a small clock provider for
> fsidiv within
> the FSI driver, or should it be added under drivers/clk/renesas/?

I think it should be under drivers/clk/renesas, but Geert ?

Thank you for your help !!

Best regards
---
Kuninori Morimoto