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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c50a8f7sm10232140b3a.56.2026.04.13.03.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Apr 2026 03:07:56 -0700 (PDT) From: phucduc.bui@gmail.com To: kuninori.morimoto.gx@renesas.com, broonie@kernel.org Cc: lgirdwood@gmail.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, perex@perex.cz, tiwai@suse.com, linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 6/6] ASoC: dt-bindings: renesas,fsi: add support for multiple clocks Date: Mon, 13 Apr 2026 17:07:00 +0700 Message-ID: <20260413100700.30995-7-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260413100700.30995-1-phucduc.bui@gmail.com> References: <20260413100700.30995-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before accessing its registers. Without this clock, any register access leads to a system hang as the FSI block sits behind the SPU bus. Update the binding to support a flexible positional clock list to properly describe the hardware clock tree, including: - SPU bus/bridge clock (spu) for register access. - CPG DIV6 clocks (icka/b) as functional clock parents. - FSI internal dividers (diva/b) for audio clock generation. - External clock inputs (xcka/b) provided by the board. Signed-off-by: bui duc phuc --- Changes in v2: - Rename FSI module clock to "own" to match driver. - Add "spu", "icka/b", "diva/b", "xcka/b" clock names. - Use YAML anchors to constrain clock-names properly. - Add "if" rule to require "spu" clock for r8a7740. - Update example with full clock configuration. - Clean up schema by moving allOf location. .../bindings/sound/renesas,fsi.yaml | 61 +++++++++++++++++-- 1 file changed, 56 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml index df91991699a7..d0ae54f3d321 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -9,9 +9,6 @@ title: Renesas FIFO-buffered Serial Interface (FSI) maintainers: - Kuninori Morimoto -allOf: - - $ref: dai-common.yaml# - properties: $nodename: pattern: "^sound@.*" @@ -38,7 +35,36 @@ properties: maxItems: 1 clocks: - maxItems: 1 + description: | + Clock driving the FSI Controller. The first clock must be + the module clock ("own"). + minItems: 1 + maxItems: 8 + + clock-names: + description: | + Names of clocks corresponding to entries in "clocks": + - "own": Main FSI module clock (must be first and always present) + - "spu": SPU bus/bridge clock. On R8A7740, this clock must be + enabled to allow register access as the FSI block is connected + behind the SPU bus. + - "icka" / "ickb": CPG DIV6 functional clocks for FSI port A/B + - "diva"/"divb": Internal FSI dividers for port A/B used for + audio clock generation + - "xcka"/"xckb": External clock inputs for FSI port A/B + provided by the board + minItems: 1 + items: + - const: own + - &fsi_all_clks + enum: [spu, icka, ickb, diva, divb, xcka, xckb] + - &fsi_no_spu_clks + enum: [icka, ickb, diva, divb, xcka, xckb] + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks power-domains: maxItems: 1 @@ -69,6 +95,27 @@ required: unevaluatedProperties: false +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + const: renesas,fsi2-r8a7740 + then: + properties: + clock-names: + minItems: 2 + items: + - const: own + - const: spu + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + - *fsi_no_spu_clks + examples: - | #include @@ -77,7 +124,11 @@ examples: compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsidiva_clk>, + <&fsidivb_clk>,<&fsiack_clk>,<&fsibck_clk>; + clock-names = "own", "spu", "icka", "ickb", + "diva", "divb", "xcka", "xckb"; power-domains = <&pd_a4mp>; #sound-dai-cells = <1>; -- 2.43.0