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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f6e294sm8461085ad.6.2026.06.02.20.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 20:58:38 -0700 (PDT) From: phucduc.bui@gmail.com To: Heiko Stuebner , Mark Brown , Liam Girdwood Cc: Nicolas Frattaroli , Jaroslav Kysela , Takashi Iwai , linux-sound@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH 1/3] ASoC: rockchip: rockchip_i2s: Use guard() for spin locks Date: Wed, 3 Jun 2026 10:57:39 +0700 Message-ID: <20260603035741.68893-2-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260603035741.68893-1-phucduc.bui@gmail.com> References: <20260603035741.68893-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc Clean up the code using guard() for spin locks. Merely code refactoring, and no behavior change. Signed-off-by: bui duc phuc --- NOTE: This patch is compile-tested only. sound/soc/rockchip/rockchip_i2s.c | 160 +++++++++++++++--------------- 1 file changed, 80 insertions(+), 80 deletions(-) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 0a0a95b4f520..5a5087f4ae03 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -127,52 +127,52 @@ static int rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) unsigned int val = 0; int ret = 0; - spin_lock(&i2s->lock); - if (on) { - ret = regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_TDE_ENABLE, - I2S_DMACR_TDE_ENABLE); - if (ret < 0) - goto end; - ret = regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_START | I2S_XFER_RXS_START); - if (ret < 0) - goto end; - i2s->tx_start = true; - } else { - i2s->tx_start = false; - - ret = regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_TDE_ENABLE, - I2S_DMACR_TDE_DISABLE); - if (ret < 0) - goto end; - - if (!i2s->rx_start) { + scoped_guard(spinlock, &i2s->lock) { + if (on) { + ret = regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_TDE_ENABLE, + I2S_DMACR_TDE_ENABLE); + if (ret < 0) + break; ret = regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + I2S_XFER_TXS_START | I2S_XFER_RXS_START); if (ret < 0) - goto end; - udelay(150); - ret = regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC | I2S_CLR_RXC, - I2S_CLR_TXC | I2S_CLR_RXC); - if (ret < 0) - goto end; - ret = regmap_read_poll_timeout_atomic(i2s->regmap, - I2S_CLR, - val, - val == 0, - 20, - 200); + break; + i2s->tx_start = true; + } else { + i2s->tx_start = false; + + ret = regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_TDE_ENABLE, + I2S_DMACR_TDE_DISABLE); if (ret < 0) - dev_warn(i2s->dev, "fail to clear: %d\n", ret); + break; + + if (!i2s->rx_start) { + ret = regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START | I2S_XFER_RXS_START, + I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + if (ret < 0) + break; + udelay(150); + ret = regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_TXC | I2S_CLR_RXC, + I2S_CLR_TXC | I2S_CLR_RXC); + if (ret < 0) + break; + ret = regmap_read_poll_timeout_atomic(i2s->regmap, + I2S_CLR, + val, + val == 0, + 20, + 200); + if (ret < 0) + dev_warn(i2s->dev, "fail to clear: %d\n", ret); + } } } -end: - spin_unlock(&i2s->lock); + if (ret < 0) dev_err(i2s->dev, "lrclk update failed\n"); @@ -184,53 +184,53 @@ static int rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) unsigned int val = 0; int ret = 0; - spin_lock(&i2s->lock); - if (on) { - ret = regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_RDE_ENABLE, - I2S_DMACR_RDE_ENABLE); - if (ret < 0) - goto end; - - ret = regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_START | I2S_XFER_RXS_START); - if (ret < 0) - goto end; - i2s->rx_start = true; - } else { - i2s->rx_start = false; - - ret = regmap_update_bits(i2s->regmap, I2S_DMACR, - I2S_DMACR_RDE_ENABLE, - I2S_DMACR_RDE_DISABLE); - if (ret < 0) - goto end; + scoped_guard(spinlock, &i2s->lock) { + if (on) { + ret = regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_RDE_ENABLE, + I2S_DMACR_RDE_ENABLE); + if (ret < 0) + break; - if (!i2s->tx_start) { ret = regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + I2S_XFER_TXS_START | I2S_XFER_RXS_START); if (ret < 0) - goto end; - udelay(150); - ret = regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC | I2S_CLR_RXC, - I2S_CLR_TXC | I2S_CLR_RXC); - if (ret < 0) - goto end; - ret = regmap_read_poll_timeout_atomic(i2s->regmap, - I2S_CLR, - val, - val == 0, - 20, - 200); + break; + i2s->rx_start = true; + } else { + i2s->rx_start = false; + + ret = regmap_update_bits(i2s->regmap, I2S_DMACR, + I2S_DMACR_RDE_ENABLE, + I2S_DMACR_RDE_DISABLE); if (ret < 0) - dev_warn(i2s->dev, "fail to clear: %d\n", ret); + break; + + if (!i2s->tx_start) { + ret = regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START | I2S_XFER_RXS_START, + I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); + if (ret < 0) + break; + udelay(150); + ret = regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_TXC | I2S_CLR_RXC, + I2S_CLR_TXC | I2S_CLR_RXC); + if (ret < 0) + break; + ret = regmap_read_poll_timeout_atomic(i2s->regmap, + I2S_CLR, + val, + val == 0, + 20, + 200); + if (ret < 0) + dev_warn(i2s->dev, "fail to clear: %d\n", ret); + } } } -end: - spin_unlock(&i2s->lock); + if (ret < 0) dev_err(i2s->dev, "lrclk update failed\n"); -- 2.43.0