From: Linus Walleij <linusw@kernel.org>
To: Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-sound@vger.kernel.org, Linus Walleij <linusw@kernel.org>
Subject: [PATCH v2 9/9] ASoC: ux500: Program the MSP FIFO watermarks
Date: Wed, 02 Sep 2026 09:55:59 +0200 [thread overview]
Message-ID: <20260902-ux500-msp-fixes-v2-9-4b60b002d55a@kernel.org> (raw)
In-Reply-To: <20260902-ux500-msp-fixes-v2-0-4b60b002d55a@kernel.org>
The DMA engine is configured for four-element bursts, but the MSP
driver never programs the FIFO watermark register and instead depends
on its previous or reset value. The DB8500 DMA request protocol requires
the peripheral watermark to match the DMA packet size.
Program four-element receive and transmit watermarks when configuring
the first direction, before enabling MSP DMA requests.
Fixes: 3592b7f69a54 ("ASoC: Ux500: Add MSP I2S-driver")
Assisted-by: LLM
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
sound/soc/ux500/ux500_msp_i2s.c | 2 ++
sound/soc/ux500/ux500_msp_i2s.h | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index 43dc9b3aa4ef..683b485fb570 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -507,6 +507,8 @@ int ux500_msp_i2s_open(struct ux500_msp *msp,
old_reg &= ~mask;
new_reg |= old_reg;
writel(new_reg, msp->registers + MSP_GCR);
+ writel(MSP_WMRK_TX_4_ELEMENTS | MSP_WMRK_RX_4_ELEMENTS,
+ msp->registers + MSP_WMRK);
}
res = enable_msp(msp, config, first);
diff --git a/sound/soc/ux500/ux500_msp_i2s.h b/sound/soc/ux500/ux500_msp_i2s.h
index 17b5c37a7e5d..2bf2699bdc49 100644
--- a/sound/soc/ux500/ux500_msp_i2s.h
+++ b/sound/soc/ux500/ux500_msp_i2s.h
@@ -62,6 +62,7 @@ enum msp_direction {
#define MSP_SRG 0x10
#define MSP_FLR 0x14
#define MSP_DMACR 0x18
+#define MSP_WMRK 0x1c
#define MSP_IMSC 0x20
#define MSP_RIS 0x24
@@ -228,6 +229,10 @@ enum msp_direction {
#define RDMAE_SHIFT 0
#define TDMAE_SHIFT 1
+/* FIFO watermark register */
+#define MSP_WMRK_RX_4_ELEMENTS BIT(0)
+#define MSP_WMRK_TX_4_ELEMENTS BIT(3)
+
/* Interrupt Register */
#define RX_SERVICE_INT BIT(0)
#define RX_OVERRUN_ERROR_INT BIT(1)
--
2.55.0
next prev parent reply other threads:[~2026-09-02 7:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 7:55 [PATCH v2 0/9] ASoC: ux500: Fix MSP lifecycle, clocking and resources Linus Walleij
2026-09-02 7:55 ` [PATCH v2 1/9] ASoC: ux500: Fix MSP stream lifecycle handling Linus Walleij
2026-09-02 7:55 ` [PATCH v2 2/9] ASoC: ux500: Propagate MSP setup errors Linus Walleij
2026-09-02 7:55 ` [PATCH v2 3/9] ASoC: ux500: Correct MSP frame and bit clock setup Linus Walleij
2026-09-02 7:55 ` [PATCH v2 4/9] ASoC: ux500: Validate MSP DAI configuration Linus Walleij
2026-09-02 7:55 ` [PATCH v2 5/9] ASoC: ux500: Deassert the MSP reset during probe Linus Walleij
2026-09-02 7:55 ` [PATCH v2 6/9] ASoC: ux500: Request the MSP MMIO resource Linus Walleij
2026-09-02 7:55 ` [PATCH v2 7/9] ASoC: ux500: Remove obsolete PRCMU QoS calls Linus Walleij
2026-09-02 7:55 ` [PATCH v2 8/9] ASoC: ux500: Allow repeated MSP prepare calls Linus Walleij
2026-09-02 7:55 ` Linus Walleij [this message]
2026-09-02 11:58 ` [PATCH v2 0/9] ASoC: ux500: Fix MSP lifecycle, clocking and resources Mark Brown
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