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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac61171feesm4077076a91.17.2026.10.14.04.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 04:28:41 -0700 (PDT) From: phucduc.bui@gmail.com To: Mark Brown , AngeloGioacchino Del Regno , Trevor Wu , Ajay Kumar Nandam Cc: Liam Girdwood , Matthias Brugger , Jaroslav Kysela , Takashi Iwai , Kuninori Morimoto , cassiogabrielcontato@gmail.com, Mukesh Ojha , Liviu Dudau , Haotian Zhang , HariKrishna Sagala , linux-sound@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v3 05/16] ASoC: mediatek: mt8195: Fix main clock error handling Date: Wed, 14 Oct 2026 18:27:40 +0700 Message-ID: <20261014112752.683032-6-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261014112752.683032-1-phucduc.bui@gmail.com> References: <20261014112752.683032-1-phucduc.bui@gmail.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc Check the return values of clock enable functions and propagate errors to the caller. Disable previously enabled clocks on failure to match the main clock disable sequence. Fixes: 6746cc858259 ("ASoC: mediatek: mt8195: add platform driver") Signed-off-by: bui duc phuc --- sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 23 +++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c index 03d2c4fd1f85..44cddc2b1564 100644 --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c @@ -716,14 +716,31 @@ static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe) int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) { - mt8195_afe_enable_timing_sys(afe); + int ret; + + ret = mt8195_afe_enable_timing_sys(afe); + if (ret) + return ret; mt8195_afe_enable_afe_on(afe); - mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1); - mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2); + ret = mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1); + if (ret) + goto err_disable_afe_on; + + ret = mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2); + if (ret) + goto err_disable_apll1_tuner; return 0; + +err_disable_apll1_tuner: + mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1); +err_disable_afe_on: + mt8195_afe_disable_afe_on(afe); + mt8195_afe_disable_timing_sys(afe); + + return ret; } int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) -- 2.43.0