From: Rob Herring <robh@kernel.org>
To: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
Cc: Srinivas Kandagatla <srini@kernel.org>,
Mark Brown <broonie@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>,
linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>,
Kumar Anurag Singh <kumar.singh@oss.qualcomm.com>,
Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Subject: Re: [PATCH v8 01/10] ASoC: dt-bindings: qcom,shikra-qaif-cpu: Add binding
Date: Thu, 15 Oct 2026 14:08:02 -0500 [thread overview]
Message-ID: <20261015190802.GA5059-robh@kernel.org> (raw)
In-Reply-To: <CAC-tS8DzW88Lu_k-yKQtyfYc8u5-rh9WKTSanJ6dq6Xo3wp+kQ@mail.gmail.com>
On Mon, Oct 12, 2026 at 12:15:52PM +0530, Harendra Gautam wrote:
> > > +
[...]
> > > +
> > > + qcom,qaif-aif-lane-map:
> > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + description:
> > > + Per-lane direction map, one entry per lane starting from lane 0.
> > > + Use 0 for TX (output/speaker) and 1 for RX (input/mic).
> > > + minItems: 1
> > > + maxItems: 8
> > > + items:
> > > + enum: [0, 1]
> >
> > Can't you use a single uint32 bit mask for this?
> Here intention to keep this consistent with the other tdm mask array properties.
What I mean is use 1-bit per lane/slot. That *is* aligned to the
existing properties:
'^dai-tdm-slot-[rt]x-idle-mask$':
$ref: /schemas/types.yaml#/definitions/uint32
description: Idle slot mask. Optional. A bit being set to 1 indicates
that the corresponding TDM slot is inactive/idle.
It can be extended to an array if you someday have more than 32 lanes,
but it seems you only have 8 ATM.
Rob
next prev parent reply other threads:[~2026-10-15 19:08 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-28 12:52 [PATCH v8 00/10] ASoC: qcom: Add QAIF driver for Shikra audio platform Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 01/10] ASoC: dt-bindings: qcom,shikra-qaif-cpu: Add binding Harendra Gautam
2026-10-06 14:16 ` Rob Herring
2026-10-12 6:45 ` Harendra Gautam
2026-10-15 19:08 ` Rob Herring [this message]
2026-09-28 12:52 ` [PATCH v8 02/10] ASoC: qcom: Add QAIF shared data structures and variant interface Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 03/10] ASoC: qcom: Add QAIF hardware register map Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 04/10] ASoC: qcom: Add QAIF CPU DAI ops, regmap, DT parsing and platform init Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 05/10] ASoC: soc-core: Add snd_soc_of_xlate_dai_name() generic helper Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 06/10] ASoC: qcom: Switch lpass-cpu and qaif-cpu to snd_soc_of_xlate_dai_name() Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 07/10] ASoC: qcom: Add QAIF PCM operations Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 08/10] ASoC: qcom: Add QAIF IRQ handling and platform register Harendra Gautam
2026-09-29 11:36 ` Ajay Kumar Nandam
2026-09-30 5:28 ` Harendra Gautam
2026-09-28 12:52 ` [PATCH v8 09/10] ASoC: qcom: Add Shikra QAIF support Harendra Gautam
2026-09-28 12:53 ` [PATCH v8 10/10] MAINTAINERS: Add Qualcomm QAIF driver entry Harendra Gautam
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