[PATCH 1/3] ASoC: fsl_sai: Defer TERE until stream setup

[Fabio Estevam <festevam@gmail.com>]

On i.MX8MP, TERE also enables MCLK output. Runtime resume sets it
before hw_params has configured the stream, so clocks can start from
stale register values.

In master mode, a custom board with a 400 MHz IPG clock drove BCLK
at 200 MHz before hw_params rewrote xCR2. On first open, reset xCR4
also drove frame sync at about 100 MHz. Later opens can select the
bus clock with DIV=0 and again drive BCLK prematurely.

Enable TERE at the end of hw_params after programming stream format
and clock settings. During runtime resume, restore TERE only when a
configured stream is being resumed.

Fixes: 3e4a82612998 ("ASoC: fsl_sai: MCLK bind with TX/RX enable bit")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 sound/soc/fsl/fsl_sai.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index d232c8f53061..51779d7f8bf8 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -799,6 +799,15 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
 	regmap_write(sai->regmap, FSL_SAI_xMR(tx),
 		     ~GENMASK_U32(min(channels, slots) - 1, 0));
 
+	/*
+	 * On i.MX8MP, TERE also enables the master clock output. Enable it
+	 * after hw_params has configured the stream to avoid briefly driving
+	 * clocks from stale register values.
+	 */
+	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
+		regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
+				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
+
 	return 0;
 }
 
@@ -1983,7 +1992,13 @@ static int fsl_sai_runtime_resume(struct device *dev)
 	if (ret)
 		goto disable_rx_clk;
 
-	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
+	/*
+	 * A fresh stream has not configured its clock divider yet. Keep TERE
+	 * disabled until hw_params in that case; an already configured stream
+	 * needs it restored after a system suspend.
+	 */
+	if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output &&
+	    sai->mclk_streams)
 		regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
 				   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
 
-- 
2.43.0