[PATCH 11/11] soundwire: amd: provide defaults for the bus clock properties

[Corey Smith <corsmith@gmail.com>]

The manager clock configuration was moved from hard-coded values to the
MIPI DisCo properties (max clock frequency, default frame rate and
default row size).  Rembrandt (ACP6x) firmware does not describe those
properties on the SoundWire link nodes, so sdw_master_read_prop()
leaves them zeroed and amd_sdw_clk_init_ctrl() aborts the manager
start-up with -EINVAL.  On the HP Dragonfly Pro ONE this makes the
whole snd-pci-ps probe fail with error -22 and no SoundWire device is
created.

Restore the legacy defaults when the firmware does not provide them:
a 12 MHz bus clock, a 48 kHz frame rate and the 50 x 10 frame shape.
Platforms whose firmware does describe the properties are unaffected.

Assisted-by: LLM
Signed-off-by: Corey Smith <corsmith@gmail.com>
---
 drivers/soundwire/amd_manager.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c
index 697ec93..d451428 100644
--- a/drivers/soundwire/amd_manager.c
+++ b/drivers/soundwire/amd_manager.c
@@ -25,6 +25,12 @@
 
 #define DRV_NAME "amd_sdw_manager"
 
+/*
+ * Frame rate used when firmware does not describe the MIPI DisCo clock
+ * properties on the SoundWire link nodes.
+ */
+#define AMD_SDW_DEFAULT_FRAME_RATE	48000
+
 #define to_amd_sdw(b)	container_of(b, struct amd_sdw_manager, bus)
 
 static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager)
@@ -752,8 +758,27 @@ static int sdw_master_read_amd_prop(struct sdw_bus *bus)
 
 static int amd_prop_read(struct sdw_bus *bus)
 {
+	struct sdw_master_prop *prop = &bus->prop;
+
 	sdw_master_read_prop(bus);
 	sdw_master_read_amd_prop(bus);
+
+	/*
+	 * Some platforms, Rembrandt (ACP6x) in particular, do not describe
+	 * the MIPI DisCo clock properties on the SoundWire link nodes.  The
+	 * values read by sdw_master_read_prop() then stay zeroed and
+	 * amd_sdw_clk_init_ctrl() fails with -EINVAL.  Restore the defaults
+	 * the driver used before the clock configuration was moved to
+	 * firmware: a 12 MHz bus clock, a 48 kHz frame rate and the 50 x 10
+	 * frame shape.
+	 */
+	if (!prop->max_clk_freq)
+		prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;
+	if (!prop->default_frame_rate)
+		prop->default_frame_rate = AMD_SDW_DEFAULT_FRAME_RATE;
+	if (!prop->default_row)
+		prop->default_row = AMD_SDW_DEFAULT_ROWS;
+
 	return 0;
 }