From: phucduc.bui@gmail.com
To: Binbin Zhou <zhoubinbin@loongson.cn>,
Binbin Zhou <zhoubb.aaron@gmail.com>,
Mark Brown <broonie@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
Yingkun Meng <mengyingkun@loongson.cn>,
linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org,
bui duc phuc <phucduc.bui@gmail.com>
Subject: [PATCH v2 2/3] ASoC: loongson: Use FIELD_PREP() for register fields
Date: Wed, 28 Oct 2026 17:41:37 +0700 [thread overview]
Message-ID: <20261028104138.26973-3-phucduc.bui@gmail.com> (raw)
In-Reply-To: <20261028104138.26973-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Use FIELD_PREP() to set the bit fields in the I2S configuration
registers instead of open-coded shifts.
This makes the register field assignments clearer and consistent
between revision 0 and revision 1.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/loongson/loongson_i2s.c | 11 ++++++-----
sound/soc/loongson/loongson_i2s.h | 5 +++++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/sound/soc/loongson/loongson_i2s.c b/sound/soc/loongson/loongson_i2s.c
index aebea177e7e0..0d5278203024 100644
--- a/sound/soc/loongson/loongson_i2s.c
+++ b/sound/soc/loongson/loongson_i2s.c
@@ -80,10 +80,10 @@ static int loongson_i2s_hw_params(struct snd_pcm_substream *substream,
mclk_ratio = DIV_ROUND_CLOSEST(clk_rate, (sysclk * 2)) - 1;
/* According to 2k1000LA user manual, set bits == depth */
- val |= (bits << 24);
- val |= (bits << 16);
- val |= (bclk_ratio << 8);
- val |= mclk_ratio;
+ val = FIELD_PREP(LS_I2S_CFG_LR_LEN_MASK, bits) |
+ FIELD_PREP(LS_I2S_CFG_TX_RES_DEPTH_MASK, bits) |
+ FIELD_PREP(LS_I2S_CFG_BCLK_RATIO_MASK, bclk_ratio) |
+ FIELD_PREP(LS_I2S_CFG_MCLK_RATIO_MASK, mclk_ratio);
regmap_write(i2s->regmap, LS_I2S_CFG, val);
break;
@@ -106,7 +106,8 @@ static int loongson_i2s_hw_params(struct snd_pcm_substream *substream,
}
regmap_update_bits(i2s->regmap, LS_I2S_CFG, mask, val);
- val = (mclk_ratio_frac << 16) | mclk_ratio;
+ val = FIELD_PREP(LS_I2S_CFG1_MCLK_RATIO_FRAC_MASK, mclk_ratio_frac) |
+ FIELD_PREP(LS_I2S_CFG1_MCLK_RATIO_MASK, mclk_ratio);
regmap_write(i2s->regmap, LS_I2S_CFG1, val);
break;
diff --git a/sound/soc/loongson/loongson_i2s.h b/sound/soc/loongson/loongson_i2s.h
index 457d90e3d5b6..0c280e9b7505 100644
--- a/sound/soc/loongson/loongson_i2s.h
+++ b/sound/soc/loongson/loongson_i2s.h
@@ -45,6 +45,11 @@
#define LS_I2S_CFG_TX_RES_DEPTH_MASK GENMASK(23, 16)
#define LS_I2S_CFG_BCLK_RATIO_MASK GENMASK(15, 8)
#define LS_I2S_CFG_RX_RES_DEPTH_MASK GENMASK(7, 0) /* rev 1 */
+#define LS_I2S_CFG_MCLK_RATIO_MASK GENMASK(7, 0) /* rev 0 */
+
+/* Loongson I2S Config 1 Register (rev 1) */
+#define LS_I2S_CFG1_MCLK_RATIO_FRAC_MASK GENMASK(31, 16)
+#define LS_I2S_CFG1_MCLK_RATIO_MASK GENMASK(15, 0)
#define LS_I2S_DRVNAME "loongson-i2s"
--
2.43.0
next prev parent reply other threads:[~2026-10-28 10:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 10:41 [PATCH v2 0/3] ASoC: loongson: Fix configuration and clock error handling phucduc.bui
2026-10-28 10:41 ` [PATCH v2 1/3] ASoC: loongson: Fix IISConfig0 update in hw_params for rev 1 phucduc.bui
2026-10-28 10:41 ` phucduc.bui [this message]
2026-10-28 10:41 ` [PATCH v2 3/3] ASoC: loongson: Handle clock enable errors in set_fmt phucduc.bui
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