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([183.91.15.56]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b245c1c272sm15595215c88.8.2026.11.05.02.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 02:44:04 -0800 (PST) From: phucduc.bui@gmail.com To: Shengjiu Wang , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Mark Brown Cc: Liam Girdwood , Jaroslav Kysela , Takashi Iwai , linuxppc-dev@lists.ozlabs.org, linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org, bui duc phuc Subject: [PATCH v2 10/10] ASoC: fsl_sai: Don't write CHMOD to the other direction's xCR4 Date: Thu, 5 Nov 2026 17:42:37 +0700 Message-ID: <20261105104237.38542-11-phucduc.bui@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261105104237.38542-1-phucduc.bui@gmail.com> References: <20261105104237.38542-1-phucduc.bui@gmail.com> X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: bui duc phuc When the current direction is synced to the other one, hw_params() also writes the frame configuration to the other direction's xCR4. The mask includes CHMOD, whose value is set by the current direction (Tx only) but written to the other one, so it is wrong: - TCR4[CHMOD] is cleared, while Tx needs it set (output mode). - RCR4 bit 5 is set, while it is reserved and must be written as 0. CHMOD is not part of the frame configuration, so drop it from the mask. Fixes: f4c4b1bb2f5a ("ASoC: fsl_sai: Set SAI Channel Mode to Output Mode") Signed-off-by: bui duc phuc --- sound/soc/fsl/fsl_sai.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index c61703ddb6f8..430e896d064e 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -720,8 +720,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, if (fsl_sai_dir_is_synced(sai, adir)) { regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), - FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | - FSL_SAI_CR4_CHMOD_MASK, + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, val_cr4); regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | -- 2.43.0