Re: [PATCH] ASoC: codecs: cs42l84: set up PLL for more sample rates

[James Calligeros <jcalligeros99@gmail.com>]

Hi Mark,

On Wednesday, 11 March 2026 4:51:25 am Australian Eastern Standard Time Mark 
Brown wrote:
> These are adding 44.1kHz based rates with a new value for MCLK (the
> final value in each entry).  Those values are read with a switch
> statement in cs42l84_pll_config but that only has an entry for 24.576MHz
> for some reason, that won't match 112.896MHz and will just leave the
> pll_mclk_f with whatever value it had before.  Don't we need a new case
> statement there for the new MCLK?

Yes and no. According to the datasheet, the chip only requires the PLL to be
in the "region" of 12 or 24 MHz. Since we only have 12 MHz region PLL configs
in our table, this does actually work without changes, albeit unintutitively
(and accidentally).

On 42L42, this is configured using the MCLKDIV and MCLK_SRC_SEL bits, which
behave identically to what we've ended up calling MCLK_F. I will add an
explicit arm to the case statement and a comment explaining this so that it is
not ambiguous.

Regards,
James