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Stavinskii" Cc: Arnd Bergmann , linux-sound@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org Date: Mon, 02 Feb 2026 22:31:24 +0100 In-Reply-To: <20260202095323.1233553-1-arnd@kernel.org> References: <20260202095323.1233553-1-arnd@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.2 Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Arnd! On Mon, 2026-02-02 at 10:53 +0100, Arnd Bergmann wrote: > From: Arnd Bergmann >=20 > cv1800b_adc_setbclk_div() does four 64-bit divisions in a row, which 3 of the 4 divisors are actually a power of two, so it would be a bug in the compiler to issue a division for them... Regarding the 64 bits: seems that the actual issue is the tmp variable that is of u64 type for no reason, because priv->mclk_rate is only u32. Maybe turning tmp into a u32 would avoid unnecessary 64-bit division altogether? > is rather inefficient on 32-bit systems, and using the plain division > causes a build failure as a result: >=20 > ERROR: modpost: "__aeabi_uldivmod" [sound/soc/sophgo/cv1800b-sound-adc.ko= ] undefined! >=20 > Consolidate those into a single division using the div_u64() macro. >=20 > Fixes: 4cf8752a03e6 ("ASoC: sophgo: add CV1800B internal ADC codec driver= ") > Signed-off-by: Arnd Bergmann > --- > =C2=A0sound/soc/sophgo/cv1800b-sound-adc.c | 7 ++----- > =C2=A01 file changed, 2 insertions(+), 5 deletions(-) >=20 > diff --git a/sound/soc/sophgo/cv1800b-sound-adc.c b/sound/soc/sophgo/cv18= 00b-sound-adc.c > index 794030b713e9..b66761156b99 100644 > --- a/sound/soc/sophgo/cv1800b-sound-adc.c > +++ b/sound/soc/sophgo/cv1800b-sound-adc.c > @@ -105,11 +105,8 @@ static int cv1800b_adc_setbclk_div(struct cv1800b_pr= iv *priv, unsigned int rate) > =C2=A0 if (!priv->mclk_rate || !rate) > =C2=A0 return -EINVAL; > =C2=A0 > - tmp =3D priv->mclk_rate; > - tmp /=3D CV1800B_RXADC_WORD_LEN; > - tmp /=3D CV1800B_RXADC_CHANNELS; > - tmp /=3D rate; > - tmp /=3D 2; > + tmp =3D div_u64(priv->mclk_rate, CV1800B_RXADC_WORD_LEN * > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CV1800B_RXADC_CHANNELS * rate * 2); > =C2=A0 > =C2=A0 if (!tmp) { > =C2=A0 dev_err(priv->dev, "computed BCLK divider is zero\n"); --=20 Alexander Sverdlin.