From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 457133D25CB; Fri, 15 May 2026 11:15:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778843724; cv=none; b=M97WPqYvMLSOZHweX/AaXQ1JZ/o7zkpzsW0vbUs5HzIXj7BT/Da4mAggemXseGUvWZzQX3dRAJ837c61xX05SYchJUPQT2iLyhTGcP5JXH0yL758bJepWUCPU5hBcpNBtwi6DLdA7Zh7Sd8StQwbgcVzVas/VbMMeL5FFAZpsLY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778843724; c=relaxed/simple; bh=R3MLm+HTCPg11JEGwyO6cNd+P5MrVRELYO/S9ybE160=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=LgIXCsRoN3K2jUav8Qid3KA69KtJac9ue8ulzpKtIPpkoQNjLhS38o9GHm2sGcVeij1sDecUXa85Hx7d1WgOTnX+XZfr5jrbzB5rCCepf+5iOkbW/eBKBOfYe4/vl+zgDuvjZXXr90meOESBNnCE96hzyy1CV35l3Uup/k5vagc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s11HboqW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s11HboqW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7086CC2BCB0; Fri, 15 May 2026 11:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778843723; bh=R3MLm+HTCPg11JEGwyO6cNd+P5MrVRELYO/S9ybE160=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=s11HboqWgBCn1CZkQkgqZ6a2tYVcC1FbVBEQKl1sTs1c3ovNK6pC1kh9bJSMwnHk6 LoslfbkH2z0KpU91KGjqI0L3BTWE4rfTE5uB10yZNSmHJmlF5Vzqm3BOSkgAFDiBtM RdfaxBQw2m8QixHgfCsMmX0TKOdWXTAJmbgqDb/OMLg0axlaA2ua2wfJ1xp65BlydT 3V1gGYcxjSncgHXHK0AdWMYsTR0vFgvL0SBKUjqNuGb2TexkFziGysbf6HB4OsufrN tH62fyUVcozgaTi1CIYnoBrVMbWByLpVhJMreSp7zWj21AIvuyQ6LvZUNoa/tJmMIV BVTDAUswNNSUQ== Message-ID: <4fc78848-5eb2-48fa-8cdb-99b210844fc4@kernel.org> Date: Fri, 15 May 2026 13:15:18 +0200 Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/10] ASoC: dt-bindings: renesas,fsi: add support multiple clocks To: Bui Duc Phuc Cc: kuninori.morimoto.gx@renesas.com, broonie@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sound@vger.kernel.org, magnus.damm@gmail.com, perex@perex.cz, robh@kernel.org, tiwai@suse.com, Geert Uytterhoeven References: <20260510084303.122426-1-phucduc.bui@gmail.com> <20260510084303.122426-2-phucduc.bui@gmail.com> <20260515-transparent-calculating-ocelot-bdec04@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 15/05/2026 12:20, Bui Duc Phuc wrote: > Hi Krzysztof, > > On Fri, May 15, 2026 at 1:46 PM Krzysztof Kozlowski wrote: >>> The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before >>> accessing its registers. Without this clock, any register access leads to >> >> But why are you adding all these clocks to sh73a0 as well? >> > > The FSI IP and its clock management seem to be architecturally identical between > these two SoCs. For instance, both sh73a0 and r8a7740 use the exact same > register address 0xe6150084 for the SPU DIV6 clock control. Therefore, > it's highly > likely they share the same bus dependency for register access. This must be also mentioned in the commit msg. > > If there are further doubts regarding the sh73a0 internal bus topology, perhaps > @Geert Uytterhoeven could kindly double-check if this SPU bridge clock > dependency also applies to sh73a0 as it does for r8a7740? > > > >>> - CPG DIV6 clocks (icka/b) as functional clock parents. >> >> You do not need to add parents of clocks. >> > > I see your point. I will update the description to list icka/b simply as > 'functional clocks' instead of 'parents', as their hierarchy is already > handled by the clock provider. > > > >>> - FSI internal dividers (diva/b) for audio clock generation. >> >> Internal dividers do not have representation. They are internal. > > I see your point. What I intended to describe was the internal divider > configuration for Port A/B within the FSIDIV block, not separate clock > representations in CCF. > I will rephrase this as: > DIVA/DIVB divider settings used for audio clock generation. > > In v1, I brought up this FSIDIV topic with Morimoto and Geert. > >>> By the way, I’d like to discuss the fsidiv clock handling. >>> In the legacy implementation, it was handled here: >>> https://elixir.bootlin.com/linux/v7.0-rc7/source/drivers/sh/clk/cpg.c. >>> Currently, this has not been ported to the Common Clock Framework (CCF) for >>> R8A7740, and it resides in a different register range from the core CPG. >>> For v2, would you prefer that I implement a small clock provider for >>> fsidiv within >>> the FSI driver, or should it be added under drivers/clk/renesas/? > >> I think it should be under drivers/clk/renesas, but Geert ? > > However, I haven't heard back from Geert yet. > >> This cannot be flexible. >> >>> + - fck # Main FSI module clock >>> + - spu # optional SPU bus/bridge clock >>> + - icka # optional CPG DIV6 functional clocks for FSI port A >>> + - ickb # optional CPG DIV6 functional clocks for FSI port B >>> + - diva # optional Internal FSI dividers for port A used for audio clock generation >>> + - divb # optional Internal FSI dividers for port B used for audio clock generation >>> + - xcka # optional External clock inputs for FSI port A provided by the board >>> + - xckb # optional External clock inputs for FSI port B provided by the board > > There is also an ongoing discussion about how strict/flexible > the DT clock constraints should be for FSI in this thread: > https://lore.kernel.org/all/CAABR9nEhOTz1-0NmCMTbz=-+782Pto0yovSQhBXrXqhLwMg80Q@mail.gmail.com/ > > Geert and Rob have already shared some opinions there, > so it may be useful to continue the discussion in that thread as well. I missed that before sending my reply. Best regards, Krzysztof