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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4VRrZN4HdTO2ZnZtPAm/RVeJPWuE1I/D989zer7kLQf7X65JKfu4sFlSXjD1?= =?us-ascii?Q?OC3gnGhpC0neSKeYy32rExAgTOYIgDg8ez5FaQhw0jYMLcM13SczkUgSR/wj?= =?us-ascii?Q?iua+u1HYKHe9bjhU5hob91VAY6ovknqAHxQWGx5a6KjG+p5zNQqwntfBfjDu?= =?us-ascii?Q?dXXRDNMhCr0HDwdZazxnfM+D7i7BxUidrSObJs7Q/hYG0ZmgOAv7xsWRtjQ4?= =?us-ascii?Q?S6QrODZC3RPsYjCmmrhwihDxEOhYOqTEnv8XZ+b89BIFlObdVKRs3FfLb7YH?= =?us-ascii?Q?zsJBkLpXyBWp3KXKgm+6gT3b8GBbuT3uU29as3AuYtcx3JkoFHKz+KB7/ZPE?= =?us-ascii?Q?ji7tvZs55Cb+fRnyHFI/482lpLICA2crHn0W/vgL3oQwPdvFoh4qLiaJb4L6?= =?us-ascii?Q?xIm4RMboQ8vkkcUWZ0ay1HpFgPMzvCCIgDDi4rIQiyiHdi2dN8EBfAuwhmqb?= =?us-ascii?Q?qWCDmhJ3sbwqypkG6ddluqrRytlN4/mC0yBDH3DA7PtWbrqjCpex9fT909mB?= =?us-ascii?Q?CmT3gpUygIStlro4TV9TcLYEvLjRsBZWIgtqE6gUgNzIwqXmNt3kYkUrO7Nc?= =?us-ascii?Q?ZcjCsRLIcaPOm3Rm4f1FYyeQgTdBKU/gv4MWPwh8dI5tP4mX059imQ0Cob1/?= =?us-ascii?Q?Se83vA5BSYLcjEfKTqRPN0KVe4i4Ip5oQ46eDGBaLvOvVSbWTYQk99e1wref?= =?us-ascii?Q?h/vyBcfE5QKSLOWoR0iWJZHhWRBbqUxBnqWfNh8Bnz8Cze5Fd6vWqI+bLUBm?= =?us-ascii?Q?RdOquy+ZTWm+vg/06Wf8uT0m291PGJrs9P9GRJ/DPPrXTZao0ZB9PVAoNKKL?= =?us-ascii?Q?dN2OJEdvDIGx+PM3bjYaJNYZup1KOyIEX8mqYmoMHPMoRRrcTpvPq61OoG/0?= =?us-ascii?Q?fm8mBExx0rClluCeaQwuE7G+wLokLrGGumGil674KNIlRDSYQaWF0KKp3zYe?= =?us-ascii?Q?mvWTEnyd4vtyNrxpjBZ+YHtM/wIu1/GuJvLPdPUhCOZ+mY1teVRaSWaAFgIK?= =?us-ascii?Q?y4if83gu3bBD2GYQruPccOj+/9tKqfU8LvVpCX+5PD9oc/8ZVNuESeVDOBIt?= =?us-ascii?Q?fvwUqcOeKP34MLHpEzfFpRLiiNoEvofGFHPcfED1gppfzKkqED1nRoh5MluK?= =?us-ascii?Q?6MBrIFCgVuiqouQuP033ZHl5bc1an2sXmGYtBMLoZfDXREJc8w1auw4d9Kdt?= =?us-ascii?Q?T96xROq/53DesbcCOscoARuzhraO5qKMb8ESqixbeZ6r3nLpW17aJbQyqDwU?= =?us-ascii?Q?NJ3+vAKFTfUIB7W2pcF55LOB3uiFcrZh5/OWgokNeimGAIbG/zsxXo6GW6Mz?= =?us-ascii?Q?xaei5VhodLqU62y9uk5QcOVcfsgxd7FEpv64yxya7phHpTOIw7FSf4hE/1G9?= =?us-ascii?Q?Rel+RZo8MWQIIfvNdgMkytKCoVdQZPuK7x8HgX491qKwcSwD+KydphlPelAq?= =?us-ascii?Q?zheYy6UvKAtg62K+kuI8QoG0R1piuWrI7rSM4mw8nVNYbPdkP5wLuvz4AL1i?= =?us-ascii?Q?nygzqcNHL6dqs6Z7IchpsSTbV3tvnXBemgyaDoT+09iQiyuRAJgG4d1Usiql?= =?us-ascii?Q?k42rtvpfde29E5ECgmxuD/EkZdzIxHI0d/FXtMARC5K0QzwV+zQG28RBcT7X?= =?us-ascii?Q?PAL6NZpSVmJfHZgU5kgveCZ1q+I7IjPhH5gZxWXlylsd6SLPbsCfSA1tAn1X?= =?us-ascii?Q?fcHzhuiOny4l95hapNSwFw3CMD+rY7MMruy60fC4qNLG/We+?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 373cb774-97b9-44f9-921d-08deb071e912 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9372.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2026 22:00:42.6659 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Cb9PMFNh11COn+zwkd7kDG9q+gIzawWXXhxJnIQjIRZ4lrc5UHT3HO4MBR8aOfEltpEVfDQALQK6nIsiwaXFSA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMDPR04MB11553 On Tue, May 12, 2026 at 03:12:13PM +0300, Claudiu Beznea wrote: > Add cyclic DMA support to the RZ DMAC driver. A per-channel status bit is > introduced to mark cyclic channels and is set during the DMA prepare > callback. The IRQ handler checks this status bit and calls > vchan_cyclic_callback() accordingly. > > Signed-off-by: Claudiu Beznea > --- > > Changes in v5: > - none > > Changes in v4: > - drop the nxla update logic in rz_dmac_lmdesc_recycle() as this is > not needed for any kind of transfers > - drop the update of channel->status = 0 from rz_dmac_free_chan_resources() > and rz_dmac_terminate_all() as this was moved in patch 09/17 > > Changes in v3: > - updated rz_dmac_lmdesc_recycle() to restore the lmdesc->nxla > - in rz_dmac_prepare_descs_for_cyclic() update directly the > desc->start_lmdesc with the descriptor pointer insted of the > descriptor address > - used rz_dmac_lmdesc_addr() to compute the descritor address > - set channel->status = 0 in rz_dmac_free_chan_resources() > - in rz_dmac_prep_dma_cyclic() check for invalid periods or buffer len > and limit the critical area protected by spinlock > - set channel->status = 0 in rz_dmac_terminate_all() > - updated rz_dmac_calculate_residue_bytes_in_vd() to use > rz_dmac_lmdesc_addr() > - dropped goto in rz_dmac_irq_handler_thread() as it is not needed > anymore; dropped also the local variable desc > > Changes in v2: > - none > > drivers/dma/sh/rz-dmac.c | 136 +++++++++++++++++++++++++++++++++++++-- > 1 file changed, 130 insertions(+), 6 deletions(-) > > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c > index 2de519b581b6..d6ad070be705 100644 > --- a/drivers/dma/sh/rz-dmac.c > +++ b/drivers/dma/sh/rz-dmac.c > @@ -35,6 +35,7 @@ > enum rz_dmac_prep_type { > RZ_DMAC_DESC_MEMCPY, > RZ_DMAC_DESC_SLAVE_SG, > + RZ_DMAC_DESC_CYCLIC, > }; > > struct rz_lmdesc { > @@ -67,9 +68,11 @@ struct rz_dmac_desc { > /** > * enum rz_dmac_chan_status: RZ DMAC channel status > * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callbacks > + * @RZ_DMAC_CHAN_STATUS_CYCLIC: Channel is cyclic > */ > enum rz_dmac_chan_status { > RZ_DMAC_CHAN_STATUS_PAUSED, > + RZ_DMAC_CHAN_STATUS_CYCLIC, suggest add new field bool iscycle in rz_dmac_chan. > }; > > struct rz_dmac_chan { > @@ -191,6 +194,7 @@ struct rz_dmac { > > /* LINK MODE DESCRIPTOR */ > #define HEADER_LV BIT(0) > +#define HEADER_WBD BIT(2) > > #define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16 > #define RZ_DMAC_MAX_CHANNELS 16 > @@ -431,6 +435,57 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel) > channel->chctrl = 0; > } > ... > > +static struct dma_async_tx_descriptor * > +rz_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, > + size_t buf_len, size_t period_len, > + enum dma_transfer_direction direction, > + unsigned long flags) > +{ > + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan); > + struct rz_dmac_desc *desc; > + size_t periods; > + > + if (!is_slave_direction(direction)) > + return NULL; > + > + if (!period_len || !buf_len) > + return NULL; > + > + periods = buf_len / period_len; > + if (!periods || periods > DMAC_NR_LMDESC) > + return NULL; > + > + scoped_guard(spinlock_irqsave, &channel->vc.lock) { > + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC)) > + return NULL; > + > + desc = list_first_entry_or_null(&channel->ld_free, struct rz_dmac_desc, node); sugest use dma_pool manage desc, so ld_free can be removed. Frank