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The > MCLK2 source (0x08) therefore never matches, so MCLK2 is never enabled > for an AIF clocked from it, and the AIF relies on other users of that > clock to keep it running. > > On the Exynos4412 Trats2 board, AIF1 and SYSCLK run from MCLK2, the > 32768Hz PMIC clock, while the codec is idle. That clock is shared with > the WLAN and Bluetooth chips, which enable it only once their drivers > are loaded. Until then the codec runs from a stopped clock: FLL1 fails > to lock when configured from that state, and the codec floods the > kernel log with FIFO error interrupts once a digital path is powered > up: > > wm8994-codec wm8994-codec: Timed out waiting for FLL lock > wm8994-codec wm8994-codec: FIFO error > > Booting with clk_ignore_unused, which keeps that clock running from > the bootloader, makes both issues disappear. > > Fixing just the comparison is not enough. The AIF clock source can > be changed while the AIF clock is running, for example the Midas > machine driver switches AIF1 between MCLK2 and FLL1 while AIF1CLK is > kept enabled for jack detection. Looking up the clock again on disable > can then release a different MCLK than the one enabled, leaking the > enable count of one clock and underflowing the other. > > Shift the field value before decoding it, and remember which MCLK has > been enabled for each AIF, so that the same clock is released on > disable. While at it, report the MCLK number 1-based in the error > message. > > Fixes: 001b83d395ab ("ASoC: wm8994: Add support for MCLKn clock gating") > Signed-off-by: Marek Szyprowski > --- Reviewed-by: Charles Keepax Thanks, Charles