From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7D82197A9A; Thu, 31 Oct 2024 09:59:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730368762; cv=none; b=d9bBWBjZonuNyels0AVt4r1KwG68LknV9jXmBfpPpUyuSe+V/YWhxvJlYq6puZpIlj7WiZZ21T9twjTftR+oCiy6H7UMNClX2UEHONel+YrNHcbf7DQtHvUpWe/AeFHKChpkmF96tYMpeS2bPVmnBkDWi5CsqpZxL26V/oFEJvI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730368762; c=relaxed/simple; bh=0Z/Ae2UNtxEs3oOIzL9noQbt9KWPAGJ+Ppa2XVlpXeU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=uKZjlYRH/9WWnzPkz6zJbYt2uIjYyDQzJAWq/yLqJsQPRnQrBanN4RJKLj8oGJm8uYPnO5p1PnzPyfqYGts7+zTsBDm/8bcJ2W6MNl/m/9IrfMg6aT/b0uCgr+KJJyvXU+FJ4lQhE9Z78eHziuF2Ku1bkRan2UlYV+9yEOOkLG0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PmGBbOJ0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PmGBbOJ0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 06069C4CEC3; Thu, 31 Oct 2024 09:59:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730368761; bh=0Z/Ae2UNtxEs3oOIzL9noQbt9KWPAGJ+Ppa2XVlpXeU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=PmGBbOJ0DKa25hH+c1NLm5IW6UAQOPuqujiGj89c+Dmkl9+bri+eg6qS8wnnXSXud HduqN9MsQsDJiHd1E6FqtGnpgikzYv4vXhYymJDHNWcyv0BvGesK3LdaW+IrkEUox+ Kb4xLAsh2aLrzLbOn1qHAxuAP6v6unc816JgeplfgO4QyBxXtYXTUH6u9Xc30DagaT Y01NeeLyCEZcvkv1GzH5/2HrD+IdpVJcIsK9lN8+hu6m4KSns8146sCQ5uy8C8nKNN ED2MFbA8ebI8UEGkBDs/KparCPlu/s1J7APBi3pDIe4bKyPVr87hJG/rBFdxrj+3cQ MbpxQWun36q6g== Message-ID: Date: Thu, 31 Oct 2024 10:59:12 +0100 Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] ASoC: dt-bindings: wcd937x-sdw: Add static channel mapping support To: Mohammad Rafi Shaik Cc: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Bard Liao , Jaroslav Kysela , Takashi Iwai , Pierre-Louis Bossart , Sanyog Kale , linux-arm-msm@vger.kernel.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_rohkumar@quicinc.com, kernel@quicinc.com References: <20241023061326.3871877-1-quic_mohs@quicinc.com> <20241023061326.3871877-2-quic_mohs@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 30/10/2024 06:07, Mohammad Rafi Shaik wrote: > On 10/23/2024 1:22 PM, Krzysztof Kozlowski wrote: >> On Wed, Oct 23, 2024 at 11:43:23AM +0530, Mohammad Rafi Shaik wrote: >>> Add static channel mapping between master and slave rx/tx ports for >>> Qualcomm wcd937x soundwire codec. >>> >>> Currently, the channel mask for each soundwire port is hardcoded in the >>> wcd937x-sdw driver, and the same channel mask value is configured in the >>> soundwire master. >>> >>> The Qualcomm boards like the QCM6490-IDP require different channel mask settings >>> for the soundwire master and slave ports. >> >> Different than what? Other wcd937x? Which are these? >> > For Qualcomm QCM6490-IDP board soundwire master needs a different > channel mask setting. I understand, but I asked different than which board? Maybe all boards needs this different channel setting, so basically it is "not different". > > The wcd937x channel mask values are hardcoded in wcd driver. > https://elixir.bootlin.com/linux/v6.12-rc5/source/sound/soc/codecs/wcd937x-sdw.c#L35 > https://elixir.bootlin.com/linux/v6.12-rc5/source/sound/soc/codecs/wcd938x-sdw.c#L37 > > In case of QCM6490-IDP the soundwire master and wcd937x require > different channel mask settings, not the same. > For Example, wcd937x ADC2 connection > > Master Slave (wcd937x) > +--------------+ +--------------+ > | +--------+ | | +--------+ | > ADC1 ----->| | PORT1 | | | | TX1 | > |<-----------ADC1 > ADC2 ----->| | | | | | | | > | +--------+ | | +--------+ | > | | | | > ADC3 ----->| +--------+ | | +--------+ | > | | PORT2 | | | | TX2 | > |<-----------ADC2 > | | | | | | | > |<-----------ADC3 > | +--------+ | | +--------+ | > | | | | > | +--------+ | | +--------+ | > DMIC0...DMIC3------>| | PORT3 | | | | TX3 | > |<-----------DMIC0...DMIC3 > | | | | | | | > |<-----------MBHC > | +--------+ | | +--------+ | > | | | | > | +--------+ | | +--------+ | > DMIC4...DMIC3 ----->| | PORT4 | | | | TX4 | > |<-----------DMIC4...DMIC7 > | | | | | | | | > | +--------+ | | +--------+ | > | | | | > +------------- + +--------------+ > > > For ADC2, The Slave needs to configure TX2 Port with channel mask value > 1 and > For Master, it required PORT1 with channel mask value 2. > > > In existing design master and slave configured with same channel mask, > it will fail ADC2. > The new design will help to configure channel mapping between master and > slave from DT. > >>> >>> With the introduction of the following channel mapping properties, it is now possible >>> to configure the master channel mask directly from the device tree. >>> >>> The qcom,tx-channel-mapping property specifies the static channel mapping between the slave >>> and master tx ports in the order of slave port channels which is adc1, adc2, adc3, adc4, >>> dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. >> >> I still don't get what is the channel here. >> > Typo error, > > The qcom,tx-channel-mapping property specifies the static channel > mapping between the slave > > and master tx ports in the order of slave port channel index which are > adc1, adc2, adc3, adc4, > > dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. > > > > https://elixir.bootlin.com/linux/v6.12-rc5/source/sound/soc/codecs/wcd937x.h#L599 > > > > Will be fixed in the next version > >>> >>> The qcom,rx-channel-mapping property specifies static channel mapping between the slave >>> and master rx ports in the order of slave port channels which is hph_l, hph_r, clsh, >>> comp_l, comp_r, lo, dsd_r, dsd_l. >> >> And this description copies binding :/. >> >> Please wrap commit message according to Linux coding style / submission >> process (neither too early nor over the limit): >> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 >> > > Ack > >>> >>> Signed-off-by: Mohammad Rafi Shaik >>> --- >>> .../bindings/sound/qcom,wcd937x-sdw.yaml | 36 +++++++++++++++++++ >>> 1 file changed, 36 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml >>> index d3cf8f59cb23..a6bc9b391db0 100644 >>> --- a/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml >>> +++ b/Documentation/devicetree/bindings/sound/qcom,wcd937x-sdw.yaml >>> @@ -58,6 +58,38 @@ properties: >>> items: >>> enum: [1, 2, 3, 4, 5] >>> >>> + qcom,tx-channel-mapping: >>> + description: | >>> + Specifies static channel mapping between slave and master tx port >>> + channels. >>> + In the order of slave port channels which is adc1, adc2, adc3, adc4, >>> + dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. >>> + ch_mask1 ==> bit mask value 1 >>> + ch_mask2 ==> bit mask value 2 >>> + ch_mask3 ==> bit mask value 4 >>> + ch_mask4 ==> bit mask value 8 >>> + $ref: /schemas/types.yaml#/definitions/uint8-array >>> + minItems: 8 >>> + maxItems: 13 >> >> Why size is variable? This device has fixed amount of slave ports, I >> think. >> > > yes will check modify > >>> + items: >>> + enum: [1, 2, 4, 8] >> >> What is the point of using bits if you cannot actually create a bit mask >> out of it? Why this cannot be 7? >> > Actually, these values should be fixed: 1 (0001), 2 (0010), 4(0100), > 8(1000). What is fixed here? I asked why these look like bitmasks but they cannot be used as bitmask. This is a mapping, so index is channel slave port channel number and the value is master port channel number, no? > > > If required to set 7, it is handled in wcd driver based on mixer commands. > https://elixir.bootlin.com/linux/v6.12-rc5/source/sound/soc/codecs/wcd937x.c#L1199 I talk about binding. Why you are not allowing value of 7 if this is a mask? If this is not a mask - property says it is channel mapping - then these should be [1-4]. > > > Example: > WCD937X_HPH_L -> channel mask value is 1 > WCD937X_HPH_R -> channel mask value is 2 > > > The final channel mask for that specific port is 3 >>> + >>> + qcom,rx-channel-mapping: >>> + description: | >>> + Specifies static channels mapping between slave and master rx port >>> + channels. >>> + In the order of slave port channels, which is >>> + hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. >>> + ch_mask1 ==> bit mask value 1 >>> + ch_mask2 ==> bit mask value 2 >>> + ch_mask3 ==> bit mask value 4 >>> + ch_mask4 ==> bit mask value 8 >> >> and the value is what exactly? Index is channel, but what does "ch_mask4 ==> bit >> mask value 8" mean? I don't understand this at all. >> > > Master > +--------------+ > | +--------+ | > ADC1 ----->| | PORT1 | | > ADC2 ----->| | | | > | +--------+ | > | | > ADC3 ----->| +--------+ | > | | PORT2 | | > | | | | > | +--------+ | > | | > | +--------+ | > DMIC0...DMIC3 ---->| | PORT3 | | > | | | | > | +--------+ | > | | > | +--------+ | > DMIC4...DMIC7----->| | PORT4 | | > | | | | > | +--------+ | > | | > +------------- + > > > The PORT1 has 2 ADC connections, > > ADC1 -> PORT1 ch_mask index 1 -> channel mask value 1 (0001) > ADC2 -> PORT1 ch_mask index 2 -> channel mask value 2 (0010) > > > DMIC0 -> PORT3 ch_mask index 1 -> channel mask value 1 (0001) > DMIC1 -> PORT3 ch_mask index 2 -> channel mask value 2 (0010) > DMIC2 -> PORT3 ch_mask index 3 -> channel mask value 4 (0100) > DMIC3 -> PORT3 ch_mask index 4 -> channel mask value 8 (1000) > > > Will check and add a proper description. Best regards, Krzysztof