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Tue, 02 Aug 2022 03:25:51 -0700 (PDT) Received: from [192.168.1.6] ([213.161.169.44]) by smtp.gmail.com with ESMTPSA id c22-20020a056512239600b0048af7e58c9dsm800641lfv.278.2022.08.02.03.25.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Aug 2022 03:25:51 -0700 (PDT) Message-ID: <08b60fe9-6e89-b10e-dcfa-5a0d53912676@linaro.org> Date: Tue, 2 Aug 2022 12:25:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH v2 2/3] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers Content-Language: en-US To: Naga Sureshkumar Relli , broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor.dooley@microchip.com Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220802070518.855951-1-nagasuresh.relli@microchip.com> <20220802070518.855951-3-nagasuresh.relli@microchip.com> From: Krzysztof Kozlowski In-Reply-To: <20220802070518.855951-3-nagasuresh.relli@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org On 02/08/2022 09:05, Naga Sureshkumar Relli wrote: > + > + qspi->clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(qspi->clk)) { > + dev_err(&pdev->dev, "clock not found.\n"); Same comments as v1. > + ret = PTR_ERR(qspi->clk); > + goto remove_master; > + } > + > + ret = clk_prepare_enable(qspi->clk); > + if (ret) { > + dev_err(&pdev->dev, "failed to enable clock\n"); > + goto remove_master; > + } > + > + init_completion(&qspi->data_completion); > + mutex_init(&qspi->op_lock); > + > + qspi->irq = platform_get_irq(pdev, 0); > + if (qspi->irq <= 0) { > + ret = qspi->irq; > + goto clk_dis_all; > + } > + > + ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr, > + IRQF_SHARED, pdev->name, qspi); > + if (ret) { > + dev_err(&pdev->dev, "request_irq failed %d\n", ret); > + goto clk_dis_all; > + } > + > + ctlr->bits_per_word_mask = SPI_BPW_MASK(8); > + ctlr->mem_ops = &mchp_coreqspi_mem_ops; > + ctlr->setup = mchp_coreqspi_setup_op; > + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | > + SPI_TX_DUAL | SPI_TX_QUAD; > + ctlr->dev.of_node = np; > + > + ret = devm_spi_register_controller(&pdev->dev, ctlr); > + if (ret) { > + dev_err(&pdev->dev, "spi_register_controller failed\n"); > + goto clk_dis_all; > + } > + > + return 0; > + > +clk_dis_all: > + clk_disable_unprepare(qspi->clk); > +remove_master: > + spi_controller_put(ctlr); > + > + return ret; > +} > + > +static int mchp_coreqspi_remove(struct platform_device *pdev) > +{ > + struct mchp_coreqspi *qspi = platform_get_drvdata(pdev); > + u32 control = readl_relaxed(qspi->regs + REG_CONTROL); > + > + mchp_coreqspi_disable_ints(qspi); > + control &= ~CONTROL_ENABLE; > + writel_relaxed(control, qspi->regs + REG_CONTROL); > + clk_disable_unprepare(qspi->clk); > + > + return 0; > +} > + > +/* > + * Platform driver data structure Same comments as v1. > + */ > +static const struct of_device_id mchp_coreqspi_of_match[] = { > + { .compatible = "microchip,mpfs-qspi" }, > + { .compatible = "microchip,coreqspi-rtl-v2" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, mchp_coreqspi_of_match); > + Best regards, Krzysztof