From: Florian Fainelli <florian@openwrt.org>
To: ralf@linux-mips.org
Cc: linux-mips@linux-mips.org, grant.likely@secretlab.ca,
spi-devel-general@lists.sourceforge.net,
Florian Fainelli <florian@openwrt.org>
Subject: [PATCH 1/9 v3] MIPS: BCM63XX: add IRQ_SPI and CPU specific SPI IRQ values
Date: Tue, 31 Jan 2012 15:10:40 +0100 [thread overview]
Message-ID: <1328019048-5892-2-git-send-email-florian@openwrt.org> (raw)
In-Reply-To: <1328019048-5892-1-git-send-email-florian@openwrt.org>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
No changes in v1 and v2
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 5b8d15b..9975727 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -478,6 +478,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
*/
enum bcm63xx_irq {
IRQ_TIMER = 0,
+ IRQ_SPI,
IRQ_UART0,
IRQ_UART1,
IRQ_DSL,
@@ -509,6 +510,7 @@ enum bcm63xx_irq {
* 6338 irqs
*/
#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6338_UART1_IRQ 0
#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
@@ -539,6 +541,7 @@ enum bcm63xx_irq {
* 6345 irqs
*/
#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6345_SPI_IRQ 0
#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6345_UART1_IRQ 0
#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
@@ -569,6 +572,7 @@ enum bcm63xx_irq {
* 6348 irqs
*/
#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6348_UART1_IRQ 0
#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -599,6 +603,7 @@ enum bcm63xx_irq {
* 6358 irqs
*/
#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
@@ -638,6 +643,7 @@ enum bcm63xx_irq {
#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -677,6 +683,7 @@ extern const int *bcm63xx_irqs;
#define __GEN_CPU_IRQ_TABLE(__cpu) \
[IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
+ [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
[IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
[IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
[IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
--
1.7.5.4
next prev parent reply other threads:[~2012-01-31 14:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-31 14:10 [PATCH 0/9 v3] MIPS: BCM63XX: add support for SPI Florian Fainelli
2012-01-31 14:10 ` Florian Fainelli [this message]
2012-01-31 14:10 ` [PATCH 2/9 v3] MIPS: BCM63XX: define BCM6358 SPI base address Florian Fainelli
2012-01-31 14:10 ` [PATCH 3/9 v3] MIPS: BCM63XX: add BCM6368 SPI clock mask Florian Fainelli
2012-01-31 14:10 ` [PATCH 4/9 v3] MIPS: BCM63XX: define SPI register sizes Florian Fainelli
2012-01-31 14:10 ` [PATCH 5/9 v3] MIPS: BCM63XX: remove SPI2 register Florian Fainelli
2012-01-31 14:10 ` [PATCH 6/9 v3] MIPS: BCM63XX: define internal registers offsets of the SPI controller Florian Fainelli
2012-01-31 14:10 ` [PATCH 7/9 v3] MIPS: BCM63XX: add stub to register the SPI platform driver Florian Fainelli
2012-01-31 14:10 ` [PATCH 8/9 v3] MIPS: BCM63XX: make board setup code register the spi platform device Florian Fainelli
2012-01-31 14:10 ` [PATCH 9/9 v3] spi: add Broadcom BCM63xx SPI controller driver Florian Fainelli
[not found] ` <1328019048-5892-10-git-send-email-florian-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2012-01-31 17:52 ` Shubhrajyoti Datta
2012-02-01 10:14 ` [PATCH v4] " Florian Fainelli
2012-02-01 11:22 ` Maxime Bizon
[not found] ` <1328091249-10389-1-git-send-email-florian-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2012-03-09 22:04 ` Grant Likely
2012-03-12 8:25 ` Florian Fainelli
2012-01-31 20:19 ` [PATCH 9/9 v3] " Grant Likely
[not found] ` <20120131201922.GE22611-e0URQFbLeQY2iJbIjFUEsiwD8/FfD2ys@public.gmane.org>
2012-01-31 21:20 ` Florian Fainelli
[not found] ` <201201312220.41561.florian-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2012-01-31 21:59 ` Grant Likely
[not found] ` <1328019048-5892-1-git-send-email-florian-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2012-05-30 10:04 ` [PATCH 0/9 v3] MIPS: BCM63XX: add support for SPI Florian Fainelli
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1328019048-5892-2-git-send-email-florian@openwrt.org \
--to=florian@openwrt.org \
--cc=grant.likely@secretlab.ca \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=spi-devel-general@lists.sourceforge.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).