[PATCH V2 0/3] SoC and board integration for QSPI on r8a7791/koelsch

[PATCH V2 0/3] SoC and board integration for QSPI on r8a7791/koelsch

[Geert Uytterhoeven]

This series adds support for the Spansion s25fl512s SPI FLASH on the
r8a7791-based Koelsch board. It is based on
renesas-devel-v3.13-rc7-20140109v2, with Valentine's i2c pinctrl and
Laurent's SCIF DT work applied on top.
[Simon: I don't know in which order you will merge these. If you want me
 to rebase my patches, just ask! Thanks!]

This applies to non-multiplatform Koelsch only.  Multi-platform Koelsch
support will be added in a separate series.

    [1/4] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
    [2/4] ARM: shmobile: r8a7791: add QSPI clocks
    [3/4] ARM: shmobile: koelsch: Add QSPI support
    [4/4] ARM: shmobile: koelsch: Enable RSPI and MTD_M25P80 in

Changes in V2:
  - Split QSPI pins in 2 sets of 3 pin groups
  - Add "[PATCH V2 4/4] ARM: shmobile: koelsch: Enable RSPI and MTD_M25P80
    in defconfig"

Thanks!

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH V2 1/4] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>

A QSPI function set consists of 3 groups:
  - qspi_ctrl (2 control wires)
  - qspi_data2 (2 data wires, for Single/Dual SPI)
  - qspi_data4 (4 data wires, for Quad SPI)

Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
Cc: Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
V2:
  - Split in 2 sets of 3 pin groups

 drivers/pinctrl/sh-pfc/pfc-r8a7791.c |   63 ++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 654bef369ab8..0ac8264440df 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -2135,6 +2135,53 @@ static const unsigned int msiof2_tx_pins[] = {
 static const unsigned int msiof2_tx_mux[] = {
 	MSIOF2_TXD_MARK,
 };
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_ctrl_mux[] = {
+	SPCLK_MARK, SSL_MARK,
+};
+static const unsigned int qspi_data2_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int qspi_data2_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK,
+};
+static const unsigned int qspi_data4_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+	RCAR_GP_PIN(1, 8),
+};
+static const unsigned int qspi_data4_mux[] = {
+	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
+};
+
+static const unsigned int qspi_ctrl_b_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int qspi_ctrl_b_mux[] = {
+	SPCLK_B_MARK, SSL_B_MARK,
+};
+static const unsigned int qspi_data2_b_pins[] = {
+	/* MOSI_IO0, MISO_IO1 */
+	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
+};
+static const unsigned int qspi_data2_b_mux[] = {
+	MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
+};
+static const unsigned int qspi_data4_b_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
+	RCAR_GP_PIN(6, 4),
+};
+static const unsigned int qspi_data4_b_mux[] = {
+	SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
+	IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
+};
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX, TX */
@@ -2877,6 +2924,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(msiof2_ss2),
 	SH_PFC_PIN_GROUP(msiof2_rx),
 	SH_PFC_PIN_GROUP(msiof2_tx),
+	SH_PFC_PIN_GROUP(qspi_ctrl),
+	SH_PFC_PIN_GROUP(qspi_data2),
+	SH_PFC_PIN_GROUP(qspi_data4),
+	SH_PFC_PIN_GROUP(qspi_ctrl_b),
+	SH_PFC_PIN_GROUP(qspi_data2_b),
+	SH_PFC_PIN_GROUP(qspi_data4_b),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_data_b),
 	SH_PFC_PIN_GROUP(scif0_data_c),
@@ -3074,6 +3127,15 @@ static const char * const msiof2_groups[] = {
 	"msiof2_tx",
 };
 
+static const char * const qspi_groups[] = {
+	"qspi_ctrl",
+	"qspi_data2",
+	"qspi_data4",
+	"qspi_ctrl_b",
+	"qspi_data2_b",
+	"qspi_data4_b",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_data_b",
@@ -3230,6 +3292,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(msiof0),
 	SH_PFC_FUNCTION(msiof1),
 	SH_PFC_FUNCTION(msiof2),
+	SH_PFC_FUNCTION(qspi),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif2),
-- 
1.7.9.5

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[PATCH V2 2/4] ARM: shmobile: r8a7791: add QSPI clocks

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>

The QSPI clock divider value depends on the MD1, MD2, and MD3 mode
switches.

Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
---
V2:
  - No changes

 arch/arm/mach-shmobile/clock-r8a7791.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index ca01dfe5f656..1185e5669a5e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -101,6 +101,7 @@ static struct clk main_clk = {
  */
 SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
 SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);
 
 /* fixed ratio clock */
 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
@@ -123,6 +124,7 @@ static struct clk *main_clks[] = {
 	&pll3_clk,
 	&hp_clk,
 	&p_clk,
+	&qspi_clk,
 	&rclk_clk,
 	&mp_clk,
 	&cp_clk,
@@ -133,6 +135,7 @@ static struct clk *main_clks[] = {
 /* MSTP */
 enum {
 	MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
+	MSTP917,
 	MSTP813,
 	MSTP811, MSTP810, MSTP809,
 	MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
@@ -151,6 +154,7 @@ static struct clk mstp_clks[MSTP_NR] = {
 	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
 	[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
 	[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
+	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
 	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
 	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
 	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
@@ -189,6 +193,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_CON_ID("zg",		&zg_clk),
 	CLKDEV_CON_ID("hp",		&hp_clk),
 	CLKDEV_CON_ID("p",		&p_clk),
+	CLKDEV_CON_ID("qspi",		&qspi_clk),
 	CLKDEV_CON_ID("rclk",		&rclk_clk),
 	CLKDEV_CON_ID("mp",		&mp_clk),
 	CLKDEV_CON_ID("cp",		&cp_clk),
@@ -214,6 +219,7 @@ static struct clk_lookup lookups[] = {
 	CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
 	CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
 	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+	CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
 	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 	CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
@@ -263,6 +269,11 @@ void __init r8a7791_clock_init(void)
 		break;
 	}
 
+	if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+	else
+		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
 	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 		ret = clk_register(main_clks[k]);
 
-- 
1.7.9.5

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[PATCH V2 3/4] ARM: shmobile: koelsch: Add QSPI support

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>

Enable support for the Spansion s25fl512s SPI FLASH on the Koelsch board:
  - Add QSPI platform device, resources, platform data, and pinmux,
  - Add FLASH data and MTD partitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
---
V2:
  - Split in 2 groups (qspi_ctrl/qspi_data4)

 arch/arm/mach-shmobile/board-koelsch.c |   64 ++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index de7cc64b1f37..37e4a6fd36b3 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -25,12 +25,17 @@
 #include <linux/input.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/rcar-du.h>
 #include <linux/platform_device.h>
 #include <linux/sh_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7791.h>
@@ -148,6 +153,55 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
 	.nbuttons	= ARRAY_SIZE(gpio_buttons),
 };
 
+/* QSPI */
+static const struct resource qspi_resources[] __initconst = {
+	DEFINE_RES_MEM(0xe6b10000, 0x1000),
+	DEFINE_RES_IRQ(gic_spi(184)),
+};
+
+static const struct rspi_plat_data qspi_pdata __initconst = {
+	.num_chipselect = 1,
+};
+
+/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
+static struct mtd_partition spi_flash_part[] = {
+	{
+		.name		= "loader",
+		.offset		= 0x00000000,
+		.size		= 512 * 1024,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	{
+		.name		= "bootenv",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= 512 * 1024,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	{
+		.name		= "data",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= MTDPART_SIZ_FULL,
+	},
+};
+
+static const struct flash_platform_data spi_flash_data = {
+	.name		= "m25p80",
+	.parts		= spi_flash_part,
+	.nr_parts	= ARRAY_SIZE(spi_flash_part),
+	.type		= "s25fl512s",
+};
+
+static const struct spi_board_info spi_info[] __initconst = {
+	{
+		.modalias	= "m25p80",
+		.platform_data	= &spi_flash_data,
+		.mode		= SPI_MODE_0,
+		.max_speed_hz	= 30000000,
+		.bus_num	= 0,
+		.chip_select	= 0,
+	},
+};
+
 static const struct pinctrl_map koelsch_pinctrl_map[] = {
 	/* DU */
 	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
@@ -165,6 +219,11 @@ static const struct pinctrl_map koelsch_pinctrl_map[] = {
 				  "eth_rmii", "eth"),
 	PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
 				  "intc_irq0", "intc"),
+	/* QSPI */
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
+				  "qspi_ctrl", "qspi"),
+	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
+				  "qspi_data4", "qspi"),
 	/* SCIF0 (CN19: DEBUG SERIAL0) */
 	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
 				  "scif0_data_d", "scif0"),
@@ -190,6 +249,11 @@ static void __init koelsch_add_standard_devices(void)
 	platform_device_register_data(&platform_bus, "gpio-keys", -1,
 				      &koelsch_keys_pdata,
 				      sizeof(koelsch_keys_pdata));
+	platform_device_register_resndata(&platform_bus, "qspi", 0,
+					  qspi_resources,
+					  ARRAY_SIZE(qspi_resources),
+					  &qspi_pdata, sizeof(qspi_pdata));
+	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
 
 	koelsch_add_du_device();
 }
-- 
1.7.9.5

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[PATCH V2 4/4] ARM: shmobile: koelsch: Enable RSPI and MTD_M25P80 in defconfig

[Geert Uytterhoeven]

From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>

This enables support for the Spansion s25fl512s SPI FLASH on QSPI.

Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
---
V2:
  - No changes

 arch/arm/configs/koelsch_defconfig |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index f795ea42a8fc..8f283f725a12 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -36,6 +36,8 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_ARC is not set
 # CONFIG_NET_CADENCE is not set
@@ -58,6 +60,8 @@ CONFIG_SH_ETH=y
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=20
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_SPI_RSPI=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
-- 
1.7.9.5

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Re: [PATCH V2 1/4] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Sunday 12 January 2014 12:00:30 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
> 
> A QSPI function set consists of 3 groups:
>   - qspi_ctrl (2 control wires)
>   - qspi_data2 (2 data wires, for Single/Dual SPI)
>   - qspi_data4 (4 data wires, for Quad SPI)
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
> Cc: Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Acked-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

and applied to my tree.

> ---
> V2:
>   - Split in 2 sets of 3 pin groups
> 
>  drivers/pinctrl/sh-pfc/pfc-r8a7791.c |   63
> ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 654bef369ab8..0ac8264440df
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> @@ -2135,6 +2135,53 @@ static const unsigned int msiof2_tx_pins[] = {
>  static const unsigned int msiof2_tx_mux[] = {
>  	MSIOF2_TXD_MARK,
>  };
> +/* - QSPI
> ------------------------------------------------------------------- */
> +static const unsigned int qspi_ctrl_pins[] = {
> +	/* SPCLK, SSL */
> +	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
> +};
> +static const unsigned int qspi_ctrl_mux[] = {
> +	SPCLK_MARK, SSL_MARK,
> +};
> +static const unsigned int qspi_data2_pins[] = {
> +	/* MOSI_IO0, MISO_IO1 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
> +};
> +static const unsigned int qspi_data2_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK,
> +};
> +static const unsigned int qspi_data4_pins[] = {
> +	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
> +	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
> +	RCAR_GP_PIN(1, 8),
> +};
> +static const unsigned int qspi_data4_mux[] = {
> +	MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
> +};
> +
> +static const unsigned int qspi_ctrl_b_pins[] = {
> +	/* SPCLK, SSL */
> +	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
> +};
> +static const unsigned int qspi_ctrl_b_mux[] = {
> +	SPCLK_B_MARK, SSL_B_MARK,
> +};
> +static const unsigned int qspi_data2_b_pins[] = {
> +	/* MOSI_IO0, MISO_IO1 */
> +	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
> +};
> +static const unsigned int qspi_data2_b_mux[] = {
> +	MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
> +};
> +static const unsigned int qspi_data4_b_pins[] = {
> +	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
> +	RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
> +	RCAR_GP_PIN(6, 4),
> +};
> +static const unsigned int qspi_data4_b_mux[] = {
> +	SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
> +	IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
> +};
>  /* - SCIF0
> ------------------------------------------------------------------ */
> static const unsigned int scif0_data_pins[] = {
>  	/* RX, TX */
> @@ -2877,6 +2924,12 @@ static const struct sh_pfc_pin_group pinmux_groups[]
> = { SH_PFC_PIN_GROUP(msiof2_ss2),
>  	SH_PFC_PIN_GROUP(msiof2_rx),
>  	SH_PFC_PIN_GROUP(msiof2_tx),
> +	SH_PFC_PIN_GROUP(qspi_ctrl),
> +	SH_PFC_PIN_GROUP(qspi_data2),
> +	SH_PFC_PIN_GROUP(qspi_data4),
> +	SH_PFC_PIN_GROUP(qspi_ctrl_b),
> +	SH_PFC_PIN_GROUP(qspi_data2_b),
> +	SH_PFC_PIN_GROUP(qspi_data4_b),
>  	SH_PFC_PIN_GROUP(scif0_data),
>  	SH_PFC_PIN_GROUP(scif0_data_b),
>  	SH_PFC_PIN_GROUP(scif0_data_c),
> @@ -3074,6 +3127,15 @@ static const char * const msiof2_groups[] = {
>  	"msiof2_tx",
>  };
> 
> +static const char * const qspi_groups[] = {
> +	"qspi_ctrl",
> +	"qspi_data2",
> +	"qspi_data4",
> +	"qspi_ctrl_b",
> +	"qspi_data2_b",
> +	"qspi_data4_b",
> +};
> +
>  static const char * const scif0_groups[] = {
>  	"scif0_data",
>  	"scif0_data_b",
> @@ -3230,6 +3292,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(msiof0),
>  	SH_PFC_FUNCTION(msiof1),
>  	SH_PFC_FUNCTION(msiof2),
> +	SH_PFC_FUNCTION(qspi),
>  	SH_PFC_FUNCTION(scif0),
>  	SH_PFC_FUNCTION(scif1),
>  	SH_PFC_FUNCTION(scif2),
-- 
Regards,

Laurent Pinchart

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Re: [PATCH V2 2/4] ARM: shmobile: r8a7791: add QSPI clocks

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Sunday 12 January 2014 12:00:31 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>
> 
> The QSPI clock divider value depends on the MD1, MD2, and MD3 mode
> switches.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org>

Acked-by: Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org>

> ---
> V2:
>   - No changes
> 
>  arch/arm/mach-shmobile/clock-r8a7791.c |   11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c
> b/arch/arm/mach-shmobile/clock-r8a7791.c index ca01dfe5f656..1185e5669a5e
> 100644
> --- a/arch/arm/mach-shmobile/clock-r8a7791.c
> +++ b/arch/arm/mach-shmobile/clock-r8a7791.c
> @@ -101,6 +101,7 @@ static struct clk main_clk = {
>   */
>  SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
>  SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
> +SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);
> 
>  /* fixed ratio clock */
>  SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
> @@ -123,6 +124,7 @@ static struct clk *main_clks[] = {
>  	&pll3_clk,
>  	&hp_clk,
>  	&p_clk,
> +	&qspi_clk,
>  	&rclk_clk,
>  	&mp_clk,
>  	&cp_clk,
> @@ -133,6 +135,7 @@ static struct clk *main_clks[] = {
>  /* MSTP */
>  enum {
>  	MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
> +	MSTP917,
>  	MSTP813,
>  	MSTP811, MSTP810, MSTP809,
>  	MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
> @@ -151,6 +154,7 @@ static struct clk mstp_clks[MSTP_NR] = {
>  	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3
> */ [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4
> */ [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5
> */ +	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), 
/*
> QSPI */ [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /*
> Ether */ [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0),
> /* VIN0 */ [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8,
> 0), /* VIN1 */ @@ -189,6 +193,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_CON_ID("zg",		&zg_clk),
>  	CLKDEV_CON_ID("hp",		&hp_clk),
>  	CLKDEV_CON_ID("p",		&p_clk),
> +	CLKDEV_CON_ID("qspi",		&qspi_clk),
>  	CLKDEV_CON_ID("rclk",		&rclk_clk),
>  	CLKDEV_CON_ID("mp",		&mp_clk),
>  	CLKDEV_CON_ID("cp",		&cp_clk),
> @@ -214,6 +219,7 @@ static struct clk_lookup lookups[] = {
>  	CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
>  	CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
>  	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
> +	CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
>  	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
>  	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
>  	CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
> @@ -263,6 +269,11 @@ void __init r8a7791_clock_init(void)
>  		break;
>  	}
> 
> +	if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
> +		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
> +	else
> +		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
> +
>  	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
>  		ret = clk_register(main_clks[k]);
-- 
Regards,

Laurent Pinchart

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Re: [PATCH V2 3/4] ARM: shmobile: koelsch: Add QSPI support

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Sunday 12 January 2014 12:00:32 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> 
> Enable support for the Spansion s25fl512s SPI FLASH on the Koelsch board:
>   - Add QSPI platform device, resources, platform data, and pinmux,
>   - Add FLASH data and MTD partitions.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>

Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

> ---
> V2:
>   - Split in 2 groups (qspi_ctrl/qspi_data4)
> 
>  arch/arm/mach-shmobile/board-koelsch.c |   64
> ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+)
> 
> diff --git a/arch/arm/mach-shmobile/board-koelsch.c
> b/arch/arm/mach-shmobile/board-koelsch.c index de7cc64b1f37..37e4a6fd36b3
> 100644
> --- a/arch/arm/mach-shmobile/board-koelsch.c
> +++ b/arch/arm/mach-shmobile/board-koelsch.c
> @@ -25,12 +25,17 @@
>  #include <linux/input.h>
>  #include <linux/kernel.h>
>  #include <linux/leds.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/partitions.h>
>  #include <linux/phy.h>
>  #include <linux/pinctrl/machine.h>
>  #include <linux/platform_data/gpio-rcar.h>
>  #include <linux/platform_data/rcar-du.h>
>  #include <linux/platform_device.h>
>  #include <linux/sh_eth.h>
> +#include <linux/spi/flash.h>
> +#include <linux/spi/rspi.h>
> +#include <linux/spi/spi.h>
>  #include <mach/common.h>
>  #include <mach/irqs.h>
>  #include <mach/r8a7791.h>
> @@ -148,6 +153,55 @@ static const struct gpio_keys_platform_data
> koelsch_keys_pdata __initconst = { .nbuttons	= ARRAY_SIZE(gpio_buttons),
>  };
> 
> +/* QSPI */
> +static const struct resource qspi_resources[] __initconst = {
> +	DEFINE_RES_MEM(0xe6b10000, 0x1000),
> +	DEFINE_RES_IRQ(gic_spi(184)),
> +};
> +
> +static const struct rspi_plat_data qspi_pdata __initconst = {
> +	.num_chipselect = 1,
> +};
> +
> +/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
> +static struct mtd_partition spi_flash_part[] = {
> +	{
> +		.name		= "loader",
> +		.offset		= 0x00000000,
> +		.size		= 512 * 1024,
> +		.mask_flags	= MTD_WRITEABLE,
> +	},
> +	{
> +		.name		= "bootenv",
> +		.offset		= MTDPART_OFS_APPEND,
> +		.size		= 512 * 1024,
> +		.mask_flags	= MTD_WRITEABLE,
> +	},
> +	{
> +		.name		= "data",
> +		.offset		= MTDPART_OFS_APPEND,
> +		.size		= MTDPART_SIZ_FULL,
> +	},
> +};
> +
> +static const struct flash_platform_data spi_flash_data = {
> +	.name		= "m25p80",
> +	.parts		= spi_flash_part,
> +	.nr_parts	= ARRAY_SIZE(spi_flash_part),
> +	.type		= "s25fl512s",
> +};
> +
> +static const struct spi_board_info spi_info[] __initconst = {
> +	{
> +		.modalias	= "m25p80",
> +		.platform_data	= &spi_flash_data,
> +		.mode		= SPI_MODE_0,
> +		.max_speed_hz	= 30000000,
> +		.bus_num	= 0,
> +		.chip_select	= 0,
> +	},
> +};
> +
>  static const struct pinctrl_map koelsch_pinctrl_map[] = {
>  	/* DU */
>  	PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
> @@ -165,6 +219,11 @@ static const struct pinctrl_map koelsch_pinctrl_map[] =
> { "eth_rmii", "eth"),
>  	PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
>  				  "intc_irq0", "intc"),
> +	/* QSPI */
> +	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
> +				  "qspi_ctrl", "qspi"),
> +	PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791",
> +				  "qspi_data4", "qspi"),
>  	/* SCIF0 (CN19: DEBUG SERIAL0) */
>  	PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
>  				  "scif0_data_d", "scif0"),
> @@ -190,6 +249,11 @@ static void __init koelsch_add_standard_devices(void)
>  	platform_device_register_data(&platform_bus, "gpio-keys", -1,
>  				      &koelsch_keys_pdata,
>  				      sizeof(koelsch_keys_pdata));
> +	platform_device_register_resndata(&platform_bus, "qspi", 0,
> +					  qspi_resources,
> +					  ARRAY_SIZE(qspi_resources),
> +					  &qspi_pdata, sizeof(qspi_pdata));
> +	spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
> 
>  	koelsch_add_du_device();
>  }
-- 
Regards,

Laurent Pinchart

Re: [PATCH V2 0/3] SoC and board integration for QSPI on r8a7791/koelsch

[Simon Horman]

On Sun, Jan 12, 2014 at 12:00:29PM +0100, Geert Uytterhoeven wrote:
> This series adds support for the Spansion s25fl512s SPI FLASH on the
> r8a7791-based Koelsch board. It is based on
> renesas-devel-v3.13-rc7-20140109v2, with Valentine's i2c pinctrl and
> Laurent's SCIF DT work applied on top.
> [Simon: I don't know in which order you will merge these. If you want me
>  to rebase my patches, just ask! Thanks!]

I see that Laruent has taken patch 1/4.

Is it possible for me to merge patches 2-4/4 independently of that patch?
That is, can I apply them and still produce a kernel that boots. If so,
that is my preferred option. If not I will talk to Laurent about a branch
to base things on.

Also, I would like to get an Ack from Magnus.

> 
> This applies to non-multiplatform Koelsch only.  Multi-platform Koelsch
> support will be added in a separate series.
> 
>     [1/4] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
>     [2/4] ARM: shmobile: r8a7791: add QSPI clocks
>     [3/4] ARM: shmobile: koelsch: Add QSPI support
>     [4/4] ARM: shmobile: koelsch: Enable RSPI and MTD_M25P80 in
> 
> Changes in V2:
>   - Split QSPI pins in 2 sets of 3 pin groups
>   - Add "[PATCH V2 4/4] ARM: shmobile: koelsch: Enable RSPI and MTD_M25P80
>     in defconfig"
> 
> Thanks!
> 
> Gr{oetje,eeting}s,
> 
> 						Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> 							    -- Linus Torvalds
> 

Re: [PATCH V2 0/3] SoC and board integration for QSPI on r8a7791/koelsch

[Geert Uytterhoeven]

Hi Simon,

On Tue, Jan 14, 2014 at 1:46 AM, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> On Sun, Jan 12, 2014 at 12:00:29PM +0100, Geert Uytterhoeven wrote:
>> This series adds support for the Spansion s25fl512s SPI FLASH on the
>> r8a7791-based Koelsch board. It is based on
>> renesas-devel-v3.13-rc7-20140109v2, with Valentine's i2c pinctrl and
>> Laurent's SCIF DT work applied on top.
>> [Simon: I don't know in which order you will merge these. If you want me
>>  to rebase my patches, just ask! Thanks!]
>
> I see that Laruent has taken patch 1/4.
>
> Is it possible for me to merge patches 2-4/4 independently of that patch?
> That is, can I apply them and still produce a kernel that boots. If so,
> that is my preferred option. If not I will talk to Laurent about a branch
> to base things on.

Yes you can. Note that RSPI still won't be enabled without "spi: rspi: Remove
dependency on DMAE for SHMOBILE" (which has now landed in the spi tree).
And with that patch applied, you'll get warnings like:

    pinmux core: sh-pfc does not support function qspi
    sh-pfc pfc-r8a7791: invalid function qspi in map table
    pinmux core: sh-pfc does not support function qspi
    sh-pfc pfc-r8a7791: invalid function qspi in map table

which are harmless, and spi will still work, as that's the default pin config
anyway.

> Also, I would like to get an Ack from Magnus.

Sure.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Re: [PATCH V2 0/3] SoC and board integration for QSPI on r8a7791/koelsch

[Simon Horman]

On Tue, Jan 14, 2014 at 10:05:28AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Tue, Jan 14, 2014 at 1:46 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Sun, Jan 12, 2014 at 12:00:29PM +0100, Geert Uytterhoeven wrote:
> >> This series adds support for the Spansion s25fl512s SPI FLASH on the
> >> r8a7791-based Koelsch board. It is based on
> >> renesas-devel-v3.13-rc7-20140109v2, with Valentine's i2c pinctrl and
> >> Laurent's SCIF DT work applied on top.
> >> [Simon: I don't know in which order you will merge these. If you want me
> >>  to rebase my patches, just ask! Thanks!]
> >
> > I see that Laruent has taken patch 1/4.
> >
> > Is it possible for me to merge patches 2-4/4 independently of that patch?
> > That is, can I apply them and still produce a kernel that boots. If so,
> > that is my preferred option. If not I will talk to Laurent about a branch
> > to base things on.
> 
> Yes you can. Note that RSPI still won't be enabled without "spi: rspi: Remove
> dependency on DMAE for SHMOBILE" (which has now landed in the spi tree).
> And with that patch applied, you'll get warnings like:
> 
>     pinmux core: sh-pfc does not support function qspi
>     sh-pfc pfc-r8a7791: invalid function qspi in map table
>     pinmux core: sh-pfc does not support function qspi
>     sh-pfc pfc-r8a7791: invalid function qspi in map table
> 
> which are harmless, and spi will still work, as that's the default pin config
> anyway.

Thanks, that is perfectly fine.

> > Also, I would like to get an Ack from Magnus.
> 
> Sure.
> 
> Thanks!
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
>